Capp june 2012
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This document contains questions that appear to be from a Master's degree examination on computer architecture and parallel processing. It includes questions in two parts - Part A contains 10 short answer questions on topics like performance metrics for parallel systems, differences between network topologies, possibility of super-linear speedup, and lower bounds on optimal schedules. Part B contains 5 longer answer questions requiring explanations on models of parallel computation, classification schemes, crossbar switches, applications of parallel processing, caching policies, virtual memory systems, multiprocessor architectures, and matrix multiplication algorithms for SIMD models.
Capp june 2012
- 1. WWW.EQUESTIONPAPER.BLOGSPOT.IN 1 M.E. DEGREE EXAMINATION, JUNE 2012. Second Semester Applied Electronics AP 9222/248205/AP 9222/10244 AE 202— COMPUTER ARCHITECTURE AND PARALLEL PROCESSING (Common to M.E. VLSI Design, M.E. Computer and Communication and M.E. Embedded System Technologies) (Regulation 2009) Time: Three hours Maximum : 100 Marks Answer ALL Questions PART A — (10 × 2 = 20 Marks) 1. What are the metrics used for measuring the performance of parallel systems? 2. What is the difference between a binary K-cube and a cube connected network of degree K? 3. Is it possible for the average speedup exhibited by a parallel algorithm to be super linear? 4. Given a task graph and arbitrarily large number of processors, what is a lower bound on the length of an optimal schedule? 5. Name the various memory update policies. 6. What is the need for memory hierarchy? 7. What are the two types of data flow architecture? 8. Compare multi vector and SIMDD computers. 9. Name any two SIMD languages. 10. Differentiate between SIMD and SPMD programming.
- 2. WWW.EQUESTIONPAPER.BLOGSPOT.IN 2 PART B — (5 × 16 = 80 Marks) 11. (a) (i) Explain the PRAM and VLSI model of parallel computation. (8) (ii) List the conditions of parallelism. (8) Or (b) Discuss the various computer architectural classification schemes with suitable diagrams. (16) 12. (a) (i) Consider a PXM cross bar switch connecting O processors to m memory modules. Assume only one input AND gate and OR gate. Assume that all variables are available in true and complement forms. Estimate the number of gates in the switch. Assume the data width to be W bits. (8) (ii) List the parallel processing applications in various domains. (8) Or (b) Discuss the merits and demerits of various partitioning and scheduling techniques for parallel environment. (16) 13. (a) In a uniprocessor with cache, the processor issues its memory access requests to cache controller (CC). In case of miss or write through, CC interacts with memory controller (MC). Draw the flow charts describing the operation of CC for a read and a write operation for: (1) WBWA (2) WTWA (3) Write through without write allocation. (16) Or (b) Explain paged memory and memory with paged segments virtual memory system. (16) 14. (a) (i) Draw and explain the types of multiprocessor and multicomputer architectures. (10)
- 3. WWW.EQUESTIONPAPER.BLOGSPOT.IN 3 (ii) Draw the architecture of de Brigin networks and shuffle exchange networks. (6) Or (b) Discuss the merits and demerits of types of scalar, multithreaded and data flow architectures. (16) 15. (a) Write the matrix multiplication algorithm for 2-D mesh and hypercube SIMD models. (16) Or (b) Write the parallel constructs provided by any four languages with example. (16)