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ICSE 2008 Proc. 2008, Johor, Malaysia
Reliable Fast Detection Anti-collision Technique for RFID
System Implemented on Chip
Jahariah Sampe, Nonmember, IEEE and Masuri Othman, Member, IEEE
Department of Electrical, Electronics and System Faculty of Engineering,
Institute of Microengineering and Nanoelectronic,
Universiti Kebangsaan Malaysia
43600 Bangi, Selangor, MALAYSIA
Email:jahariah@yahoo.com
Abstract The paper presented a proposed
Reliable Fast Detection Anti-collision
Technique (RFDACT) for Radio Frequency
Identification (RFID) system. Our proposed
RFDACT is implemented on-chip using
Application Specific Integrated Circuit (ASIC)
technology. The RFDACT consists of two
main subsystems; PreFDACT and
PostFDACT. The PreFDACT detects any
error in the incoming messages. Then, the
identification bit (ID) of the error free packet
will be fed to the next subsystem. The
PostFDACT will identify the tag by using the
deterministic fast detection anti-collision
technique. The proposed system is designed
using Verilog HDL. The system is simulated
using Modelsim and synthesized using Xilinx
Synthesis Technology. The system has been
successfully implemented in hardware using
Field Programmable Grid Array (FPGA)
VirtexII. The output waveforms from the
FPGA are tested on the Tektronix Logic
Analyzer for real time verification. Finally the
RFDACT system is implemented on chip using
0.18 µm Library, Synopsys Compiler and
tools. The hardware verification result shows
the proposed system enables to identify the
tags at the operating frequency of 180 MHz
without error. The system’s chip is consumed
7.578mW powers, occupied 6,041 gates and
0.0375 mm2
area.
I. INTRODUCTION
THE Radio Frequency Identification (RFID)
system consists of three main components; reader,
tag and data management software. The reader is
to write instructions to and to read data from the
tags. The tags are to store data or unique
Identification bits (ID) and are basically attached
to the objects to be identified. During the data
transmission from the tags to the reader, there
might be an error. Therefore, a main role of the
Data link layer in the data management system is
to convert the unreliable physical link between
reader and tag into a reliable link. As a result the
RFID system employs the Cyclic Redundancy
Check (CRC) as an error detection scheme. The
CRC calculation consists of an iterative process
involving Exclusive-ORs and shift register which
is executed much faster in hardware compare in
software [10-11].
In addition an anti-collision technique is
required to coordinate the communication
between the reader and the multiple tags. The
common deterministic anti-collision techniques
are based on the Tree algorithm such as the Binary
Tree and the Query Tree algorithms [1-4]. In the
Binary Tree algorithm, the identification process
will firstly search the smallest tag’s ID until the
largest one follows the Binary Tree sequence.
Since this algorithm is a deterministic
anti-collision technique, the reader will control
the communication between the Tags. As a result
enable production of the tag with simple, small,
low cost and low power features. However the
drawback of the Binary Tree algorithm is its
identification time is dependent on two
parameters; the number of tags simultaneously
exists in the interrogation zone and the length of
tag’s ID. If either one of these parameters is
increased the identification time will increase.
Moreover this algorithm also requires the tags to
remember the previous instructions from the
reader during the communication process.
II. RFDACT ARCHITECTURE
Based on the Binary Tree anti-collision
algorithm, the Reliable Fast Detection
Anti-collision Technique (RFDACT) is proposed.
2491-4244-2561-7/08/$20.00 ©2008 IEEE

The proposed RFDACT is novel in terms of faster
identification time by reducing the number of
iterations needed to identify one tag. The
powered tags are divided into a group of four for
every Read cycle in order to reduce the number of
iterations during the identification process. In
addition, the identification time of the proposed
RFDACT does not dependent on the length of the
tag’s ID. Instead of sending and receiving the ID
bit by bit, the RFDACT will read all the ID bits at
once regardless of its length. This is performed by
using the word-by-word multiplexing or byte
interleaving. Meanwhile, this algorithm also does
not require the tags to remember the previous
instructions from the reader during the
identification process. The reader transmits the
read command to the tags and the tags will
simultaneously backscatter its’ ID bits. As a
result the tag is treated as an address carrying
device i.e. the tag only carries its identification
bits. Therefore, the memoryless tag which
exhibits very low power consumption can be
produced [3].
The RFDACT system is based on a Time
Division Multiplexing (TDM) operation.
Therefore three parameters are used to measure
the performance of the system; the maximum data
rate (N), the length of ID bits (n) and the number
of supported input/output lines (L). The
identification time for RFDACT system is same
regardless of the length of the tag’s ID and equal
to one System clock cycle (T). Therefore, the
relationship between the maximum data rate (N),
the length of ID bits (n), the access time (tacc) and
the number of input/output lines (L) is given by
the following equation [12].
acctL
n
N
×
= (1)
In order to increase the throughput of the primary
RFDACT system, the number of input/output
lines (channels) should be increased. But from
(1), it shows that if the data rate increases, the
number of supported lines will be decreased and
vice versa. Therefore, to increase the number of
lines supported by the system per read cycle
without decreasing the maximum data rate, a few
primary RFDACT modules should be
multiplexed.
Fig. 1 shows the block diagram of the RFDACT
system, which consist of two main subsystems;
PreRFDACT (front end) and PostRFDACT (back
end). The PreRFDACT subsystem as shown in
Fig. 1(a) is used to detect error in the incoming
messages. The CRC-generator module in this
subsystem employs the CRC16-CCITT standard
using the polynomial generator of X16
+ X12
+ X5
+1. Output from this subsystem which consist
only the ID of the active tags will be fed to the
next subsystem. The PostRFDACT subsystem as
shown in Fig. 1(b) will identify these tags’ ID by
using the Fast Detection anti-collision technique.
(a) Pre-RFDACT
(b) Post-RFDACT
Fig. 1 The subsystems of RFDACT system
In the PreRFDACT, the received messages are
fed into the CRC-remover module. In this module,
the received messages are separated into two; the
received packet and the received CRC. Then
these packet and CRC will be sent to the
CRC-checker module for a verification process.
The CRC-checker module will recalculate the
CRC of the received packet. Thus, the calculated
CRC are compared with the received CRC. If the
values are the same means no error, the statusbit is
set to its original value i.e. zero. Otherwise or
there are errors in the packet, the statusbit is set to
two. After that, this updated statusbit is appended
to its respective packet. Next the packet with the
updated status-bit is fed to the Status-checker
module. Finally the Status-checker module will
check the incoming packets whether have errors
or not. If there are errors, reset the slot of the
respective packet to zero value. Otherwise, fill the
slot of the packet with its respective ID. Hence,
the status-bit will be removed from its packet and
:
:
Data-value0
Status-Checker
Data-value3
:
CRC
Checker0
CRC-Remover
CRC
Checker3
Packet0
Pakcet3
Active0
Active3Clock
Reset
Messages
Tag clock
To monitor
(tag_out)
Improved
Fast-search
Read-Killtag
Reset
Clock
Clock Divider
Active0
Active3
To upper layer
(tag_kill)
Select
Generator
250

only the tag’s ID will be output to the
PostRFDACT.
In the PostRFDACT, the Fast-search module
will identify the four tag’s IDs simultaneously in
one Read cycle which equal to a Tag clock cycle.
The module will firstly identify the smallest ID
bits until the largest one follows the Binary Tree
with a maximum number of four leaves. Finally,
the identified tag will be killed by adding a bit ‘1’
to the most significant bit (MSB) of the tag’s ID
[9].
2.1 RFDACT modules
The proposed RFDACT system is designed using
Verilog HDL. The PreRFDACT system as shown
in Fig. 1(a) consists of Message-generator,
CRC-remover and Status-checker modules. Each
of these modules consist of a few submodules.
Message-generator module consists of
Packet-generator and CRC-generator submodules.
CRC-remover module consists of four
CRC-checker modules. CRC-checker module
consists of the CRC generator module and a
comparator. Status-checker module consists of
four Data-value submodules. All these modules
are synchronized to a system clock. The output of
this system which consist only the active tags’ ID
will become an input to the PostRFDACT system.
The PostRFDACT system as shown in Fig. 1(b)
consists of Fast-search, Read-killtag,
Clock-divider and Select-generator modules. All
these modules are also synchronized to a system
clock. In this subsystem there are two output
ports, the first port is to display the identified tags.
The other port is to acknowledge the successful
identified tags.
III. SIMULATION RESULTS
Verilog HDL codes for the RFDACT system
have been successfully simulated and verified
using the ModelSim XE II/Starter 5.7g tool. The
following will discuss the Behavioral simulation
waveforms for the selected ports in the RFDACT
system as shown in Fig. 2. At the first Read
cycle, for the received messages of 000C8584416,
0000550A516, 00010123116, and 0EA6093DF16,
the recalculated CRC of these messages are
584416, 50A516, 123116, and 93DF16 respectively.
As a result, the calculated CRCs are equal to the
received CRCs which is represented by the four
bit of the least significant bit (LSB) of the
messages. Since there are no errors in the received
messages, the statusbit of the packets are set to
zero, which are represented by the MSB of the
packets; 000C816, 0000516, 0001016 and 0EA6016
respectively. Finally, the ID of these packets will
be fed simultaneously to the PostRFDACT
system at the positive edge of the Tag clock.
(a) Output data from the PreRFDACT modules
(b) Output data form the PostRFDACT modules
Fig. 2 The Behavioral simulation of RFDACT
In the PostFDACT subsystem, the Fast-search
module will identify the four active tags
simultaneously starting from the smallest value to
the largest one. For examples, for the four input
tag’s ID of 00C816, 000516, 001016 and EA6016
will be identified as 00516, 001016, 00C816 and
EA6016 respectively. Then these identified tags
will be fed to the Read-killtag module
simultaneously at the negative edge of the Tag
clock. Finally, the Read-killtag Module will
output the four identified tags serially, one tag at
every cycle of the system clock starting from the
smallest tag’s ID to the largest one. Moreover, at
the same clock cycle, the identified tag will be
killed.
251

IV. IMPLEMENTATION AND VERIFICATION
The RFDACT system has been implemented in
hardware using the Field Programmable Grid
Array (FPGA) model Virtex II Xc2v250. The
output waveforms from the FPGA have been
displayed using the Tektronix Logic Analyzer
model TLA 5201 for real time verification. From
the result, it shows that the system still enables to
identify the tags at the operating frequency of 180
MHz without errors. This is the maximum
operating frequency of the used FPGA model.
The following will compare and discuss the
FPGA output and its respective Place-Route
Simulation output. This is purposely to verify the
correctness of the obtained FPGA output.
(a) FPGA output using Spectrum Analyzer
(b) Place-Route simulation output
Fig. 3 Output at the operating frequency of 40 MHz
Fig. 3(a) shows the FPGA output at the
operating frequency of 40 MHz and the threshold
voltage of 1.25V. The figure consists of two
portions; the upper and the bottom which
represent the low and the high sampling rate
waveforms respectively. For each portion the A3
represents the eight MSB of the tag’s ID and the
A2 represents the eight LSB of the tag’s ID. Fig.
3(b) is the equivalent Place-Route simulation
output of Fig. 3(a). For examples for both outputs,
the identified tags at the first Read cycle are
0D5916, 356016, 6B6816 and 8A5016. For the
second Read cycle, the identified tags are 0D5A16,
356416, 6B7016 and 8A5C16 etc. From the
comparison results, it shows that the RFDACA
system is correctly identified the tags at this
operating frequency.
Since the RFDACT system is successfully
implemented in hardware using FPGA with
desired performances. Then the system is
implemented on chip using ASIC approach. In
this approach the system is resynthesized using
0.18µm Library, Synopsys Compiler and tools. In
ASIC the most critical step is to determine the
design constraint parameters for the synthesis.
The chosen constraint parameters should ensure
that there is no constraint parameters are violated.
The other synthesis results for the system clock
period of 3.3 ns are shown on Table 1. This clock
period is given a good slack value of 0.41 ns.
Table 1 Synthesized output parameters
Xilinix Parameters ASIC Parameters
Max. Frequency=253MHz Cell area= 0.03753 mm2
Total gate count=6041 Power = 7.578 mW
Connection Delay=1.18ns Arrival time=2.31ns
Max. pin Delay=5.35ns Slack = 0.41 ns
Table 1 shows the output parameters using two
synthesis technology; Xilinix and ASIC. The
RFDACT system has the maximum operating
frequency of 253 MHz and the total gates of 6,041.
The average connection delay is 1.18 ns and the
maximum pin delay is 5.35 ns. Moreover, the
RFDACT is occupied 0.03753 mm2
cell area and
consumed 7.578 mW power. The data required
time and the data arrival time are 2.72 ns and
2.31ns respectively.
V. CONCLUSIONS
A proposed Reliable Fast Detection
Anti-collision Technique (RFDACT) is presented
to achieve a reliable and faster identification of
the tags. An error packet is detected at the front
end of the system before the tag identification
process is carried out. The faster identification
process is performed at the back end of the system
by using the deterministic anti-collision
technique. The RFDACT system has been
successfully implemented in hardware using
FPGA model Virtex II Xc2v250. The simulation
output of the system has been verified in real time
using Tektronix Logic Analyzer model TLA 520.
252

From the verification result, it shows that this
hardware implemented system enables to identify
the tags at the operating frequency of 180 MHz
without error. Then the system is implemented on
chip using 0.18 µm Library, Synopsys compiler
and tools. The synthesis result shows that the
minimum identification time is 3.3 ns. The chip is
utilized 6041 gates, occupied 0.03753 mm2
cell
area and consumed 7.578 mW power.
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[8] S. Singh, “Low Cost Object Identification in
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[9] Jahariah S. and Masuri O., “Fast Detection
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253

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