![Current Mirrors
Ch. 5 # 32
IX 2
VX
2ro1, 2 1/gm3
VX
ro4
Rout ro2 || ro4 , (2ro1,2 [1/gm3] || ro3 )
Av gm1,2 (ro2 || ro4 )
• For small signals Iss is open,
• That is any current flowing into M1 must flow out of M2
• It can be represented](https://image.slidesharecdn.com/cmosunit32023-24-240624190130-d3321d09/85/cmos-Unit-passive-and-active-current-mirrors-3-2023-24-ppt-32-320.jpg)
![Current Mirrors
Ch. 5 # 49
• The circuit exhibits 3 poles. [each is determined by the total
capacitance from each node to ground, multiplied by total resistance at
the node to ground]
• We can associate each pole with each other
•
• “each node in the circuit contributes one pole to the transfer function”](https://image.slidesharecdn.com/cmosunit32023-24-240624190130-d3321d09/85/cmos-Unit-passive-and-active-current-mirrors-3-2023-24-ppt-49-320.jpg)
cmos Unit passive and active current mirrors 3 2023-24.ppt
- 1. Unit -3 Passive and Active Current Mirrors Current Mirrors Ch. 2 # 2
- 2. Basic current mirror Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Travis N. Blalock, University Differential Amplifiers Ch. 4 # 2 A current mirror is a circuit designed to build many current sources in the system from the reference current source Current mirror means we have reference current source, this reference current source copies the current to the other current sources.
- 3. Current Mirrors Ch. 5 # 3 Basic current mirrors
- 4. IOUT unCox 2 W L ( R2 R2 R1 VDD VTH )2 • This fig consider the simple resistor biasing assuming m1 is in saturation.
- 5. Current Mirrors Ch. 5 # 5 • This expression reveals varies dependencies of Iout upon the supply, process & temperature. • The overdrive v/g is a function of Vdd & Vth. • The threshold v/g varies by 100mV. • exhibits temperature dependencies • Therefore Iout is poorly defined. • Note: the process & temperature dependencies exist if gate v/g is not a function of supply v/g • Ie., if gate- source v/g of the mosfet is precisely defined • Then drain current is not equal. • So to design, current source in analog circuits is based on “coping” current from reference.
- 6. Current Mirrors Ch. 5 # 6 • In complex circuit sometimes requiring external adjustments • It is used to generate a stable reference current Iref • Which is copied to many current sources in the system
- 7. Current Mirrors Ch. 5 # 7 • For a mosfet, • Denotes function of Id v/s Vgs • Then • Now if a transistor is biased at Iref
- 8. Current Mirrors Ch. 5 # 8 if this voltage is applied to the gate and source terminals of a second MOSFET, the resulting current is
- 9. Current Mirrors Ch. 5 # 9 • In fig b, the structure consisting of M1 & M2 is called “current mirror” • The device need not to be identical. • Neglecting channel length modulation,
- 10. Cascode Current Mirror Current Mirrors Ch. 5 # 10 • Till now, we have neglected channel length modulation • The effects of the results in significant errors in coping currents
- 11. Cascode Current Mirror Current Mirrors Ch. 5 # 11
- 12. Current Mirrors Ch. 5 # 12 • Fig 5.9 a,: if Vb is chosen such that Vy=Vx • Then Iout closely tracks Iref • The cascode devide “shields” the bottom transistors from variations in Vp • W.K.T • Therefore Vy remains close to Vx • Hence • Accuracy high • To generate Vb, ensure Vy=Vx • This result suggests that, • If gate- source v/g is added to Vx, • Then Vb is obtained.
- 13. Current Mirrors Ch. 5 # 13 • In fig 5.9b, place another diode M0 in series with M1 • Therefore generating a v/g • Proper choice of dimensions of M0 w.r.t M3 yields • In fig 5.9 c, connect the node N to M3 • Then • If • Then •
- 14. Cascode Current Mirror (cont.) Current Mirrors Ch. 5 # 14
- 15. Current Mirrors Ch. 5 # 15 • In fig 5.11(a): Vb is chosen to allow the lowest possible value of Vp • But o/p current doesn’t accurately track Iref • Because M1 & M2 sustain unequal drain-source v/g • In fig 5.11(b): accuracy high • But minimum level at P is high by 1 threshold v/g
- 16. Current Mirrors Ch. 5 # 16 • Fig 5.13 a, this circuit cascode topology with o/p shorted to its i/p • We must have for M2 to be saturated • In fig 5.13.b: all transistors are in saturation and proper ratioing • The cascode current source M3 & M4 consumes minimum headroom • While M1 & M2 sustain equal drain source • Therefore accurate coping of Iref • This is called “low v/g cascode”
- 17. Cascode Current Mirror Biasing Current Mirrors Ch. 5 # 17
- 18. Current Mirrors Ch. 5 # 18 • In fig 5.14b, here diode-connected transistor M7 has large W/L • So • Hence • We requiring no resistor, this circuit suffers from similar error due to body effect
- 19. Active Current Mirrors Current Mirrors Ch. 5 # 19 • It is the basic pmos circuit which acts as current mirror • M1 & M2 are identical • Whatever the current flowing across Iin will reflect across Iout • Current through Iout is given some active component signal • Current mirrors can also process signals Operate as “active elements” • So it is called as “active current mirrors”
- 20. Active Current Mirrors (Cont….. Current Mirrors Ch. 5 # 20
- 21. Current Mirrors Ch. 5 # 21 • In fig5.17 a, consider differential pair M1 & M2 • M3 & M4 current source load. • In fig 5.17,b: • In fig 5.17,c: now we have to compute Rout • M2 is degenerated by the source output impedance • That is the circuit is similar to common source amplifier with regenerative circuit • output impedance equal to
- 22. Current Mirrors Ch. 5 # 22 • We calculate
- 23. Current Mirrors Ch. 5 # 23
- 24. Active Current Mirrors (Cont….. Current Mirrors Ch. 5 # 24
- 25. Active Current Mirror (Cont… Current Mirrors Ch. 5 # 25
- 26. Large Signal Analysis Current Mirrors Ch. 5 # 26 • o/p v/g depends on diff b/w Id4 & Id2. • In fig replace ideal tail current source by mosfet • If Vin1 is much –ve than Vin2 • M1, M3, M4 off • Since no current flows from Vdd • M2 & M5 deep triode region • carrying 0 current • Thus Vout=0 • As Vin1 approaches Vin2 • M1on (drawing part of Id5 from M3) • Therefore M4 on
- 27. Current Mirrors Ch. 5 # 27 • As Vin becomes more +ve than Vin2 • Id1, Id3, Id4 increases • If Id2 decreases • Then M4 triode region (0) • If Vin1 – Vin2 is sufficiently large • M2 off • M4 deep triode region with 0 current • Vout= Vdd • Then M1 enters triode region
- 28. Current Mirrors Ch. 5 # 28 • For M2 to be in saturation? • o/p v/g cannot be less than • To allow maximum o/p swings, the i/p CM level must be low. • I.e.. min • When Vin1=Vin2? Or with perfect symmetry? • Suppose Due to C.L.M M1 carry greater current thane M2 M4 carry greater current than M3
- 29. Small-Signal Analysis Current Mirrors Ch. 5 # 29 • It has small inputs • v/g swings at node x &y are different • Because the diode-connected device M3 yields much lower v/g gain from the i/p to node x • As a result, the effects of Vx &Vy at node P do not cancel each other • This node cannot be considered as virtual ground • We compute the gain using 2 approaches
- 30. Small-Signal Analysis 1st approach Calculation of Gm Current Mirrors Ch. 5 # 30 2 / 2 / 2 , 1 2 2 , 1 4 3 1 in m D in m D D D V g I V g I I I Iout ID2 ID4 gm1,2Vin , Gm gm1, 2 • Consider the circuit is not quite symmetric • Node P can be approximately by a virtual ground
- 31. Current Mirrors Ch. 5 # 31 • The active mirror operation yields a different value • Because when a v/g is applied to the o/p to measure Rout • The gate v/g of M4 does not remain constant • Rather than draw the entire equivalent circuit
- 32. Current Mirrors Ch. 5 # 32 IX 2 VX 2ro1, 2 1/gm3 VX ro4 Rout ro2 || ro4 , (2ro1,2 [1/gm3] || ro3 ) Av gm1,2 (ro2 || ro4 ) • For small signals Iss is open, • That is any current flowing into M1 must flow out of M2 • It can be represented
- 33. Small-Signal Analysis 2nd approach Current Mirrors Ch. 5 # 33
- 34. Small-Signal Analysis (Cont…. Current Mirrors Ch. 5 # 34
- 35. Small-Signal Analysis (Cont… Current Mirrors Ch. 5 # 35
- 36. Common Mode Characteristics Current Mirrors Ch. 5 # 36 ACM Vout Vin,CM • Change in the i/p cm level leads to change in bias current of all transistors
- 37. Common Mode (cont.) Current Mirrors Ch. 5 # 37 • Here F & X are shorted that is Vin,cm increases • Vf and Vout drops ACM 1 2gm3,4 || ro3,4 2 1 2gm1,2 RSS 1 1 2gm1,2 RSS gm1,2 gm 3, 4
- 38. Common Mode (cont.) Current Mirrors Ch. 5 # 38 CMRR ADM ACM gm1, 2(ro1,2 || ro3,4 ) gm3,4 (1 2gm1,2 RSS ) gm1,2 gm3,4 (ro1, 2 || ro3,4 )(1 2gm1, 2RSS)
- 39. Common Mode (cont.) effect of mismatch Current Mirrors Ch. 5 # 39
- 40. Calculating current individually Current Mirrors Ch. 5 # 40
- 41. Common Mode (cont.) Current Mirrors Ch. 5 # 41
- 42. Unit3 Frequency Response of Amplifiers
- 43. • Till now we are focused on low frequency characteristics of amplifier neglecting the effect of device & load capacitance • In most analog circuits, we consider the parameter such as noise, PD, gain • But it is important to understand the frequency response limitations • In this chapter we study about single stage & differential amplifiers in the frequency domain
- 46. • If the impedance Z forms the only signal B/W X & Y. • Then the conversion is often invalid in the fig • For the simple resistive divider, the theorem gives correct i/p but incorrect gain
- 47. Current Mirrors Ch. 5 # 47 • Miller’s theorem proves useful where Z is similar with main signal • If we apply to obtain , i/p- o/p transfer function, miller’s theorem cannot be used simultaneously to calculate o/p impedance. • Therefore to derive transfer function, we apply v/g source to the i/p circuit for obtaining • To determine o/p impedance, we apply v/g source to o/p for obtaining
- 48. • Consider simple cascade amplifier • A1 & A2 are ideal v/g amplifier • R1 & R2 are o/p resistance of each stage • Cin & Cn are i/p capacitance of each stage. • Cp load capacitance • Overall transfer function is
- 49. Current Mirrors Ch. 5 # 49 • The circuit exhibits 3 poles. [each is determined by the total capacitance from each node to ground, multiplied by total resistance at the node to ground] • We can associate each pole with each other • • “each node in the circuit contributes one pole to the transfer function”
- 50. • The location of the poles is difficult to calculate. • Because R3 & C3 create intersection b/w x & y • In many circuits to estimating the transfer function. • We multiply total capacitance by the total incremental resistance. • Thus obtaining an equivalent time constant & hence a pole frequency.
- 51. Common Source Stage This topology provides high i/p impedance, high v/g gain, minimal v/g headroom. In this fig, common source stage driven by a finite resistance Rs Capacitance Cgs & Cdb are grounded. Cgd appears b/w i/p & o/p
- 52. Current Mirrors Ch. 5 # 52 • Assume • M1 operates in saturation
- 53. Another approximation of o/p pole can be obtained if Rs is high. In the fig Rs is neglected. therefore
- 54. Common Source Stage using Equivalent Circuit We can sum current at each node
- 55. Current Mirrors Ch. 5 # 55
- 57. Common Source Stage using Equivalent Circuit
- 58. CS Stage using Feed forward path • Cgd provides feedforward path, that conducts the i/p signal to the o/p at very high frequencies • Therefore a slope in frequency response that is less –ve than
- 59. Calculation of Zero in a CS Stage Current through Cgd & M1 = & opposite
- 60. Calculation of Input Impedance
- 61. Calculation of Input Impedance
- 62. Source Followers • These are occasionally employed as level shifters or buffers. • In fig, here Cl represents total capacitance at o/p node to ground • Strong interaction b/w b/w X & Y through Cgs make it difficult to associate a pole with each other node.
- 63. Current Mirrors Ch. 5 # 63 • In fig neglecting body effect, using equivalent circuit • we sum the current at the o/p node
- 65. Source Followers (Input Impedance) Here M1 (small signal gate source) =
- 67. Source Followers (Output Impedance)
- 69. Source Followers (Output Impedance)
- 71. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Travis N. Blalock, University Differential Amplifiers Ch. 4 # 71 Thank you