Combinational circuit (7-Segment display)
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The document describes the design of combinational logic circuits for 7-segment displays, comparators, adders, and parallel adders. It includes truth tables, Karnaugh maps, logic expressions, and circuit diagrams for 7-segment displays to display digits, a 2-bit comparator to compare two binary numbers, half adders, full adders using half adders, and a 4-bit parallel binary adder.
Combinational circuit (7-Segment display)
- 1. Combinational 7 segment, comparator and Adder circuit Digital Logic Design
- 3. Inputs Output A B C D a 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 Inputs Output A B C D a 1 0 0 0 1 1 0 0 1 1 1 0 1 0 X 1 0 1 1 X 1 1 0 0 X 1 1 0 1 X 1 1 1 0 X 1 1 1 1 X Function Table for Segment ‘a’
- 4. Inputs Output A B C D b 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 Inputs Output A B C D b 1 0 0 0 1 1 0 0 1 1 1 0 1 0 X 1 0 1 1 X 1 1 0 0 X 1 1 0 1 X 1 1 1 0 X 1 1 1 1 X Function Table for Segment ‘b’
- 5. Inputs Output A B C D c 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 Inputs Output A B C D c 1 0 0 0 1 1 0 0 1 1 1 0 1 0 X 1 0 1 1 X 1 1 0 0 X 1 1 0 1 X 1 1 1 0 X 1 1 1 1 X Function Table for Segment ‘c’
- 6. Inputs Output A B C D d 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 1 1 0 1 1 0 1 0 1 1 1 0 Inputs Output A B C D d 1 0 0 0 1 1 0 0 1 1 1 0 1 0 X 1 0 1 1 X 1 1 0 0 X 1 1 0 1 X 1 1 1 0 X 1 1 1 1 X Function Table for Segment ‘d’
- 7. Inputs Output A B C D e 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 1 0 1 1 1 0 Inputs Output A B C D e 1 0 0 0 1 1 0 0 1 0 1 0 1 0 X 1 0 1 1 X 1 1 0 0 X 1 1 0 1 X 1 1 1 0 X 1 1 1 1 X Function Table for Segment ‘e’
- 8. Inputs Output A B C D f 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 0 Inputs Output A B C D f 1 0 0 0 1 1 0 0 1 1 1 0 1 0 X 1 0 1 1 X 1 1 0 0 X 1 1 0 1 X 1 1 1 0 X 1 1 1 1 X Function Table for Segment ‘f’
- 9. Inputs Output A B C D g 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 0 Inputs Output A B C D g 1 0 0 0 1 1 0 0 1 1 1 0 1 0 X 1 0 1 1 X 1 1 0 0 X 1 1 0 1 X 1 1 1 0 X 1 1 1 1 X Function Table for Segment ‘g’
- 10. Karnaugh Map for Segment ‘a’ ABCD 00 01 11 10 00 1 0 1 1 01 0 1 1 1 11 x x x x 10 1 1 x x DBBDCA
- 11. Karnaugh Map for Segment ‘b’ ABCD 00 01 11 10 00 1 1 1 1 01 1 0 1 0 11 x x x x 10 1 1 x x CDDCB
- 12. Karnaugh Map for Segment ‘c’ ABCD 00 01 11 10 00 1 1 1 0 01 1 1 1 1 11 x x x x 10 1 1 x x BDC
- 13. Karnaugh Map for Segment ‘d’ ABCD 00 01 11 10 00 1 0 1 1 01 0 1 0 1 11 x x x x 10 1 1 x x DCBDCCBDBA
- 14. Karnaugh Map for Segment ‘e’ ABCD 00 01 11 10 00 1 0 0 1 01 0 0 0 1 11 x x x x 10 1 0 x x DCDB
- 15. Karnaugh Map for Segment ‘f’ ABCD 00 01 11 10 00 1 0 0 0 01 1 1 0 1 11 x x x x 10 1 1 x x DBCBDCB
- 16. Karnaugh Map for Segment ‘g’ ABCD 00 01 11 10 00 0 0 1 1 01 1 1 0 1 11 x x x x 10 1 1 x x CBDCCBA
- 18. Comparator Circuit • Inputs two 2-bit binary numbers A and B • Has three outputs • A>B • A=B • A<B
- 19. Inputs Output A1 A0 B1 B0 A>B 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 Inputs Output A1 A0 B1 B0 A>B 1 0 0 0 1 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 Function Table for A>B
- 20. Inputs Output A1 A0 B1 B0 A=B 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 0 Inputs Output A1 A0 B1 B0 A=B 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 Function Table for A=B
- 21. Inputs Output A1 A0 B1 B0 A<B 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 1 0 0 1 1 0 1 0 1 1 1 1 Inputs Output A1 A0 B1 B0 A<B 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 0 Function Table for A<B
- 22. Karnaugh Map for A>B A1A0/ B1B0 00 01 11 10 00 0 0 0 0 01 1 0 0 0 11 1 1 0 1 10 1 1 0 0 00101011 BAABBABA
- 23. Karnaugh Map for A=B A1A0/ B1B0 00 01 11 10 00 1 0 0 0 01 0 1 0 0 11 0 0 1 0 10 0 0 0 1 0101010101010101 BBAABBAABBAABBAA
- 24. Karnaugh Map for A<B A1A0/ B1B0 00 01 11 10 00 0 1 1 1 01 0 0 1 1 11 0 0 0 0 10 0 0 1 0 01000111 BBABAABA
- 25. Half & Full Adders A B Cout InputBits OutputBits Half-Adder A B Cin Cout InputBits OutputBits Full-Adder
- 26. Half-Adder • Function Table • Expression • Logic Circuit
- 27. Half-Adder Function Table Input Output A B Sum Carry Out 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
- 28. Half-Adder Circuit A B Cout BABABASum ABCarryOut
- 29. Full-Adder • Function Table • Expression • Logic Circuit
- 30. Full-Adder Function Table Input Output A B Carry In (C) Sum Carry Out 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1
- 31. Sum Expression ABCCBACBACBASum )()( BCCBACBCBASum )()( CBACBASum CBASum
- 32. Carry Out Expression ABCCABCBABCACarryOut )()( CCABBABACCarryOut ABBACCarryOut )(
- 34. Full-Adder • Full-Adder = Half-Adder + Half-Adder
- 35. Full-Adder based on Two Half-Adders A B Cout Half-Adder A B Cout Half-Adder Cin A B Cout
- 36. Parallel Binary Adder • Multiple Single bit Full-Adder connected in Parallel