Combinational logic circuits

9/15/09 - L12 Combinational
Logic Design Copyright 2009 - Joanne DeGroat, ECE, OSU 1

Class 12-Combinational Logic
 Other gate types
 Material from section 3-1 and 3-2 of text

Combinational Logic Design
 A process with 5 steps
 Specification
 Formulation
 Optimization
 Technology mapping
 Verification
 1st three steps and last best illustrated by example

Functional Blocks
 Fundamental circuits that are the base building blocks of
most larger digital circuits
 They are reusable and are common to many systems.
 Examples of functional logic circuits
 Decoders
 Encoders
 Code converters
 Multiplexers

Where they are used
 Multiplexers
 Selectors for routing data to the processor, memory, I/O
 Multiplexers route the data to the correct bus or port.
 Decoders
 are used for selecting things like a bank of memory and then
the address within the bank. This is also the function
needed to ‘decode’ the instruction to determine the operation
to perform.
 Encoders
 are used in various components such as keyboards.

Specifications step
 Write a specification for the circuits
 Specification includes
 What are the inputs: how many, how many bits in a given
output, how are they grouped,, are they control, are they
active high?
 What are the outputs: how many and how many bits in a
each, active high, active low, tristate output?
 The functional operation that takes place in the chip, i.e., for
given inputs what will appear on the outputs.

Formulation step
 Convert the specifications into a variety forms for optimal
implementation.
 Possible forms
 Truth Tables
 Expressions
 K-maps
 Binary Decision Diagrams
 IF THE SPECIFCATION IS ERRONOUS OR
INCOMPLETE (open for various interpretation) then the
circuit will perform as specified but will not perform as
desired.

Last 3 steps
 Best illustrated by example
 A BCD to Excess-3 code converter
 BCD-to-7-segment decoder

BCD-to-Excess-3 Code converter
 BCD is a code for the decimal digits 0-9
 Excess-3 is also a code for the decimal digits

Specification of BCD-to-Excess3
 Inputs: a BCD input, A,B,C,D with A as the most
significant bit and D as the least significant bit.
 Outputs: an Excess-3 output W,X,Y,Z that corresponds to
the BCD input.
 Internal operation – circuit to do the conversion in
combinational logic.

Formulation of BCD-to-Excess-3
 Excess-3 code is easily formed by adding a binary 3 to the
binary or BCD for the digit.
 There are 16 possible inputs for both BCD and Excess-3.
 It can be assumed that only valid BCD inputs will appear
so the six combinations not used can be treated as don’t
cares.

Optimization – BCD-to-Excess-3
 Lay out K-maps for each output, W X Y Z
 A step in the digital circuit design process.

Placing 1 on K-maps
 Where are the minterms located on a K-Map?

Expressions for W X Y Z
 W(A,B,C,D) = Σm(5,6,7,8,9)
+d(10,11,12,13,14,15)
 X(A,B,C,D) = Σm(1,2,3,4,9)
+d(10,11,12,13,14,15)
 Y(A,B,C,D) = Σm(0,3,4,7,8)
+d(10,11,12,13,14,15)
 Z(A,B,C,D) = Σm(0,2,4,6,8)
+d(10,11,12,13,14,15)

Minimize K-Maps
 W minimization
 Find W = A + BC + BD

Minimize K-Maps
 X minimization
 Find X = BC’D’+B’C+B’D

Minimize K-Maps
 Y minimization
 Find Y = CD + C’D’

Minimize K-Maps
 Z minimization
 Find Z = D’

Two level circuit implementation
 Have equations
 W = A + BC + BD = A + B(C+D)
 X = B’C + B’D + BC’D’ = B’(C+D) + BC’D’
 Y = CD + C’D’
 Z = D’
 Factoring out (C+D) and call it T
 Then T’ = (C+D)’ = C’D’
 W = A + BT
 X = B’T + BT’
 Y = CD + T’
 Z = D’

Create the digital circuit
 Implementing the
second set of
equations where
T=C+D results in a
lower gate count.
 This gate has a fanout
of 3

BCD-to-Seven-Segment Decoder
 Specification
 Digital readouts on many digital products often use LED
seven-segment displays.
 Each digit is created by lighting the appropriate segments.
The segments are labeled a,b,c,d,e,f,g
 The decoder takes a BCD input and outputs the correct code
for the seven-segment display.

Specification
 Input: A 4-bit binary value that is a BCD coded input.
 Outputs: 7 bits, a through g for each of the segments of
the display.
 Operation: Decode the input to activate the correct
segments.

Formulation
 Construct a truth table

Optimization
 Create a K-map for each output and get
 A = A’C+A’BD+B’C’D’+AB’C’
 B = A’B’+A’C’D’+A’CD+AB’C’
 C = A’B+A’D+B’C’D’+AB’C’
 D = A’CD’+A’B’C+B’C’D’+AB’C’+A’BC’D
 E = A’CD’+B’C’D’
 F = A’BC’+A’C’D’+A’BD’+AB’C’
 G = A’CD’+A’B’C+A’BC’+AB’C’

Note on implementation
 Direct implementation would require 27 AND gates and 7
OR gates.
 By sharing terms, can actualize and implementation with
14 less gates.
 Normally decoder in a device name indicates that the
number of outputs is less than the number of inputs.

4-bit Equality Checker
 Specification
 Input: Two vectors, A(3:0) and B(3:0) each being 4-bits.
The msb bits the A(3) and B(3).
 Output: E which has a value of 1 when A=B and 0 if any bit
of A/=B.
 Operation: Combinational logic to compare the 4 bits of A
with the 4 bits of B to produce E

 Formulation
 For each bit position Ai will be compared with Bi and if they
are equal, a 0 will be output. If they differ a 1 will be
output.
 Thus, if any bit position indicates a 1 then the values are
different. These 1st level comparators outputs can then be
Ored together.
 The ORed output is inverted to produce a 1 when they are
equal.

 Optimization
 Done by implementing two
separate blocks.
 1st the unit MX that compares
two bit and outputs a 0 if they
are equal, i.e., an XOR
operation.

The second unit
 The ME unit takes the MX outputs and generates a 1 when
all the inputs are 0, i.e., a NOR operation.
 E = (N0+N1+N2+N3)’

Heirarchical Representation
 Figure 3-5 of text

Class 12 assignment
 Covered sections 3-1 and 3-2
 Problems for hand in
 3-1 and 3-3 (due Monday)
 Problems for practice
 3-2, 3-8, 3-10, 3-11a
 Reading for next class:

Combinational logic circuits

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