Chapter 3 instruction set-of-8085

Instruction Set of 8085
An instruction is a binary pattern designed inside a
microprocessor to perform a specific function.
The entire group of instructions that a microprocessor
supports is called Instruction Set.
8085 has 246 instructions.
Each instruction is represented by an 8-bit binary value.
These 8-bits of binary value is called Op-Code or
Instruction Byte.

Classification of Instruction Set
 Data Transfer Instruction
 Arithmetic Instructions
 Logical Instructions
 Branching Instructions
 Control Instructions

Data Transfer Instructions
These instructions move data between registers, or
between memory and registers.
These instructions copy data from source to
destination.
While copying, the contents of source are not
modified.

1-3. Data Transfer Instructions
Opcode Operand Addressing modes Description
MOV Rd, Rs
M, Rs
Rd, M
Register
Indirect
Indirect
Copy from source to
destination.
This instruction copies the contents of the source register(Rs) into the
destination register(Rd).
The contents of the source register are not altered.
If one of the operands is a memory location, its location is specified by
the contents of the HL registers.
1 Byte Instruction
Example: MOV B, C or MOV B, M

A 20 B 20
A F
B 30 C
D E
H 20 L 50
A 20 B
BEFORE EXECUTION AFTER EXECUTION
MOV B, A
A F
B 30 C
D E
H 20 L 50
A F
B C
D E
H 20 L 50
A F
B C 40
D E
H 20 L 50
MOV M, B
MOV C, M
40 40
30

4, 5. Data Transfer Instructions
Opcod
e
Operand Addressing modes Description
MVI Rd, Data
M, Data
Immediate
Immediate/Indirect
Move immediate 8-bit
The 8-bit data is stored in the destination register(Rd) or
memory(M). R is general purpose 8 bit register such as
A,B,C,D,E,H and L.
If the operand is a memory location, its location is specified
by the contents of the H-L registers.
Example: MVI B, 60H or MVI M, 40H

A F
B C
D E
H L
A F
B 60 C
D E
H L
AFTER EXECUTIONBEFORE EXECUTION
MVI B, 60H
40
HL=2050H
2051H
204FH 204FH
HL=2050H
2051H
MVI M, 40H

6. Data Transfer
Instructions
LXI Reg. pair, 16-
bit data
Immediate Load register pair
immediate
This 16-bit data is moved into the register pair.
[rh] 8 MSBs of data
[rl] 8 LSBs of data
3 byte instruction
Example: LXI H, 1234 H (
H represents HL Register Pair

A F
B C
D E
H 56 L 78
A F
B C
D E
H 12 L 34
LXI H, 1234

7. Data Transfer Instructions
LDA 16-bit
address
Direct Load Accumulator Direct
The contents of a memory location, whose address is
specified in instruction, is loaded into the
accumulator.
The contents of the source are not altered.
Example: LDA 7000H

A 55
11
A 11
11
LDA 2034H2034H 2034H

8. Data Transfer
Instructions
Opcode Operand Addressing
modes
Description
STA 16-bit address Direct Store accumulator direct
The contents of accumulator is copied in the memory
location whose address is specified in instruction.
Example: STA 7000 H

A 55 A 55
55
STA 7000H7000H 7000H

9. Data Transfer
Instructions
LHLD 16-bit
address
Direct Load H-L registers direct
The contents of memory location whose address is
specified in the instruction is loaded into register L.
The contents of next memory location is loaded into
register H.
Example: LHLD 7000 H

A F
B C
D E
H 44 L 55
A F
B C
D E
H 12 L 34
34
12
34
12
LHLD 7000H
7001H
7000H
7002H
7000H
7001H
7002H

10.Data Transfer
Instructions
SHLD 16-bit address Direct Store H-L registers direct
The contents of register L is stored into memory
location whose address is specified in instruction.
The contents of register H are stored into the next
memory location.
3 bytes instruction
Example: SHLD 7000 H

A F
B C
D E
H 44 L 55
A F
B C
D E
H 44 L 55
34
12
55
44
SHLD 7000H
7001H
7000H
7002H
7000H
7001H
7002H

Opcod
e
Operand Addressing
modes
Description
LDAX B/D Register Pair Indirect Load accumulator indirect
with Register Pair
The contents of the designated register pair point to a memory location.
This instruction copies the contents of that memory location into the
accumulator.
The contents of either the register pair or the memory location are not
altered.
1 byte instruction.
Example: LDAX B

A F
B C
D 20 E 30
A 80 F
B C
D 20 E 30
80 80
LDAX D
2030H 2030H

12. Data Transfer
Instructions
STAX Reg. pair Indirect Store accumulator indirect
The contents of accumulator are copied into the
memory location whose address is in the register pair.
Example: STAX B

A 22 F
B 75 C 00
D E
A 22 F
B 75 C 00
D E
11 22
STAX B
7500H 7500H

XCHG None Register Exchange the content of H-
L with D-E pair
The contents of register H are exchanged with the
contents of register D.
The contents of register L are exchanged with the
contents of register E.
Example: XCHG

D 20 E 40
H 70 L 80
D 70 E 80
H 20 L 40
XCHG

Arithmetic Instructions
These instructions perform the operations like:
Addition
Subtract
Increment
Decrement
Almost all the instruction in this group affect the
Flag register.

Addition
Any 8-bit number, or the contents of register, or the
contents of memory location can be added to the
contents of accumulator.
The result (sum) is stored in the accumulator.
No two other 8-bit registers can be added directly.
Example: The contents of register B cannot be added
directly to the contents of register C.

Subtraction
Any 8-bit number, or the contents of register, or the
contents of memory location can be subtracted from the
The result is stored in the accumulator.
Subtraction is performed in 2’s complement form and
set the carry flag to indicate borrow.
If the result is negative, it is stored in 2’s complement
form.
No two other 8-bit registers can be subtracted directly.

Increment / Decrement
The 8-bit contents of a register or a memory location
can be incremented or decremented by 1.
The 16-bit contents of a register pair can be
incremented or decremented by 1.
Increment or decrement can be performed on any
register or a memory location.

1, 2. Arithmetic Instructions
ADD R
M
Register
Indirect
Add register or memory to
accumulator
The contents of register or memory are added to the contents of
accumulator.
The result is stored in accumulator.
If the operand is memory location, its address is specified by H-L pair.
All flags are modified to reflect the result of the addition.
Example: ADD B or ADD M

B C 77
D E
H L
B C 77
D E
H L
B C
D E
H 20 L 50
B C
D E
H 20 L 50
A 57
A ACA 35
A CA
ADD C
A=A+C
ADD M
A=A+M
73
732050 2050
Flag affected
S Z X AC X P X CY
1 0 0 1 0

3. Arithmetic Instructions
ADI 8-bit data Immediate Add immediate to
accumulator
The 8-bit data is added to the contents of
accumulator.
All flags are modified to reflect the result of the
addition.
Example: ADI 45 H

A 50 A 60
ADI 10H
A=A+DATA(8)

ADC R
M
Register
Indirect
Add register or memory to
accumulator with carry
The contents of register or memory and Carry Flag (CY) are added to the
Example: ADC B or ADC M

B C 20
D E
H L
A 50
B C 20
D E
H L
A 71
ADC C
A=A+R+CY
CY 1 CY 0
CY 1 CY 0
A 20 A 51
H 20 L 50 H 20 L 50
ADC M
A=A+M+CY
30 302050H 2050H

ACI 8-bit data Immediate Add immediate to
accumulator with carry
The 8-bit data and the Carry Flag (CY) are added to the
Example: ACI 45 H

CY 1 CY 0
A 30 A 51
ACI 20H
A=A+DATA(8)+CY

DAD Reg. pair Register Add register pair to H-L pair
 The 16-bit contents of the register pair are added to the contents of H-L pair. The result is
stored in H-L pair.
 If the result is larger than 16 bits, then CY is set. No other flags are changed, only CY is
changed.
 1 byte instruction.
 3 machine cycle (10 T states) are Opcode Fetch, Bus Idle and Bus Idle. In the Bus idle cycle no
operation is performed. Because MPU does not activate ALE signal. During 1st
bus idle cycle
MP add lower byte of 16 bit and in second machine cycle MP add higher bytes of 16 bit
number.
 Example: DAD D

B C
D 10 E 20
H 20 L 50
SP
B C
D 10 E 20
H 30 L 70
SP
CY 0 CY 0
DAD D
HL=HL+R

8,9. Arithmetic Instructions
SUB R
M
Register
Indirect
Subtract register or memory
from accumulator
The contents of the register or memory location are subtracted from the
contents of the accumulator.
All flags are modified to reflect the result of subtraction.
Example: SUB B or SUB M

B 30 C
D E
H L
A 50
B 30 C
D E
H L
A 20
SUB B
A=A-R
A 50 A 40
H 10 L 20 H 10 L 20
SUB M
A=A-M
10 10
1020H1020H

SUI 8-bit data Immediate Subtract immediate from
accumulator
The 8-bit data is subtracted from the contents of the
accumulator.
Example: SUI 77 H

A FE
A 87SUI 77H
A=A-DATA(8)

SBB R
M
Register
Indirect
Subtract register or memory
from accumulator with borrow
 The contents of the register or memory location and Borrow Flag (i.e. CY) are
subtracted from the contents of the accumulator.
 The result is stored in accumulator.
 If the operand is memory location, its address is specified by H-L pair.
 All flags are modified to reflect the result of subtraction.
 Example: SBB B or SBB M

B C 39
D E
H L
A 78
CY 1
B C 39
D E
H L
A 38
CY 0
SBB C
A=A-R-CY
CY 1
A 50
H 20 L 50
CY 0
A 39
H 20 L 50
AFTER EXECUTION
BEFORE EXECUTION
SBB M
A=A-M-CY
10 10
2050H 2050H

SBI 8-bit data Immediate Subtract immediate from
accumulator with borrow
The 8-bit data and the Borrow Flag (i.e. CY) is
subtracted from the contents of the accumulator.
Example: SBI 45 H

CY 1
A 50
CY 0
A 29
SBI 20H
A=A-DATA(8)-
CY

INR R
M
Register
Indirect
Increment register or
memory by 1
 The contents of register or memory location(addressed by HL pair) are
incremented by 1.
 The result is stored in the same place.
 If the operand is a memory location, its address is specified by the contents of
H-L pair.
 All flag are modified except Carry Flag.
 Example: INR B or INR M

B 10 C
D E
H L
A
B 11 C
D E
H L
A
H
20
L
50
H
20
L
50
30 31
2050
H
2050
H
INR M
M=M+1
B 10 C
D E
H L
A
BEFORE EXECUTION
INR B
R=R+1

INX R Register Increment register pair by 1
The contents of register pair are incremented by 1.
The result is stored in the same place.
No flag are Modified.
Example: INX H

B C
D E
H FF L FF
B C
D E
H 00 L 00
SPSP
INX H
RP=RP+1

DCR R
M
Register
Indirect
Decrement register or memory
by 1
 The contents of register or memory location are decremented by 1.
 The result is stored in the same place.
 If the operand is a memory location, its address is specified by the contents of
H-L pair.
 All flag are modified except Carry Flag.
 Example: DCR B or DCR M

B C
D E 19
H L
A
AFTER EXECUTION
B C
D E 20
H L
A
BEFORE EXECUTION
DCR E
R=R-1
H 20 L 50
H 20 L 50
21 20
2050H
DCR M
M=M-1 2050H

DCX R Register Decrement register pair by 1
The contents of register pair are decremented by 1.
The result is stored in the same place.
No Flags are modified.
Example: DCX H

B C
D 10 E 20
H L
B C
D 10 E 19
H L
SPSP
DCX D
RP=RP-1

DAA None Implicit Decimal Adjust
Accumulator
 This instruction convert the binary(Hex) result in accumulator into decimal or BCD result.
 It is used in the program after ADD, ADI, ACI, ADC instruction.
 The following steps are taken to convert binary result to decimal
1. If the value of 4 LSBs(Lower Nibble) of A > 9 or AC flag is set to 1 then 06 is added to the
content of accumulator.
2. If the value of 4 MSBs(Higher Nibble) of A > 9 or CY flag is set to 1 then 06 is added to the
content of accumulator.
 Example: DAA

Logical Instructions
These instructions perform logical operations on data
stored in registers, memory and status flags.
The logical operations are:
AND
OR
XOR
Rotate
Compare
Complement

AND, OR, XOR
Any 8-bit data, or the contents of register, or memory
location can logically have
AND operation
OR operation
XOR operation
with the contents of accumulator.

Rotate
Each bit in the accumulator can be shifted either left
or right to the next position.

Compare
Any 8-bit data, or the contents of register, or memory
location can be compares for:
Equality
Greater Than
Less Than
with the contents of accumulator.
The result is reflected in status flags.

Complement
The contents of accumulator can be complemented.
Each 0 is replaced by 1 and each 1 is replaced by 0.

1,2. Logical Instructions
ANA R
M
Register
Indirect
Logical AND register or
memory with accumulator
The contents of the accumulator are logically ANDed with the
contents of register or memory.
The result is placed in the accumulator. It is used to reset the bits.
If the operand is a memory location, its address is specified by the
contents of H-L pair.
S, Z, P are modified to reflect the result of the operation.
CY is reset (CY= 0) and AC is set (AC=1) for AND operation.
Example: ANA B or ANA M.

B 10 C
D E
H L
A
B 0F C
D E
H L
A 0A
AFTER EXECUTION
ANA B
A=A and R
B 0F C
D E
H L
A AA
BEFORE EXECUTION
CY AC CY 0 AC 1
CY AC CY 0 AC 1
A 11A 55
H 20 L 50 H 20 L 50
B3 B3
2050H
ANA M
A=A and M
2050H
1010 1010=AAH
0000 1111=0FH
0000 1010=0AH
0101 0101=55H
1011 0011=B3H
0001 0001=11H

3. Logical Instructions
ANI 8-bit data Immediate. Logical AND immediate
with accumulator
The contents of the accumulator are logically ANDed with the
8-bit data.
The result is placed in the accumulator.
S, Z, P are modified to reflect the result.
CY is reset (CY= 0) and AC is set (AC=1) for AND operation.
Example: ANI 86H.

CY AC
A B3
CY 0 AC 1
A 33
ANI 3FH
A=A and
DATA(8)
1011 0011=B3H
0011 1111=3FH
0011 0011=33H

4, 5. Logical Instructions
ORA R
M
Register
Indirect
Logical OR register or
 The contents of the accumulator are logically ORed with the contents of the register or
memory.
 The result is placed in the accumulator. It is used to set the bits.
 If the operand is a memory location, its address is specified by the contents of H-L pair.
 S, Z, P are modified to reflect the result.
 CY and AC are reset (CY = AC = 0) for OR operation.
 Example: ORA B or ORA M.

CY AC ORA B
A=A or R
1010 1010=AAH
0001 0010=12H
1011 1010=BAH
B 12 C
D E
H L
A AA
B 12 C
D E
H L
A BA
CY 0 AC 0

CY AC
ORA M
A=A or M
0101 0101=55H
1011 0011=B3H
1111 0111=F7H
H 20 L 50
A 55 A F7
CY 0 AC 0
H 20 L 50
B3 B32050H 2050H

ORI 8-bit data Immediate Logical OR immediate with
accumulator
The contents of the accumulator are logically ORed with the 8-
bit data.
CY and AC are reset (CY = AC = 0) for OR operation.
Example: ORI 86H.

CY AC
A B3
CY 0 AC 0
A BB
ORI 08H
A=A or DATA(8)
1011 0011=B3H
0000 1000=08H
1011 1011=BBH

7,8. Logical Instructions
XRA R
M
Register
Indirect
Logical XOR register or
 The contents of the accumulator are XORed with the contents of the register or
memory.
 The result is placed in the accumulator. It is used to set/reset the bits.
 If the operand is a memory location, its address is specified by the contents of H-L
pair.
 S, Z, P are modified to reflect the result of the operation.
 CY and AC are reset (CY = AC = 0) for Ex-OR operation.
 Example: XRA B or XRA M.

B 10 C
D E
H L
A
B C 2D
D E
H L
A 87
AFTER EXECUTION
XRA C
A=A xor R
B C 2D
D E
H L
A AA
BEFORE EXECUTION
CY AC CY 0 AC 0
1010 1010=AAH
0010 1101=2DH
1000 0111=87H

H 20 L 50
A 55
AFTER EXECUTION
XRA M
A=A xor M
BEFORE EXECUTION
CY AC CY 0 AC 0
0101 0101=55H
1011 0011=B3H
1110 0110=E6H
H 20 L 50
A E6
B3 B32050H 2050H

XRI 8-bit data Immediate XOR immediate with
accumulator
The contents of the accumulator are XORed with the 8-bit
data.
CY and AC are reset (CY = AC = 0) for Ex-OR operation.
Example: XRI 86H.

CY AC
A B3
CY 0 AC 0
A 8A
XRI 39H
A=A xor DATA(8)
1011 0011=B3H
0011 1001=39H
1000 1010=8AH

CMA None Implicit Complement accumulator
The contents of the accumulator are complemented.
No flags are affected.
Example: CMA.

A 55
A AA
CMA
01010101 = (55H) 101010101 =
(AAH)
1’s complement

CMC None Implicit Complement carry Flag
The Carry flag is complemented.
No other flags are affected.
Example: CMC.

CY 1
CY 0
CMC

STC None Implicit Set carry Flag
The Carry flag is set to 1.
No other flags are affected.
Example: STC.

CY 0
CY 1
STC
CY=1

13, 14. Logical Instructions
CMP R
M
Register
Indirect
Compare register or
The contents of the operand (register or memory) are
compared with the contents of the accumulator.
Both contents are preserved.
The result of the comparison is shown by setting the
flags of the PSW as follows:

13,14. Logical Instructions …cont..
if (A) < (reg/mem): carry flag is set (CY = 1)
if (A) = (reg/mem): zero flag is set (Z = 1)
if (A) > (reg/mem): carry and zero flags are reset
(CY = Z = 0)
Example: CMP B or CMP M

B 10 C
D E
H L
A
B C
D 99 E
H L
A 77
AFTER EXECUTION
CMP D
A-R
B C
D 99 E
H L
A 77
BEFORE EXECUTION
CY Z CY 1 Z 0
CY Z CY 0 Z 0
A 55A 55
H 20 L 50 H 20 L 50
32 32
2050H
CMP M
A-M
2050H
A>R: CY=0,Z=0
A=R: CY=0,Z=1
A<R: CY=1,Z=0
A>M: CY=0,Z=0
A=M: CY=0,Z=1
A<M: CY=1,Z=0

CPI 8-bit data Immediate Compare immediate with
accumulator
The 8-bit data is compared with the contents of
accumulator.
The values being compared remain unchanged.
The result of the comparison is shown by setting the
flags of the PSW as follows:

15. Logical Instructions cont..
if (A) < (data): carry flag is set (CY = 1)
if (A) = (data): zero flag is set (Z = 1)
if (A) > data): carry and zero flags are reset. (CY = Z = 0)
Example: CPI 89H

CY Z
A BA
CY 0 Z 0
A BA
CPI 30H
A-DATA
A>DATA: CY=0,Z=0
A=DATA: CY=0,Z=1
A<DATA: CY=1,Z=0
1011 1010=BAH

RLC None Implicit Rotate accumulator left
Each binary bit of the accumulator is rotated left by
one position.
Bit D7 is placed in the position of D0 as well as in the
Carry flag.
CY is modified according to bit D7.
S, Z, P, AC are not affected.
Example: RLC.

B7 B6 B5 B4 B3 B2 B1 B0CY
B6 B5 B4 B3 B2 B1 B0 B7B7
AFTER EXECUTION
BEFORE EXECUTION
CY 0
A A7
RLC
0 1010 0111 1 0100 1111
CY A CY A
CY 1
A 4F

RAL None Implicit Rotate accumulator left
through carry
Each binary bit of the accumulator is rotated left by one
position through the Carry flag.
Bit D7 is placed in the Carry flag, and the Carry flag is placed in
the least significant position D0.
Example: RAL.

B7 B6 B5 B4 B3 B2 B1 B0CY
B6 B5 B4 B3 B2 B1 B0 CYB7
AFTER EXECUTION
BEFORE EXECUTION
CY 0
A A7
RAL
0 1010 0111 1 0100 1110
CY A CY A
CY 1
A 4E

RRC None Implicit Rotate accumulator right
Each binary bit of the accumulator is rotated right by one
position.
Bit D0 is placed in the position of D7 as well as in the Carry
flag.
Example: RRC.

B7 B6 B5 B4 B3 B2 B1 B0 CY
B0 B7 B6 B5 B4 B3 B2 B1 B0
AFTER EXECUTION
BEFORE EXECUTION
CY 0
A A7
RRC
0 1010 0111 1 1101 0011
CY A CY A
CY 1
A D3

RAR None Implicit Rotate accumulator right
through carry
Each binary bit of the accumulator is rotated right by one
position through the Carry flag.
Bit D0 is placed in the Carry flag, and the Carry flag is
placed in the most significant position D7.
Example: RAR.

B7 B6 B5 B4 B3 B2 B1 B0 CY
CY B7 B6 B5 B4 B3 B2 B1 B0
AFTER EXECUTION
BEFORE EXECUTION
CY 0
A A7
RAR
0 1010 0111 1 0101 0011
CY A CY A
CY 1
A 53

Concept of Subroutine
In 8085 microprocessor a subroutine is a separate program written
aside from main program ,this program is basically the program which
requires to be executed several times in the main program.
The microprocessor can call subroutine any time using CALL
instruction. after the subroutine is executed the subroutine hands over
the program to main program using RET instruction.
When the subroutine is called the content of PC is stored on the stack,
and program execution is transferred to the subroutine address. When
the Return instruction is executed at the end of the subroutine, the
memory address stored in the stack is retrieved and the sequence of
execution is resumed in the main program.
3 types of subroutine is generally used
1. Multiple CALL subroutine
2. Nested subroutines
3. Multiple ending subroutine.

1. Multiple CALL Subroutine
Subroutine called from
memory location in the main
program.
For Ex - Delay routine is
called multiple CALL
subroutine. These routine are
easy to trace and need
minimal stack space.

2. Nested Subroutine
When subroutine is called by
another subroutine it is
called nested subroutine.
When a subroutine calls
another subroutine, all
return address are stored on
the stack.
Therefore the number of
available stack locations
limits the extent of nesting.

3. Multiple Ending
Subroutine
When subroutine can be terminated at more
than one place, is called a multiple ending
subroutine.
The subroutine has conditional returns RZ, RC
and unconditional return
When the Z flag is set, the subroutine returns
from the location 8050H and if CY is set then
return from the location 8090.

Branching Instructions
The branching instruction alter the normal sequential flow.
The branch group instructions allows the microprocessor to
change the sequence of program either conditionally or
under certain test conditions.
The group includes,
(1) Jump instructions,
(2) Call and Return instructions,
(3) Restart instructions,

1. Branching Instructions
JMP 16-bit
address
Immediate Jump unconditionally
The program sequence is transferred to the memory
location specified by the 16-bit address given in the
operand.
Example: JMP 2000 H.
PC 5000 PC 2000JMP 2000H

2-9. Branching Instructions
Jx 16-bit address Immediate Jump conditionally
The program sequence is transferred to the memory location
specified by the 16-bit address given in the operand based on
the specified flag of the PSW.
If the condition is true then only jump is made at the
specified address. If the condition is false or not satisfied then
the next instruction in the sequence is executed.
Example: JZ 2034 H.
If condition is true
PC add(label)
Else
PC PC+3 (i.e. Execute
next
instruction in sequence.)

2-9. Jump Conditionally
Opcode Description Status Flags
JC Jump if Carry CY = 1
JNC Jump if No Carry CY = 0
JP Jump if Positive S = 0
JM Jump if Minus S = 1
JZ Jump if Zero Z = 1
JNZ Jump if No Zero Z = 0
JPE Jump if Parity Even P = 1
JPO Jump if Parity Odd P = 0

PC 5000
Z 1 JZ 7000H
PC 7000
Z 1
So the next instruction will be executed from 7000 because condition is true i.e. Z=1.
PC 5000
Z 0
JZ 7000H
PC 5000
Z 0
PC+3
So the next instruction will be executed from 5003 because condition is false i.e. Z=0.

CALL 16-bit address Indirect/Immediate Call unconditionally
The program sequence is transferred to the memory location
specified by the 16-bit address given in the operand.
Before the transfer, the address of the next instruction after
CALL (the contents of the program counter) is pushed onto
the stack. The content of stack pointer is decremented by 2.
Then the program jumps to specified label.
Example: CALL 2034 H.

PC 6000
SP 7000
CALL 5000H
PC 5000
SP 6FFE
6FFE 00
6FFF 60
SP-1 PCH
SP-2 PCL
SP SP-2
PC addr(label)

Cx 16-bit
address
Indirect/Immediate Call conditionally
The program sequence is transferred to the memory
location specified by the 16-bit address given in the operand
based on the specified flag of the PSW.
Before the transfer, the address of the next instruction after
the call (the contents of the program counter) is pushed
onto the stack.
3 bytes instruction.
Example: CZ 2034 H.

Call Conditionally
CC Call if Carry CY = 1
CNC Call if No Carry CY = 0
CP Call if Positive S = 0
CM Call if Minus S = 1
CZ Call if Zero Z = 1
CNZ Call if No Zero Z = 0
CPE Call if Parity Even P = 1
CPO Call if Parity Odd P = 0

11-18. CALL Conditionally
SP-1 PCH
SP-2 PCL
SP SP-2
PC addr(label)
Else
PC PC+3 (i.e. Execute next instruction in
sequence.)

PC 6000
SP 5000
Z 0
CZ 7000H
PC 6003
SP 5000
Z 0
PC+3
This program does not call a subroutine because condition is false i.e. Z= 0.
PC 6000
SP 5000
Z 1
CZ 7000H
PC 7000
SP 4FFE
Z 1
This program calls a subroutine from
7000 because condition is true i.e. Z= 1.
4FFE 00
4FFF 60

Opcode Operand Addressing
modes
Description
RET None Indirect Return unconditionally
The program sequence is transferred from the subroutine to
the calling program. The execution of RET brings back the
saved address from the stack to the program counter.
The content of stack counter is incremented by 2. then the
program jumps to the next instruction after CALL in the
main program.
Example: RET.

PC 2000
SP 7000 RET
PC 5000
SP 7002
7000 00
7001 50
7000 00
7001 50
So the next instruction will be executed from 5000 instead of 2000.

Rx None Indirect Call conditionally
The program sequence is transferred from the subroutine to
the calling program based on the specified flag of the PSW.
The two bytes from the top of the stack are copied into the
program counter, and program execution begins at the new
address.
Example: RZ.

Return Conditionally
RC Return if Carry CY = 1
RNC Return if No Carry CY = 0
RP Return if Positive S = 0
RM Return if Minus S = 1
RZ Return if Zero Z = 1
RNZ Return if No Zero Z = 0
RPE Return if Parity Even P = 1
RPO Return if Parity Odd P = 0

20-27. Return Conditionally
PCL SP
PCH SP+1
SP SP+2
Else
PC PC+1 (i.e. Execute next instruction in
sequence.)

PC 2000
SP 7000
Z 1
RZ
PC 5000
SP 7002
Z 1
This program will return from subroutine to main program and start the execution
of instruction from 5000 because Z=1.
RZ
7000 00
7001 50
7000 00
7001 50
PC 2000
SP 7000
Z 0
PC 2001
SP 7000
Z 0
This program does not return from subroutine to main program because condition
is false i.e. Z=0.
7000 00
7001 50
7000 00
7001 50

28. Branch/Data Transfer Instructions
PCHL None Register Load program counter with
H-L contents
The contents of registers H and L are copied into the
program counter (PC).
The contents of H are placed as the high-order 8 bit of
PC and the contents of L are transferred to low order 8
bits of register PC.
 1 byte instruction
Example: PCHL
PC HL
PCH H
PCL L

H 70 L 00
PC 5000
H 70 L 00
PC 7000
PCHL
The program start the execution of instruction from 7000.
This instruction is equivalent to 1 byte unconditional JUMP
instruction, provided the address of JUMP is specified by HL
pair.

Stack, I/O and Machine Control
Instructions
The instruction of this group perform I/O data transfer,
manipulates the stack and perform machine related
operations.
Stack, I/O and machine control
PUSH
POP
XTHL
SPHL
IN
OUT
HLT
NOP

STACK
It is a reserved place at the top of memory map.
Stack can be initialized anywhere in the memory
map but it is initialize at the highest user memory
location so it will not interface with the program.
Beginning of stack is defined in the program by
instruction
LXI SP, 16 bit
It loads the 16 bit address into the stack. Then the
content of BC and HL can be stored in two
consecutive stack memory location by using Push
and can be retrieved by POP instruction.
The address in the SP always points to the top of the
Stack and indicates that the next memory location
(SP-1) is available to store information.

STACK PUSH Operation

STACK POP Operation

1. Stack Operation
PUSH Reg. pair Indirect Push register pair onto stack
The contents of register pair are copied onto stack.
SP is decremented and the contents of high-order registers
(B, D, H, A) are copied into stack.
SP is again decremented and the contents of low-order
registers (C, E, L, Flags) are copied into stack.
Example: PUSH B
[[SP] – 1] [Rh]
[[SP]-2 ] [Rl ]
[SP] [SP]-2

2. Stack Operation
PUSH PSW Indirect Push PSW onto stack
The contents processor status word (PSW) is pushed or copied
onto the stack..
SP is decremented and the contents of accumulator are copied
into stack.
SP is again decremented and the content flag copied into stack.
Example: PUSH PSW
A Flags
Processor status word(PSW)
[[SP] – 1] [A]
[[SP]-2 ] [Flag]
[SP] [SP]-2

3. Stack Operation
POP Reg. pair Indirect Pop stack to register pair
The contents of top of stack are copied into register pair.
The contents of location pointed out by SP are copied to the low-order
register of register pair (C, E, L, Flags).
SP is incremented and the contents of location are copied to the high-
order register of register pair (B, D, H, A).
Example: POP H
[Rl] [[SP]
[Rh ] [[SP]+1]
[SP] [[SP]+2]

4. Stack Operation
POP PSW Indirect Pop stack Processor status
word
POP the content of processor status word from the stack.
The contents of location pointed out by SP are copied to Flag
or program status word(PSW).
SP is incremented and the contents of location are copied to
the accumulator. The SP is again incremented by one.
Example: POP PSW
[Flags] [[SP]
[A] [[SP]+1]
[SP] [[SP]+2]

5. Stack Operation
XTHL None Indirect Exchange H–L with top of
stack
Exchange stack top with HL pair.
The contents of L register are exchanged with the location pointed out by
the contents of the SP.
The contents of H register are exchanged with the next location (SP + 1).
The content of the stack pointer register are not altered or affected.
Example: XTHL

H
30
L
40
SP 2700
BEFORE EXECUTION
50
60
H
60
L
50
SP 2700 40
30
AFTER EXECUTION
XTHL
2700H
2701H
2702H
2700H
2701H
2702H
L=[[SP]]
H=([SP]+1)

6. Stack operations
SPHL None Register Copy H-L pair to the Stack
Pointer (SP)
The content of HL pair are moved to the SP register.
Example: SPHL

H 25 L 00
SP 7000
BEFORE EXECUTION
AFTER EXECUTION
H 25 L 00
SP 2500
SPHL

7. I/O Instructions
IN 8-bit port
address
Direct Copy data to accumulator from a
port with 8-bit address
The contents of I/O port are copied into accumulator.
 After the IN instruction, the address of port is
specified. Port address in 8bit address.
Example: IN 8C H

02 77
A 55
02 77
A 77
BEFORE EXECUTION
AFTER EXECUTION
IN 02H
PORT
80H
PORT
80H
This instruction will copy the content at port whose
address is 02H into accumulator.

OUT 8-bit port
address
Direct Copy data from accumulator to a
port with 8-bit address
The contents of accumulator are copied into the I/O
port.
After the instruction OUT, the address of port is
specified. Port address is an 8 bit address.
Example: OUT 78 H
8. I/O Instructions

A 55
02 77
A 55
02 55
BEFORE EXECUTION
AFTER EXECUTION
OUT 02H
PORT
50H
PORT
50H
This instruction will copy the content of accumulator to
the output port whose address is specified in the
instruction.

9. Control Instructions
HLT None None Halt
The CPU finishes executing the current instruction and
halts any further execution.
Stops the microprocessor. Register and Flags remain
unaffected.
Example: HLT

NOP None None No operation
No operation is performed.
The instruction is fetched and decoded but no
operation is executed.
Register and Flag remain unaffected.
Example: NOP

1. Interrupt Control Group
RST 0 – 7 Indirect Restart (Software
Interrupts)
The RST instruction jumps the control to one of eight
memory locations depending upon the number.
Restart is a one word CALL instruction.
These are used as software instructions in a program to
transfer program execution to one of the eight locations.
Example: RST 3.
[[SP] – 1] [PCH]
[[SP]-2 ] [PCL]]
[SP] [SP]-2
[PC] 8 times n

Restart Address Table
Instructions Restart Address
RST 0 0000 H
RST 1 0008 H
RST 2 0010 H
RST 3 0018 H
RST 4 0020 H
RST 5 0028 H
RST 6 0030 H
RST 7 0038 H

SP 5000
PC 7000
SP 4FFE
PC 0018
00
70
RST 3
5000H
4FFFH
4FFEH
SP-1
The next instruction will be executed from 0018.
5000H
4FFFH
4FFEH

EI None None Enable interrupt
The interrupt enable flip-flop is set and all interrupts are
enabled.
This instruction is necessary to re-enable the interrupts
(except TRAP).
Example: EI

DI None Indirect Disable interrupt
The interrupt enable flip-flop is reset and all the
maskable interrupts except the TRAP are disabled.
Example: DI

SIM None Indirect Set Interrupt Mask
This is a multipurpose instruction and used to
implement the 8085 interrupts 7.5, 6.5, 5.5, and serial
data output.
The instruction interprets the accumulator contents as
follows.
Example: SIM

SIM Instruction
Interrupt Control
Serial output
data control

RIM None None Read Interrupt Mask
This is a multipurpose instruction used to read the
status of interrupts 7.5, 6.5, 5.5 and read serial data input
bit.
The instruction loads eight bits in the accumulator with
the following interpretations.
Example: RIM

RIM Instruction
Interrupt MaskPending InterruptSID

Chapter 3 instruction set-of-8085

Program 1: Transfer data from
accumulator to B register
Program 2: Load FFH in Register C.
Program 3: Load 22H and 67H in Register B
& C respectively.

Program 4: Load HL register pair by the
data 8150H
Program 2: Load FFH in Register C.
Program 3: Load 22H and 67H in Register B
& C respectively.

Program 1: Addition of two 8 bit
numbers with 8 bit sum
Algorithm
1. Initialize the memory location of the first
number in HL register pair.
2. Move the first number into accumulator.
3. Increment the content of HL register pair
to Initialize the memory location of second
data.
4. Add the second data with the accumulator.
5. Store the result in memory location 8003H.

Chapter 3 instruction set-of-8085

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Chapter 3 instruction set-of-8085