Computer Architecture and Organization--Memory and I/O

MEMORY AND I/O ORGANIZATION
Memory hierarchy, Memory Chip Organization, Cache
memory, Virtual memory. Parallel Bus Architectures,
Internal Communication Methodologies, Serial Bus
Architectures, Mass storage, Input and Output Devices.

Memory hierarchy
Memory unit enables us to store data inside the computer
desirable properties of memory:
• Large Size
• Speed of Access: little accessing time
principle of locality:
tendency of a processor to access the same set of memory
locations repetitively over a short period of time
two basic types of reference locality –
1.temporal locality
• The location of the variable counter may be accessed frequently in a loop.
• A branching instruction may be accessed repeatedly in a given period of
time.
 reuse of specific data, and/or resources, within a relatively
small time duration
 if an item is referenced, it will tend to be referenced again soon

2. Spatial locality ( data locality) -use of data elements within relatively
close storage locations.
 if an item is referenced, items whose addresses are close by will
tend to be referenced soon.
• -If we access the location of A[0], we will probably also be accessing
A[1], A[2], etc.

 consisting of multiple levels of memory with varying speed and
size, exploits these principles of locality
 faster memories are more expensive per bit than the slower
memories
Memory hierarchy
smallest, faster memory
unit closest to the processor.
 access time during a running program
= the access time of the level 1 unit.
 memory capacity is as large as the
level n unit.
Memory level vs Access Time

top of the hierarchy are registers
- are matched in speed to the CPU
-large and consume a significant amount of power.
-only a small number of registers in a processor, on the
order of a few hundred or less.
bottom of the hierarchy
-are secondary and off-line storage memories(hard magnetic
disks and magnetic tapes)
-cost per stored bit is small
- access time is very long compared with registers.
memory hierarchy

Properties of the memory hierarchy
Typical Cost = Cost/MB × Typical Amount Used
Access times of disk is 100,000 times slower than main memory
how the operating system handles the movement of blocks of data
between disks and main memory?

There are four technologies that are used in a memory hierarchy:
• SRAM (Static Random Access Memory): fastest memory available.
Used in memory units close to the processor called caches. Volatile.
• DRAM (Dynamic Random Access Memory): mid-range. Used in main
memory. Volatile.
• Flash: Falls between DRAM and disk in cost and speed. Used as non-
volatile memory, used in personal mobile devices.
• Magnetic Disk: slowest memory available. Used as non-volatile
memory in a server or PC.

Random Access Memory
- any memory location can be randomly accessed in the same amount
of time, regardless of its position in the memory.
functional behavior of a RAM cell
Static RAM cell dynamic RAM cell

static RAM (SRAM) - the contents of each location persist as long as power is
applied to the chips
Dynamic RAM(DRAM) -has a capacitor, which stores electric charge (charge
level represents a 1 or a 0.
-As the charges dissipate with time, restored, or refreshed frequently.
memory element is D flip-flop
Additional controls to allow the cell to be selected, read and written.
data line (bidirectional) for data input and output.

MEMORY HIERARCHY TERMS
• Hit: item found in a specified level of the hierarchy.
• Miss: item not found in a specified level of the hierarchy.
• Hit time: time required to access the desired item in a specified level
of the hierarchy (includes the time to determine if the access is a hit or
a miss).
• Miss penalty: the additional time required to service the miss.
• Hit rate: fraction of accesses that are in a specified level of the
hierarchy.
• Miss rate: fraction of accesses that are not in a specified level of the
hierarchy.
• Block: unit of information that is checked to reside in a specified level
of the hierarchy and is retrieved from the next lower level on a miss.

Block(line)
The unit of data that is transferred between two levels is fixed in size and
is called a block
Data transfer in memory

Chip Organization
Simplified RAM chip pinout
m -bit address (0 to m -1) is applied to pins A0 to Am-1
(Chip Select) is asserted(high-1) to select the chip
is asserted(high-1) for writing data to the chip
WR is asserted(high-1) for reading data from the chip.
W -bit data word appears on the data lines D0 to Dw-1
tAA - time delay between validity of the address lines and availability
of data at the output
𝐂𝐒
𝐖𝐑
data lines
address lines
bidirectional
1. Random Access Memory(RAM)
2. Read only memory(ROM)
1. Random Access Memory(RAM)

 m -bit address is decoded into 2m
locations within the chip
 each location has a w -bit words
 The chip contains 2m
× wbits.
Design of a memory
creating a RAM that stores four-bit words.
- RAM is a collection of registers
- four-bit registers to store the words
- 2 bit address to select one of the words
 A0 and A1 select a word for reading or writing via the 2-to-4 decoder.
 2-to-4 decoder enable one of the register at a time
 disabled registers are electrically disconnected through tri-state
buffers.

four-word memory with four bits per word
simplified representation of RAM
4x4= 4 word(2 bit address)
with 4 bit each
64M×1 chip has 26 address
lines (64M = 226
) with 1 bit
word
Increases decoder complexity
and chip area

2-1/2D organization
 reduces the decoder complexity by decoding the rows separately from the columns
 26
word× 1-bit RAM, 6 address lines
 6 address lines are split into row decoder and column decoder (the
column decoder -MUX/DEMUX combination).
 single bidirectional data line is for input and output.
 During a read operation, entire row is selected and fed into the
columnMUX, which selects a single bit for output
 During a write operation, row decoder selects the proper row, bit to
be written is distributed by the DEMUX to the target column
 row and column addresses are time-multiplexed , Only m/2 address pins
on the chip,
 First, m/2-bit row address is applied along with a row address strobe
signal, RAS.
 Then m/2-bit column address is applied, along with a column address
strobe, CAS.
control signals for chip refresh and other memory functions.

2-1/2D organization of 64-word by one-bit RAM.

CONSTRUCTING LARGE RAMS FROM SMALL RAMS
eight 16M ×1-bit RAM =16M×8-bit RAM module
Thirty two 16M×1-bit (24 bit address)RAM modules = 64M×8-bit RAM (26 address)module.
Design 4-word × 8-bit module from 4 word×4-bit RAM chip
tying their CS (chip select) lines together so they are both selected together

eight-word by four-bit RAM from two four-word by four-bit RAMs
eight words -23
(3Address line,
A0 ,A1, A2
decoder for A2enables either
upper or lower memory by
using the CS lines
A0 and A1 are decoded
within the enabled module

Commercial Memory Modules
single-in-line memory module (SIMM)
220
×8 (1MB) module
need 20 address lines
but only 10 address lines (A0 – A9)
The 10-bit addresses for the row and
column are loaded separately by
Column Address Strobe and Row
Address Strobe signals are applied
eight data bits DQ1 – DQ8 form a byte that is read or written in parallel.
RAS for refresh operation
Write( ) takes place when a 0 is placed on this line
For 32-bit word, four SIMM
modules are needed

2. Read-Only Memory(ROM)
Used in applications, where the program never changes
eg. store programs in videogames, calculators, microwave
ovens, and automobile fuel injection controllers etc.
no need for flip-flops or capacitors in ROM
Four four bit-word ROM

PROMs will be used for control units and for arithmetic logic units
(ALUs)
ALU performs four functions: Add, Subtract, Multiply, and Divide on
eight-bit operands
lookup table (LUT) approach
-generate a truth table for 22
combinations of functions and 216
(28
× 28
combinations of the two input operands ) combinations of
operands
-total of 28
× 28
× 22
= 218
words
-send the truth table to a PROM burner which loads it into the
PROM
Applications

address lines are used for the operands and function select inputs,
64-bit operands today, PROM ALU require 264
× 264
× 22
= 2130
words
lookup table (LUT) implements an eight-bit ALU

Types of ROMs
1. Programmable read only memory(PROM)
For high-volume applications, ROMs are factory-programmed
for low-volume or prototyping applications, programmable ROMs (PROMs) are used
allow the contents to be written by a user with the device called a PROM
burner(written once)
allow reading and duplicating the content
2. Erasable PROMs (EPROMs)
a. UVPROMs
Data can be written several times, after being erased with ultraviolet light
through a window that is mounted on the integrated circuit package
b. Electrically erasable PROMs (EEPROMs)
- allow their contents to be rewritten electrically.
- Newer flash memories can be electrically rewritten tens of thousands of times
-used extensively in digital video cameras, and for control programs in set-top
cable television decoders, and other devices.

Cache Memory
 cache memory : A small , fast memory in which the contents of the
most commonly accessed locations are maintained.
principle of locality:
Tendency of a processor to access the same set of memory
locations repetitively over a short period of time
two basic types of reference locality –
1.temporal locality
2. Spatial locality
 placed between the main memory and the CPU
 locality principle can be exploited in order to improve performance
 When a program executes, the cache memory is searched first
• if referenced word is present,
-referenced word is accessed in the cache
• referenced word is not in the cache,
- free location is created in the cache and the referenced word is
brought into the cache from the main memory

• The location of the variable counter may be accessed frequently in a loop.
• A branching instruction may be accessed repeatedly in a given period of
time.
 reuse of specific data, and/or resources, within a relatively
small time duration
 if an item is referenced, it will tend to be referenced again soon
1.temporal locality
2. Spatial locality ( data locality) -use of data elements within relatively
close storage locations.
 if an item is referenced, items whose addresses are close by will
tend to be referenced soon.
• -If we access the location of A[0], we will probably also be accessing
A[1], A[2], etc.

Computer Architecture and Organization--Memory and I/O

1.ASSOCIATIVE MAPPED CACHE(content-addressable)
hardware translate the main memory addresses to cache memory
addresses
 232
word memory space is divided into 227
blocks of 25
= 32 words per block.
 Cache blocks, or cache lines, ( size from 8 to 64 bytes)
- cache consists of 214
slots into which main memory blocks are placed.
 227
main memory blocks can be mapped into each cache slot
(with only one block placed in a slot at a time)
- each slot contains 27-bit tag field to keep track of which one of the
227
possible blocks is in each slot
- Tag field is 27 bits(MSB) of 32-bit memory address to the cache
- All the tags are stored in a special tag memory
A fully associative cache permits data to be stored in any cache block, instead of forcing
each memory address into one particular block. — When data is fetched from memory, it
can be placed in any unused block of the cache.
process
For mapping, the address
is partitioned into tag and
word fields

-If the referenced location is found in the cache results in a hit,
otherwise, the result is a miss.
 program is initially loaded into memory, the valid bits are all set to 0
-first instruction cause a miss, since none of the program is in cache
- block that causes the miss is located in the main memory and is loaded into
the cache
 When a reference is made to a main memory address , cache searches the cache
tag memory to see if the requested block is in the cache.
 For each slot, if the valid bit is 1, then the tag field of the referenced address is
compared with the tag field of the slot
-If matches, word is taken from the position in the slot specified by the word
field.
If not found in the cache, main memory block that contains the word is
brought into the cache and the referenced word is then taken from the cache
• tag, valid, and dirty fields are updated, and the program resumes execution.
 a valid bit in each slot indicate whether the slot holds a block that belongs to the
program being executed.
 dirty bit in each slot keeps track of whether a block has been modified while it is
in the cache.

Associative mapping scheme for a 232
word memory space

 If addressed word is not in cache,
-block corresponding to the tag field (501AF80)16 will be brought into an available slot
in the cache from the main memory,
1. process of deciding which slot should be freed when a new block is brought into
the cache is complex
2. tag field of the referenced address Is compared with all 214
tag fields in the cache
Dis advantage
Example
Replacement Policies in Associative Mapped Caches
If all valid bit are 1, one of the active slots must be freed for the new block
1.least recently used (LRU)
2 first-in first-out (FIFO)
3.least frequently used (LFU)
4. random.
5. is optimal.

• more main memory blocks than there are cache slots
2. DIRECT MAPPED CACHE
 232
word memory space is divided into 227
blocks of 25
= 32 words per
block.
 cache consists of 214
slots into which main memory blocks are placed
 This method restrict where each main memory block can be placed
in the cache
direct mapping scheme
for cache memory

 each main memory block can be mapped to only one slot, but each
slot can receive more than one block.
 mapping is performed by partitioning an address into fields for the tag, the
slot, and the word
total of 227
/214
= 213
main memory blocks can be mapped onto each
cache slot
 tag field(13 bit-in each slot) :keep track of which blocks(213
)
are in each slot
 each cache slot corresponds to an explicit set of main memory blocks
 slot field : keep track of which slots(214
) contain each block, if the
block is in the cache

 tag fields are not same
- slot is written back to main memory if the dirty bit is set
- corresponding main memory block is read into the slot
 If the valid bit is 1, tag field of the referenced address is compared
with the tag field of the slot.
 If tag fields are same,
-the word is taken from the position in the slot specified by the word field
memory location (A035F014)16 is mapped to the cache
word (14)16 , slot (2F80)16, tag (1406)16.
Advantages and Disadvantages of the Direct Mapped Cache
1. Simple
2. Tag memory (13 × 214
bits) size is less than half of the associative mapped cache.
3. small fraction of the available cache memory will actually be used

3. SET ASSOCIATIVE MAPPED CACHE
combines the simplicity of direct mapping with the flexibility of
associative mapping
associative portion is limited to just a few slots that make up a set
set associative mapping scheme
two blocks make up a set - two-way set associative cache
four blocks per set- four-way set associative cache.
 214
slots in the cache, there are 214
/2 = 213
sets

 When address is mapped to a set, direct mapping scheme is used, then associative mapping
is used within a set
32 bits of the address
set field(13 bits in the)- identifies the set in which the addressed word will be found
only two tags need to be searched for each memory reference

hit ratios and effective access times
-Measure of performance of a cache memory
Eff. access time=
Compute hit ratio and effective access time for a program that executes from memory locations
48 to 95, and then loops 10 times from 15 to 31
• The direct mapped cache has four 16-word slots, a hit time of 80 ns, and a miss time of 2500ns
Load-through is used. The cache is initially empty.

Multilevel Caches
-chip processing speed is faster than the speed of communication between chips
-on-chip cache can be faster than an off-chip cache
-Current technology is not dense enough to allow the entire cache to be placed on the
same chip as the processor
-multilevel caches have been developed
-L1, is on the same chip as the processor, and the remaining cache L2 is placed off of the
processor chip.
H1 - hit ratio for the on-chip cache,
H2 - hit ratio for the off-chip cache,
TEFF is the overall effective access time.

Cache Management
LRU(Least recently used) is the replacement policies for associative mapping
Neat Little LRU Algorithm
LRU Algorithm for a cache with four slots
• Initially, all of the cells are set to 0
When a slot is accessed, 1’s are written into each cell in the row of the table,
0’s are written into each cell in the column that corresponds to that slot.
Block 5 is then brought into slot 0(least recently used slot.)
when block 4 is brought into the cache, slot 2 is overwritten

Virtual Memory
 Virtual memory uses hardware and software to allow a computer to
compensate for physical memory shortages, by temporarily transferring
data from random access memory (RAM) to disk storage
 overlaying means "the process of transferring a block of
program code or other data into main memory, replacing what
is already stored.
1.OVERLAYS
 program contains a main routine and three subroutines A, B, and C
• physical memory is smaller than the size of the
program and larger than any single routine
• programmer has the responsibility of Managing memory usage
Virtual memory is a memory management technique where secondary memory
can be used as if it were a part of the main memory.

 modify the program so that it keeps track of which subroutines are
in memory, and reads in subroutine code as needed
• main routine serves as the driver , which stays in memory while
other routines are brought in and out
 partition graph: identifies which routines can overlay others based on
which subroutines call others.
B calls C –they are kept in the
same partition
only the main routine calls A -
subroutine A is in its own
partition
Partition #0 can overlay
partition #1, partition #1 can
overlay partition #0.
partition graph for a program

2. paging
 Pages: address space is partitioned into equal sized blocks, called
pages(210
= 1024 bytes).
 mapping the physical memory address space to some portion of
the virtual memory address space(stored on a disk)
address mapping or address translation:
virtual address(produced by processor-stored on a disk) is
translated into a physical address(main memory) in order to access
main memory.
A virtual address can translate to one physical (or disk) address,
multiple virtual addresses may translate to the same physical (or disk)
address.
page fault: referenced virtual location is not in physical memory
 a form of automatic overlaying ,managed by the operating system.

Eight virtual pages are mapped
to four physical page frames.
mapping between a virtual and a physical memory
program executed has 13-bit addresses, and 213
= 8192 virtual locations
13-bit addresses is interpreted as 3-bit page number and a 10-bit offset
within the page.
3-bit page number, find out where the page is:
-either in one of the four page frames, or in secondary memory.
page table : keep track of which pages are in physical memory

page table for a virtual memory.
present bit -
indicates whether the corresponding page is in physical memory.
Disk address field - pointer to indicate the corresponding page can be found on a disk.
page table
page frame field : indicates which physical page frame holds a virtual page, if the page is in
physical memory
xx-pages not in
physical memory

Address translation:
translate a virtual address to a physical address
physical address for the referenced word= page frame (2 bits) appended with
offset(10-bit )
virtual address 1001101000101. The three leftmost bits of the virtual address (100)
identify
-size of the virtual address space is 213
words, and the physical address space is 212
words
virtual address is partitioned into a
virtual page number and a page offset.
To translate a virtual address
- translate the virtual page
number into the physical page number
-The page offset remains the
same.

Demand paging scheme
-does not load a page into memory until there is a page fault
-time required to load the program from a disk into the memory can
be reduced by loading only the portion of the program that is needed
for a given interval of time

THE TRANSLATION LOOKASIDE BUFFER
-page table for a process is stored in main memory
-any access to main memory involves at least two references: one to
get the physical address and the other to get the data.
translation lookaside Buffer- Special cache(inside of the CPU) for storing
recently used translations
first time
given virtual address is translated into a physical address, this translation is
stored in the TLB.
-Each time the CPU issues a virtual address,
- TLB is searched for that virtual address.
If the virtual page number exists in the TLB, the TLB returns the physical
page number, and sent to the main memory

TLB that holds 8 entries for a system with 32 virtual pages and 16 page frames.
virtual page field is 5 bits wide
because there are 25
= 32 pages
physical page field is 4 bits wide
because there are 24
=16 page frames.

SEGMENTATION
 divides the address space into segments of any size
 allows for protection,
-a segment may be specified as “read only” to prevent changes,
- “execute only” to prevent unauthorized copying.
 protects users from trying to write data into instruction areas.
segmented memory allows two users to share the same word processor

 “execute only” - protected from writing.
 Segment #1 is for the data space for user #0(“read/write” for user #0)
that no other user can have access to this area.
 Segment #2 is used for the data space for user #1, and is marked as
“read/write” for user #1.
 The same word processor can be used by both user #0 and user #1, in
which case the code in segment #0 is shared, but each user has a
separate data segment.
address in a segmented memory
user’s program specify a segment number and an address
within the segment. The operating system then translates the
user’s segmented address to a physical address.

(a) Free area of memory after
Initialization
(b) after fragmentation
(c) after coalescing(merging).
Fragmentation
• When executing a process, it is loaded into the memory.
• After completing the execution, it is removed from the memory.
• Process of loading and removing create free spaces in memory.
• These spaces are small in size and cannot be allocated for some other process.
Therefore, those memory blocks remain unused.
https://pediaa.com/what-is-the-difference-between-fragmentation-and-segmentation/

 When computer is “booted up,” it loads the operating system into memory
 A portion of the address space is reserved for I/O devices
-remainder of the address space is available for use by the operating system.
-remaining portion of the address space is partially filled with physical memory
: the rest comprises a “Dead Zone” which never be accessed
“Free Area” -available to the operating system for loading and executing programs
 As programs are loaded and executed, the Free Area becomes subdivided into a
collection of small areas, none of which may be large enough to hold a program that
would fit unless some or all of the free areas are combined into a single large area.
This is a problem known as fragmentation
The free area will generally be larger than the program,
Therefore free areas are subdivided to match the program
method of assigning programs to free areas
1. first fit, -free areas are scanned until a large enough area is found that will satisfy
the program.
2. best fit- allocating the smallest free partition which meets the requirement of the
program.

S.NO VIRTUAL MEMORY CACHE MEMORY
1.
Virtual memory increases the capacity of
main memory.
While cache memory increase the
accessing speed of CPU.
2. Virtual memory is not a memory unit, its a
technique.
Cache memory is exactly a memory
unit.
3.
The size of virtual memory is greater than
the cache memory.
While the size of cache memory is less
than the virtual memory.
4.
Operating System manages the Virtual
memory.
On the other hand hardware manages
the cache memory.
5.
In virtual memory, The program with size
larger than the main memory are executed.
While in cache memory, recently used
data is copied into.
6.
In virtual memory, mapping frameworks is
needed for mapping virtual address to
physical address.
While in cache memory, no such
mapping frameworks is needed.
Difference between Virtual memory and Cache memory:

http://iiusatech.com/murdocca/CAO/caotoc.html
Bus Structure, Protocol, and Control
Bus Clocking
The Synchronous Bus
The Asynchronous Bus
Bus Arbitration--Masters and Slaves
Parallel Bus Architectures

Parallel Bus Architectures
bus : common pathway that connects a number of devices.
motherboard (the main circuit board that contains the central
processing unit) of a personal computer
motherboard of a
personal computer
connect the chips
bus is a communication system that transfers data between
components inside a computer, or between computers.

Bus Structure, Protocol, and Control
A bus consists of
1.physical parts, like connectors and wires
2. bus protocol.
wires are partitioned into separate groups for control, address,
data, and power
devices share a common set of wires
only one device may send and receives the data at any one time.
- All devices simultaneously listen
Only one device can be a bus master, and remaining devices are
slaves.
-The master controls the bus

Types of Buses
1. synchronous
2. asynchronous
Bus operations(Tx. and Rx.) are synchronized with the clock pulse
1. synchronous Bus
A 100 MHz bus clock
 bus clock speed is less than system clock speed (rate)
 Bus cycle : Number of bus clock cycles are required to effect a bus
transaction- two to five bus clock periods in duration

2. Asynchronous Bus
 It is more complex, because there is no bus clock
 Master slave system
 A master puts address, data, control that it needs on the bus, and
then asserts (master synchronization).
 The slave perform its job and asserts (slave synchronization)
when it is finished.
 The master then de-asserts , which signals the slave to de-
assert
Dis advantages
1.Asynchronous busses are more difficult to debug than synchronous
busses
2.interfaces for asynchronous busses are more difficult to fabricate

Timing diagram for asynchronous memory read

Bus Arbitration—Masters and Slaves
Bus arbitration problem :
more than one device wants to be a bus master at the same time
two basic schemes of arbitration
1. centralized
2. decentralized(distributed)

1. centralized
a. Simple centralized bus arbitration
 Devices 0 to n, are attached to
the same bus , and share a bus
request line that goes into arbiter.
 Arbiter Check bus grant , and asserts the bus grant line
 bus grant line is daisy chained from one device to the next
 device wants to be a bus master, asserts the bus request line
 first device that sees the asserted bus grant , if wants to be the bus master
-takes control of the bus and does not propagate the bus grant to higher
numbered devices.
 If a device does not want the bus, then it passes bus grant to
the next device

centralized arbitration with priority levels
b. centralized arbitration with priority levels
number of bus request/bus grant lines are used
Lower numbered bus request lines have higher priorities than
higher numbered bus request lines
To raise the priority -- device that is far from the arbiter can be
assigned to a lower numbered bus request line
Priorities are assigned within a
group on the same bus request level by arbiter

decentralized bus arbitration
2. decentralized bus arbitration
lack of a central arbiter
If the bus is busy(or if device does not want the bus), it propagates
the bus grant to the next device.
 device that wants to become a bus master first asserts the bus request
line
 If the bus is not busy(busy line is not asserted, device sends a 0 to the
next higher numbered device on the daisy chain,
asserts the busy line, and de-asserts the bus request line.
more appropriate for small number of devices

Communication between processors and memories
CPU communicate with
-memory, I/O devices, slow devices (keyboards) to high-speed
devices like disk drives and network interfaces.
-multiple CPUs that communicate with one another
Methods for managing input and output
1.programmed I/O (polling)
2. interrupt driven I/O
3. direct memory access (DMA).

1.programmed I/O (polling)
CPU first checks the status of the disk by
- reading a special register in the memory space or
- issuing a special I/O instruction
busy-wait.
 If the disk is not ready( read or write), then the -process
loops back and checks the status continuously until the
disk is ready
-If the disk is finally ready, data is transfer between the disk
and the CPU.
• After the transfer is completed, the CPU checks for
another communication request for the disk.
• If there is, then the process repeats, otherwise the
CPU continues with another task

Programmed I/O flowchart for a disk transfer
CPU wastes time by polling devices
high priority devices are not
checked until the CPU is finished
with its current I/O task

2.Interrupt-driven I/O
 device requests service through a special interrupt request line
that goes directly to the CPU
 The CPU issues a request to the disk for reading or writing, and
then immediately resumes execution of another process.
 disk interrupts the CPU when it is ready
 CPU invokes an interrupt service routine (ISR) for the disk, and
returns to normal execution when the interrupt service routine
completes its task.
 state of the Interrupt Flag (IF) present in Processor Status
Register indicate the acceptance of interrupt.
 non-maskable interrupt (NMI) The NMI is used for handling
power failures, and file system updates etc

Interrupt driven I/O flowchart for a disk transfer

3. Direct Memory Access (DMA)
 CPU is responsible for making the actual data transfer even though
interrupt driven I/O frees the CPU until the device requires service
- Data travel first to the CPU, then again over the bus to its
destination
DMA device can transfer data directly to and from
memory and I/O devices by DMA controller(specialized
processor)
 improves the speed of communication over the bus.
 CPU programs the DMA device with the starting address in
main memory, the starting address in the device, and length of the
block to be transferred.
When the DMA transfer is completed, the device informs the
CPU through an interrupt

cycle-stealing DMA
-DMA controllers can operate in a cycle stealing mode in which
they take over the bus for each byte of data to be transferred and then
return control to the CPU
DMA transfer from disk to memory bypasses the CPU

DMA flowchart for a disk transfer

Mass Storage
Mass storage device - tapes, disks
Sl No Register Mass storage devices
1 expensive and not very dense,
Fast storage tapes
slowest methods of storing information ,
inexpensive and are very dense
2. Require continuous power to
retain their stored data,
retain information indefinitely after the
power is removed - indefinite persistence -
non-volatile
1.MAGNETIC DISKS
2. MAGNETIC TAPE
3. MAGNETIC DRUMS

magnetic disk with three platters
1. MAGNETIC DISKS
- is a storage device that uses a magnetization process to write, rewrite
and access data

-one or more platters that are spaced several millimeters apart and are
connected to a Spindle
-Each platter has two surfaces made of aluminum or glass which are
coated with extremely small particles of a magnetic material such as
iron oxide
- Single head is dedicated to each surface(Six heads)
- heads are attached to a common arm(comb) , which moves in and
out to reach different portions of the surfaces.
-platters rotate at a constant speed of 3600 to 10,000 revolutions per
minute (RPM).
heads read or write data
- magnetizing the magnetic material as it passes under the
heads when writing, sensing the magnetic fields when reading
single head is used for reading or writing at any time, so data is
stored in serial fashion

transitions between magnetized areas are sensed when reading a disk,
1’s or 0’s will be detected by encoding the timing information
Manchester encoding
modified frequency modulation (MFM).
NRZ encoding
Manchester encoding
low to high –binary 1
high to low - binary 0
Data encoding

surface contains several hundred concentric tracks(composed of
sectors), store - 512 bytes of data in serially
disk platter with a 1:2 interleave factor
A set of corresponding tracks
on all of the surfaces forms a
cylinder
track 0 on each of surfaces 0, 1, 2, 3, 4, and 5
collectively form cylinder 0.
zone is a group of tracks having the same number of sectors per track
zone-bit recording : Zones near the center of the platter have fewer sectors,
while zones near the outside periphery of the platter have more sectors per
track. This technique for increasing the capacity of a disk drive is known as
zone-bit recording
.

Disk drive capacities and speeds
storage capacity(C)
N- number of bytes per sector
S- number of sectors per track
T- number of tracks per surface
P - number of platter surfaces
data transfer speed depends on three factors:
1. head seek time : time to move the head to the desired track (travel half
the distance across the disk, before arriving at the correct track)
2. rotational latency: time for the desired sector to appear under the
read/write head(1/2 the time of one complete revolution)
3. transfer time : time to transfer the sector from the disk platter once the
sector is positioned under the head.
-one complete revolution divided by the number of sectors per track
 after a complete track is transferred, the head must move to the next
track
burst rate = disk speed in revolutions per second× capacity per track

Floppy disks(diskette)
contains a flexible plastic platter coated with a magnetic material like
iron oxide on both sides
Sl.No Floppy disk Magnetic disk(hard
disk)
Access time slower (flexible disk cannot
spin as quickly as a hard disk)
faster
Rotational speed 300 RPM 3600 to 10,000 RPM
access times 250-300ms 10 times faster than
hard drives
Capacity 1.44MB 19 GB
Disk file systems
2. assign sectors to a file on demand, as needed.
File- collection of sectors that are linked together to form a single
logical entity
1.store a file in consecutive sectors so that the seek time and the
rotational latency are minimized.

disk organization is interleaving
the time required for the intermediate sectors to pass under the
head may be enough time to set up the next transfer
master control block(MCB) is a reserved section
of a disk that keeps track of the makeup of the rest of the disk

2. MAGNETIC TAPE
 has a single read / write head, separate heads for reading and writing
 A spool of plastic (Mylar) tape with a magnetic coating passes the
head,
-which magnetizes the tape when writing,
- senses stored data when reading.
 Inexpensive and slow
 store large amounts of data(backups of disks or scanned images)
not suitable for random access reading and writing
 sequential access require greater time if the head is not positioned near
the target section of tape

 Information is stored on a tape in two-dimensional fashion
 Bits are stored across the width of the tape in frames and along the
length of the tape in records.
 A file is a collection of records.
• A record is the smallest amount of data that can be read from or
written in the tape
 For write , motor starts the tape moving, the record is written,
and the motion of the tape is then stopped.
 The starting and stopping times consume sections of the tape,
which are known as inter-record gaps

 inter-record gaps eventually creep into the records is called jitter
because starting and stopping is not precise
A physical record is subdivided into an integral number of
Logical records
- No inter-record gaps between logical records.

3. MAGNETIC DRUMS
 faster than magnetic disks because
-stationary head per track,
-no head movement component in the access time.
 rotation rate of a drum is much higher than a disk due to narrow cylindrical
shape
magnetic drum unit
-drum is divided into a number of tracks.
less capacity per unit volume than disk unit
-because top ,bottom, interior of the
of the drum are not used for storage
transfer time for a sector on a drum based on
1. rotational delay
2. length of a sector

Three recording types:
1.read-only (e.g.: CD and CD-ROM)
2.recordable (write-once, e.g. CD-R)
3.re-recordable (rewritable, e.g. CD-RW)
4. OPTICAL DISKS
Employ light to read the data on a reflective surface.
eg. Compact Disc (CD) and Digital Versatile Disc (DVD)
 electronic data storage medium that can be written to and read
from using a low-powered laser beam
The data are stored on the disc with a laser or stamping machine

Compact Disc
CD ROMs are “read only” -700 MB capacity
replacing floppy disks due to low cost, good reliability and
high capacity,
-aluminum coated plastic(reflects light
differently for lands or pits)
lands represent binary "1"
pits represent binary "0“
laser beam distinguish the lands and pits based on
the amount of scattering or deflection that occurs
when the beam of light hits the surface of the disc
all the sectors on concentric tracks are lined up like a sliced pie
(disk rotation uses constant angular velocity)
CD is arranged in a spiral format (using constant linear velocity)

Digital Versatile Disc(DVD)
-DVD-Audio, DVD-Video, and DVD-ROM , DVD-RAM data storage.
If single side of the DVD is used, its storage capacity is up to 4.7 GB
storing data on both sides , capacity is 17 GB

INPUT DEVICE
1.KEYBOARDS
-7-bit ASCII characters ,only 128 bit patterns
-additional modifier keys (shift , escape , and contorl )
-addition of special keys-tab , delete ,and carriage return .
Keyboard layout for ECMA-23
Standard
Dvorak keyboard layout
Commonly used

2.BIT PADS ( DIGITIZING TABLET)
-Used for entering data from maps , photographs, charts , or
graphs

3.MICE AND TRACKBALLS
• Mouse
– Consists of a rubber ball on the bottom
– One or more buttons on the top
one for the key-down position
one for the key-up position.
-As the mouse is moved ,the ball rotates Proportional to the distance
moved.
-Potentiometers within the mouse sense the direction of motion and
the distance traveled
-Optical mouse replaces the ball with a light emitting diode(LED),
-a special reflective mousepad that consists of alternating reflective
and absorptive -horizontal and vertical stripes.
mouse

Trackball
-is a mouse turned upside down.
-The trackball unit is held stationary
while the ball is manually rotated.

4.LIGHTPENS AND TOUCH SCREENS
-Used for selecting objects
Lightpen :does not produces light ,
-but senses light form a video screen.
-electron beam, excites a Phosphor coating on the back of the
display surface.
- The phosphor glows and then dims as it returns to its natural
state.
-Each individual spot is refreshed t a rate of 30-60Hz
- so that the user perceives a continuous image.
lightpen

When a dim spot is refreshed, it becomes brighter
-If the lightpen is located at a refreshed phosphor, position of the
electron beam locates the position of the pen .
-Since the lightpen detects intensity ,it can distinguish among
Illuminated areas.
-Dark areas of the screen all appear the same since there is no
change in intensity over time
Touch screen
two forms
1. photonic
2. electrical.
-A matrix of beams covers the screen in the
horizontal and vertical dimensions.
-If the beams are interrupted (by
a finger), then the position is determined by the interrupted beams.
Touch screen

5. JOYSTICKS
-commonly used in video games, and for indicating position in
graphics systems.
-Potentiometers within the base of the joystick translate X-Y
position information into voltages,
-then encoded in binary for input to a digital system
joystick

OUTPUT DEVICES
1.LASER PRINTERS
-Consists of a charged drum in which a laser discharges in selected
areas according to a bit mapped representation of a page to be
printed.
-As the drum continuous to advances for each scan line ,the charged
areas pick up electrostatically sensitive toner powder.
laser printer

-The drum continues to advance, and the toner is transferred to the
paper ,which is heated to fix the toner on the page
-The drum is cleaned of any residual toner and the process repeats for
the next page .
-Toner is a form of plastic, it is not absorbed into the page but is
melted onto the surface
ADOBE POSTSCRIPT language:
languages for communicating information from computer
to printer

2. VIDEO DISPLAYS(monitor)
consists of
1. luminescent display device -cathode ray tube (CRT) or a liquid
crystal panel
2. controlling circuitry
CRT
- vertical and horizontal deflection plates focus an electron beam that
sweeps the display screen in raster fashion
CRT with a single electron gun.

-three different phosphor types (red, green, and blue) are interleaved in
a regular pattern
- three guns produce three beams that are simultaneously deflected on
the screen
controller for a 640×480 color monitor

1. RS-232
2.universAL serial bus (USB)
3.firewire
SERIAL BUS ARCHITECTURES

1. RS-232(Recommended standard 232)
• Standard for serial communication of data .
• The RS-232 standard can been used in
computer serial ports
• It formally connecting between a DTE(data
terminal equipment)such as a computer
terminal ,and a DCE(terminating equipment
or data communication equipment),such as
a modem
• The standard defines the electrical
characteristic and timing of the signal ,and
the physical size and pinout of connectors .
• The current version of the standard is TIA-232-F Interface between
data terminal equipment and data circuit –terminating equipment
employing serial binary data interchange.

• RS-232 when compared to later interfaces such as RS-422,RS-485
and Ethernet, has lower transmission speed, short maximum cable
length, large voltage swing, large standard connectors ,no multipoint
capability and limited multidrop capability.
• used for 9-pin and 25-pin connectors
– for slow-bit-rate devices such as keyboards, and non-graphics
terminals
9-pin and 25-pin connectors

2. Universal Serial Bus (USB)
- is an industry standard that establishes specifications for
connectors, cables and protocols for communication,
connection and power supply between personal computers and
their peripheral devices.
-standards for interconnecting peripheral devices
USB specifications:
1. USB 1.x (low speed-12 Mbits/sec)
2. USB 2.0 (high speed-480 Mbits/sec)
3. USB 3.x (super speed-12 5 Gbits/sec)
- USB 2.0 supports data transfer rates up to 480 Mbps,
- 127 devices connected to a single host controller through
special hub devices in a tree-like manner

3.FIREWIRE(EEE1394)
 FireWire is a apple computers version of a standard, high performance
serial bus , for connecting device to personal computers.
-provides a single plug-and-socket connection on which up to 63
device can be attached
- data transfer speed upto 800Mbps(megabits per second)
Advantage
-isochronous data transfer(continuous data transfer is supported
at a predetermined rate)
-Firewire attractive for digital video and digital audio
USB hub USB cable Firewire cable.

Computer Architecture and Organization--Memory and I/O

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