SlideShare a Scribd company logo
Decoder
The combinational circuit that change the binary information into 2N
output lines is
known as Decoders. The binary information is passed in the form of N input lines.
The output lines define the 2N
-bit code for the binary information. In simple words,
the Decoder performs the reverse operation of the Encoder. At a time, only one
input line is activated for simplicity. The produced 2N
-bit output code is equivalent to
the binary information.
There are various types of decoders which are as follows:
2 to 4 line decoder:
In the 2 to 4 line decoder, there is a total of three inputs, i.e., A0, and A1 and E and
four outputs, i.e., Y0, Y1, Y2, and Y3. For each combination of inputs, when the
enable 'E' is set to 1, one of these four outputs will be 1. The block diagram and the
truth table of the 2 to 4 line decoder are given below.
Block Diagram:
Truth Table:
The logical expression of the term Y0, Y0, Y2, and Y3 is as follows:
Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'
Logical circuit of the above expressions is given below:
3 to 8 line decoder:
The 3 to 8 line decoder is also known as Binary to Octal Decoder. In a 3 to 8 line
decoder, there is a total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and
three outputs, i.e., A0, A1, and A2. This circuit has an enable input 'E'. Just like 2 to
4 line decoder, when enable 'E' is set to 1, one of these four outputs will be 1. The
block diagram and the truth table of the 3 to 8 line encoder are given below.
Block Diagram:
Truth Table:
The logical expression of the term Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 is as follows:
Y0=A0'.A1'.A2'
Y1=A0.A1'.A2'
Y2=A0'.A1.A2'
Y3=A0.A1.A2'
Y4=A0'.A1'.A2
Y5=A0.A1'.A2
Y6=A0'.A1.A2
Y7=A0.A1.A2
Logical circuit of the above expressions is given below
4 to 16 line Decoder
In the 4 to 16 line decoder, there is a total of 16 outputs, i.e., Y0, Y1, Y2,……, Y16 and
four inputs, i.e., A0, A1, A2, and A3. The 3 to 16 line decoder can be constructed
using either 2 to 4 decoder or 3 to 8 decoder. There is the following formula used to
find the required number of lower-order decoders.
Required number of lower order decoders=m2/m1
m1 = 8
m2 = 16
Required number of 3 to 8 decoders= =2
Block Diagram:
Truth Table:
The logical expression of the term A0, A1, A2,…, A15 are as follows:
Y0=A0'.A1'.A2'.A3'
Y1=A0'.A1'.A2'.A3
Y2=A0'.A1'.A2.A3'
Y3=A0'.A1'.A2.A3
Y4=A0'.A1.A2'.A3'
Y5=A0'.A1.A2'.A3
Y6=A0'.A1.A2.A3'
Y7=A0'.A1.A2.A3
Y8=A0.A1'.A2'.A3'
Y9=A0.A1'.A2'.A3
Y10=A0.A1'.A2.A3'
Y11=A0.A1'.A2.A3
Y12=A0.A1.A2'.A3'
Y13=A0.A1.A2'.A3
Y14=A0.A1.A2.A3'
Y15=A0.A1.A2'.A3
Logical circuit of the above expressions is given below:

More Related Content

DOCX
Computer Architecture_Encoders NOTES.docx
PPTX
Decoders
PPTX
Encoder.pptx
PPTX
DECODER AND ENCODER (1).pptx
PPTX
B sc3 unit 4 combi..lckt
PDF
Lecture 8 Decoders & Encoders (combinational circuits)
PDF
Combinational Circuits PPT.pdf
PPTX
Switching theory unit 2
Computer Architecture_Encoders NOTES.docx
Decoders
Encoder.pptx
DECODER AND ENCODER (1).pptx
B sc3 unit 4 combi..lckt
Lecture 8 Decoders & Encoders (combinational circuits)
Combinational Circuits PPT.pdf
Switching theory unit 2

Similar to Computer Architecture_Decoder NOTES.docx (20)

PDF
Sajib 201-15-3773-encoder
PDF
Multiplexer and demultiplexer for digital logic circuitpdf
PPTX
What is a decoder and 2 to 4 DECODER
PPTX
Multiplexer.pptx
PPTX
Combinational Circuits.pptx
PPTX
Octal to binary encoder
PPT
Magnitude Comparator
PDF
Encoder_decoder_si.pdf
PPTX
Octal encoding
PPTX
I semester Unit 4 combinational circuits.pptx
PPTX
3-UNIT3_BOOLEAN ALGEBRA.pptx
PDF
13- Combinational Logic functionsw A.pdf
PPTX
Decoders-Digital Electronics
PPTX
Presentation1DigitalTechniquesMSBTEImportantnotes
PPTX
chapter3.pptx electrical engineering for university
PPTX
decoders121-170714184489769876987698749.pptx
PDF
Chapter-04.pdf
PDF
Combinational Circuits - II (Encoders, Decoders, Multiplexers & PIDs).pdf
PPTX
A Nutshell On Convolutional Codes (Representations)
PPTX
unit 3.pptx
Sajib 201-15-3773-encoder
Multiplexer and demultiplexer for digital logic circuitpdf
What is a decoder and 2 to 4 DECODER
Multiplexer.pptx
Combinational Circuits.pptx
Octal to binary encoder
Magnitude Comparator
Encoder_decoder_si.pdf
Octal encoding
I semester Unit 4 combinational circuits.pptx
3-UNIT3_BOOLEAN ALGEBRA.pptx
13- Combinational Logic functionsw A.pdf
Decoders-Digital Electronics
Presentation1DigitalTechniquesMSBTEImportantnotes
chapter3.pptx electrical engineering for university
decoders121-170714184489769876987698749.pptx
Chapter-04.pdf
Combinational Circuits - II (Encoders, Decoders, Multiplexers & PIDs).pdf
A Nutshell On Convolutional Codes (Representations)
unit 3.pptx
Ad

Recently uploaded (20)

PDF
AI-driven educational solutions for real-life interventions in the Philippine...
PPTX
B.Sc. DS Unit 2 Software Engineering.pptx
DOC
Soft-furnishing-By-Architect-A.F.M.Mohiuddin-Akhand.doc
PPTX
A powerpoint presentation on the Revised K-10 Science Shaping Paper
PDF
FORM 1 BIOLOGY MIND MAPS and their schemes
PDF
FOISHS ANNUAL IMPLEMENTATION PLAN 2025.pdf
PDF
Weekly quiz Compilation Jan -July 25.pdf
PDF
BP 704 T. NOVEL DRUG DELIVERY SYSTEMS (UNIT 1)
PDF
Uderstanding digital marketing and marketing stratergie for engaging the digi...
PDF
International_Financial_Reporting_Standa.pdf
PPTX
20th Century Theater, Methods, History.pptx
PDF
Hazard Identification & Risk Assessment .pdf
PDF
My India Quiz Book_20210205121199924.pdf
PPTX
History, Philosophy and sociology of education (1).pptx
PDF
CISA (Certified Information Systems Auditor) Domain-Wise Summary.pdf
PPTX
TNA_Presentation-1-Final(SAVE)) (1).pptx
PDF
HVAC Specification 2024 according to central public works department
PPTX
Computer Architecture Input Output Memory.pptx
PPTX
Onco Emergencies - Spinal cord compression Superior vena cava syndrome Febr...
PPTX
202450812 BayCHI UCSC-SV 20250812 v17.pptx
AI-driven educational solutions for real-life interventions in the Philippine...
B.Sc. DS Unit 2 Software Engineering.pptx
Soft-furnishing-By-Architect-A.F.M.Mohiuddin-Akhand.doc
A powerpoint presentation on the Revised K-10 Science Shaping Paper
FORM 1 BIOLOGY MIND MAPS and their schemes
FOISHS ANNUAL IMPLEMENTATION PLAN 2025.pdf
Weekly quiz Compilation Jan -July 25.pdf
BP 704 T. NOVEL DRUG DELIVERY SYSTEMS (UNIT 1)
Uderstanding digital marketing and marketing stratergie for engaging the digi...
International_Financial_Reporting_Standa.pdf
20th Century Theater, Methods, History.pptx
Hazard Identification & Risk Assessment .pdf
My India Quiz Book_20210205121199924.pdf
History, Philosophy and sociology of education (1).pptx
CISA (Certified Information Systems Auditor) Domain-Wise Summary.pdf
TNA_Presentation-1-Final(SAVE)) (1).pptx
HVAC Specification 2024 according to central public works department
Computer Architecture Input Output Memory.pptx
Onco Emergencies - Spinal cord compression Superior vena cava syndrome Febr...
202450812 BayCHI UCSC-SV 20250812 v17.pptx
Ad

Computer Architecture_Decoder NOTES.docx

  • 1. Decoder The combinational circuit that change the binary information into 2N output lines is known as Decoders. The binary information is passed in the form of N input lines. The output lines define the 2N -bit code for the binary information. In simple words, the Decoder performs the reverse operation of the Encoder. At a time, only one input line is activated for simplicity. The produced 2N -bit output code is equivalent to the binary information. There are various types of decoders which are as follows: 2 to 4 line decoder: In the 2 to 4 line decoder, there is a total of three inputs, i.e., A0, and A1 and E and four outputs, i.e., Y0, Y1, Y2, and Y3. For each combination of inputs, when the enable 'E' is set to 1, one of these four outputs will be 1. The block diagram and the truth table of the 2 to 4 line decoder are given below. Block Diagram:
  • 2. Truth Table: The logical expression of the term Y0, Y0, Y2, and Y3 is as follows: Y3=E.A1.A0 Y2=E.A1.A0' Y1=E.A1'.A0 Y0=E.A1'.A0' Logical circuit of the above expressions is given below: 3 to 8 line decoder: The 3 to 8 line decoder is also known as Binary to Octal Decoder. In a 3 to 8 line decoder, there is a total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and
  • 3. three outputs, i.e., A0, A1, and A2. This circuit has an enable input 'E'. Just like 2 to 4 line decoder, when enable 'E' is set to 1, one of these four outputs will be 1. The block diagram and the truth table of the 3 to 8 line encoder are given below. Block Diagram: Truth Table: The logical expression of the term Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 is as follows: Y0=A0'.A1'.A2' Y1=A0.A1'.A2'
  • 4. Y2=A0'.A1.A2' Y3=A0.A1.A2' Y4=A0'.A1'.A2 Y5=A0.A1'.A2 Y6=A0'.A1.A2 Y7=A0.A1.A2 Logical circuit of the above expressions is given below 4 to 16 line Decoder In the 4 to 16 line decoder, there is a total of 16 outputs, i.e., Y0, Y1, Y2,……, Y16 and four inputs, i.e., A0, A1, A2, and A3. The 3 to 16 line decoder can be constructed using either 2 to 4 decoder or 3 to 8 decoder. There is the following formula used to find the required number of lower-order decoders. Required number of lower order decoders=m2/m1 m1 = 8 m2 = 16 Required number of 3 to 8 decoders= =2
  • 6. Truth Table: The logical expression of the term A0, A1, A2,…, A15 are as follows: Y0=A0'.A1'.A2'.A3' Y1=A0'.A1'.A2'.A3 Y2=A0'.A1'.A2.A3' Y3=A0'.A1'.A2.A3 Y4=A0'.A1.A2'.A3' Y5=A0'.A1.A2'.A3 Y6=A0'.A1.A2.A3' Y7=A0'.A1.A2.A3 Y8=A0.A1'.A2'.A3' Y9=A0.A1'.A2'.A3 Y10=A0.A1'.A2.A3' Y11=A0.A1'.A2.A3 Y12=A0.A1.A2'.A3' Y13=A0.A1.A2'.A3 Y14=A0.A1.A2.A3' Y15=A0.A1.A2'.A3
  • 7. Logical circuit of the above expressions is given below: