Computer basic and cpu

 Computer Organization: is concerned with
the way the hardware components operate
and the way they are connected together to
form the computer system
 Computer Architecture: is concerned with
the structure and behavior of the computer
as seen by the user. It includes the
information format, the instruction set and
techniques for memory addressing

 ENIAC
 (Electronic Numerical Integrated And Computer)
 Designed and constructed under supervision of John
Mauchly and John Presper Eckert
 At University of Pennsylvania
 It was the world’s first general-purpose electronic
digital computer.

 ENIAC built in World War II was the first general purpose computer
 Used for computing artillery firing tables
 80 feet long by 8.5 feet high and several feet wide
 Each of the twenty 10 digit registers was 2 feet long
 Used 18,000 vacuum tubes
 Performed 1900 additions per second
–Since then:
Moore’s Law:
transistor capacity doubles
every 18-24 months

 The project was a response to U.S. war time
needs during World War II.
 Army’s Ballistics Research Laboratory (BRL), an
agency responsible for developing range and
trajectory tables for new weapons.
 BRL was having difficulty supplying these tables
accurately and within a reasonable time frame.
 Without these firing tables, the new weapons
and artillery were useless to gunners.

 The BRL employed 200 people, who, using
desktop calculators, solved the necessary
ballistics equations.
 Preparation of the tables for a single weapon
would take one person many hours, even days.
 Mauchly, a professor of electrical engineering at
the university of Pennsylvania, and Eckert, one
of his graduate student, proposed to build a
general purpose computer using vacuum tubes
for BRL’s application.

 In 1943, the Army accepted this proposal, and
work begun on the ENIAC.
 The resulting machine was enormous, Weighing
30 tons, occupying 1500 square feet of floor
space, and containing 18000 vacuum tubes.
 When operating, it consumed 140 kilowatts
power.
 It was also faster than any electromechanical
computer being capable of 5000 additions per
second.

 ENIAC was decimal rather than a binary machine.
 Numbers were represented in decimal form and
arithmetic was performed in the decimal system.
 Its memory consists of 20 “accumulators”, each capable
of holding a 10-digit decimal number.
 A ring of 10 vacuum tubes represented one digit.
 At any time only one vacuum tube was in ON state,
representing one the 10 digits.

 Drawback: It had to be programmed manually by
setting switches and plugging and unplugging
cables.
 It was completed in 1946, to late to be used in
war effort.
 Its first task was to perform a series of complex
calculations that were used to help determined
the feasibility of the hydrogen bomb.
 The ENIAC continued to operate under BRL
management until 1955, when it was
disassembled.

 The task of entering and altering programs for the
ENIAC was extremely tedious.
 The programming process could be facilitated if the
program could be represented in a form suitable for
storing in memory alongside the data.
 A computer could get its instructions by reading then
from memory, and a program could be set or altered
by setting the values of the portion of memory.
 This idea is known as the stored-program concept.

 The stored program concept is usually attributed
to the ENIAC designers, most notably the
mathematician John von Neumann, who was the
consultant on the ENIAC project.
 Alan Turing developed the idea at about the
same time.
 The first publication of the idea was in 1945
proposed by von Neumann for a new computer,
the EDVAC (Electronic Discrete Variable
Computer).

 In 1946, von Neumann and his colleagues begun
the design of a new stored program computer,
referred to as the IAS computer.
 At the Princeton Institute for Advanced Studies.
 The IAS computer, although not completed until
1952.
 But it is the prototype of all subsequent general-purpose
computers.

 General structure of IAS computer:
 A main memory, which stores both data and
instructions.
 An arithmetic and logic unit (ALU) capable of operating
on binary data.
 A control unit, which interprets the instruction in
memory and causes them to be executed.
 Input and Output (I/O) equipment operated by the
control unit.

Main
Memory
(M)
I/O
Equipment
(I,O)
Central Processing unit (CPU)
Arithmetic
Logic
Unit (CA)
Program
control
Unit (PC)
Structure of IAS Computer

 With rare exceptions, all of today’s computers
have this same general structure and function
and are referred to as von Neumann Machine.
 The memory of the IAS consists of 1000 storage
locations, called words, of 40 binary digits (bits)
each.
 Both data and instruction are stored there.
 The numbers must be represented in binary
form, and each instructions are also has to be a
binary code.

0 1 39
Sign bit
Number Word
Left Instruction Right Instruction
0 8 20 28 39
Opcode Address Opcode Address
Instruction word

 Each number is represented by a sign bit and 39-
bit value.
 A word may also contains two 20-bit instructions.
 Each instruction consisting of a 8-bit operation
code (opcode) specifying the operation to be
performed.
 A 12-bit address designating one of the words in
memory.

 The control unit operates the IAS by fetching
instruction from memory and executing them
one at a time.
 The detail structure of a diagram is in Figure on
next slide reveals that
 Both the control unit and ALU contains storage
locations, called register.

Input-
Output
equipment
Main
Memory
(M)
AC MQ
Arithmetic-logic
circuits
MBR
IBR PC
IR MAR
Control
circuits Addresses
Instructions
and data
Program control unit (ALU)

 Memory buffer register (MBR): Contains a word to be
stored in the memory, or is used to receive a word from
the memory.
 Memory address register (MAR): Specifies the address in
memory of the word to be written from or read into the
MBR.
 Instruction Register (IR): Contains the 8-bit opcode
instruction being executed.
 Instruction buffer register (IBR): Used to hold
temporarily the right hand instruction from the word in
memory.

 Program Counter (PC): Contains the address of the next
instruction-pair to be fetched from memory.
 Accumulator (AC) and multiplier quotient (MQ):
Employed to hold temporarily operands and result of
ALU operations. For example, the result of multiplying
two 40-bit numbers is an 80-bit numbers, the most
significant bits are stored in the AC and the least
significant in the MQ.

Start
Is next
Instruction
In IBR
MAR  PC
MBR  M(MAR)
Yes No
IRMBR(20:27)
MARMBR(28:39)
Left
No IBRMBR(20:39)
Instruction
Required?
IRIBR(0:7)
MARIBR(8:19)
PC PC + 1
Decode the instruction in IR
IRMBR(0:7)
MAR  MBR(8:19)
Yes
No memory
access
required

Start
Fetch the Instruction
Decode Instruction
Execute Instruction
Exit

 The IAS operates by repetitively performing an
instruction cycle.
 Each instruction cycle consists of two sub-cycles.
 During fetch cycle, the op code of the next instruction
is loaded into the IR and the address portion is loaded
into the MAR.
 This instruction may be taken from the IBR, or it can be
obtained from memory by holding a word into the MBR,
and then down to the IBR, IR, and MAR.

 Once the opcode is in the IR, the execute cycle is
performed.
 The control circuitry interprets the opcode and executes
the instruction by sending out appropriate control
signals.
 it causes data to moved or an operation to performed by
ALU.

 Data transfer: Move data between memory and ALU registers or
between two ALU register.
 Unconditional branch: the control unit memory executes
instructions in sequence from memory. This sequence can be
changed by a branch instruction. This facilitates repetitive
operations.
 Conditional branch: the branch can be made dependent on a
condition, thus allowing decision points.
 Arithmetic: Operation performed by ALU.
 Address modify: Permits addresses to be compute in the ALU and
then inserted into instructions stored in memory. This allows a
program considerable addressing flexibility.

• Register Transfer Language
• Register Transfer
• Bus and Memory Transfers
• Arithmetic Microoperations
• Logic Microoperations
• Shift Microoperations
• Arithmetic Logic Shift Unit

 Combinational and sequential circuits
can be used to create simple digital systems.
 These are the low-level building blocks of a digital computer.
 Simple digital systems are frequently characterized in terms of
 the registers they contain, and
 the operations that they perform.
 Typically,
 What operations are performed on the data in the registers
 What information is passed between registers

 The operations on the data in registers are called
microoperations.
 The functions built into registers are examples of
microoperations
 Shift
 Load
 Clear
 Increment
 …
Register Transfer Language

An elementary operation performed (during
one clock pulse), on the information stored
in one or more registers
R ¬ f(R, R)
f: shift, load, clear, increment, add, subtract, complement,
and, or, xor, …
ALU
(f)
Registers
(R)
1 clock cycle

• Definition of the (internal) organization of a computer
- Set of registers and their functions
- Microoperations set
Set of allowable microoperations provided
by the organization of the computer
- Control signals that initiate the sequence of
microoperations (to perform the functions)

 Viewing a computer, or any digital system, in this way is
called the register transfer level
 This is because we’re focusing on
 The system’s registers
 The data transformations in them, and
 The data transfers between them.

 Rather than specifying a digital system in words, a specific
notation is used, register transfer language
 For any function of the computer, the register transfer language
can be used to describe the (sequence of) microoperations
 Register transfer language
 A symbolic language
 A convenient tool for describing the internal organization of digital computers
 Can also be used to facilitate the design process of digital systems.

 Registers are designated by capital letters, sometimes followed by
numbers (e.g., A, R13, IR)
 Often the names indicate function:
 MAR- memory address register
 PC - program counter
 IR - instruction register
 Registers and their contents can be viewed and represented in
various ways
 A register can be viewed as a single entity:
MAR
 Registers may also be represented showing the bits of data they contain

• Designation of a register
R1
Register
15 0
Numbering of bits
Showing individual bits
15 8 7 0
Subfields P
C(H) PC(L)
- a register
- portion of a register
- a bit of a register
• Common ways of drawing the block diagram of a register
7 6 5 4 3 2 1 0
R2

Register Transfer
 Copying the contents of one register to another is a register
transfer
 A register transfer is indicated as
R2 ¬ R1
 In this case the contents of register R1 are copied (loaded) into register
R2
 A simultaneous transfer of all bits from the source R1 to the
destination register R2, during one clock pulse
 Note that this is a non-destructive; i.e. the contents of R1 are not
altered by copying (loading) them to R2

 A register transfer such as
R3 ¬ R5
Implies that the digital system has
Register Transfer
 the data lines from the source register (R5) to the destination register
(R3)
 Parallel load in the destination register (R3)
 Control lines to perform the action

Register Transfer
 Often actions need to only occur if a certain condition is true
 This is similar to an “if” statement in a programming language
 In digital systems, this is often done via a control signal, called a
control function
 If the signal is 1, the action takes place
 This is represented as:
P: R2 ¬ R1
Which means “if P = 1, then load the contents of register R1 into register
R2”, i.e., if (P = 1) then (R2 ¬ R1)

Implementation of controlled transfer
P: R2 ¬ R1
Block diagram
Timing diagram
Register Transfer
Clock
Transfer occurs here
R2
R1
Control
Circuit
P Load
n
Clock
Load
t t+1
• The same clock controls the circuits that generate the control function
and the destination register
• Registers are assumed to use positive-edge-triggered flip-flops

 If two or more operations are to occur simultaneously,
they are separated with commas
P: R3 ¬ R5, MAR ¬ IR
 Here, if the control function P = 1, load the contents
of R5 into R3, and at the same time (clock), load the
contents of register IR into register MAR
Register Transfer

Register Transfer
Symbols Description Examples
Capital letters Denotes a register MAR, R2
& numerals
Parentheses () Denotes a part of a register R2(0-7), R2(L)
Arrow ¬ Denotes transfer of information R2 ¬ R1
Colon : Denotes termination of control function P:
Comma , Separates two micro-operations A ¬ B, B ¬ A

Register Transfer
 In a digital system with many registers, it is impractical to
have data and control lines to directly allow each register to
be loaded with the contents of every possible other registers
 To completely connect n registers  n(n-1) lines
 O(n2) cost
 This is not a realistic approach to use in a large digital system
 Instead, take a different approach
 Have one centralized set of circuits for data transfer – the bus
 Have control circuits to select which register is the source,
and which is the destination

Bus is a path(of a group of wires) over which information is transferred, from
any of several sources to any of several destinations.
From a register to bus: BUS ¬ R
Register A Register B Register C Register D
Bus lines
Bus and Memory Transfers

Bus lines
Reg. R0 Reg. R1 Reg. R2 Reg. R3
Three-State Bus Buffers
Bus line with three-state buffers
2 x 4
Decoder
Load
D0 D1 D2 D z 3
w
Select E (enable)
Output Y=A if C=1
High-impedence if C=0
Normal input A
Control input C
Select
Enable
0
12
3
S0
S1
A0
B0
C0
D0
Bus line for bit 0

 Depending on whether the bus is to be mentioned explicitly
or not, register transfer can be indicated as either
or
R2 ¬ R1
BUS ¬ R1, R2 ¬ BUS
 In the former case the bus is implicit, but in the latter, it is
explicitly indicated

 Memory (RAM) can be thought as a sequential circuits
containing some number of registers
 These registers hold the words of memory
 Each of the r registers is indicated by an address
 These addresses range from 0 to r-1
 Each register (word) can hold n bits of data
 Assume the RAM contains r = 2k words. It needs the following
 n data input lines
 n data output lines
 k address lines
 A Read control line
 A Write control line
data input lines
n
n
data output lines
k
address lines
Read
Write
RAM
unit

 Collectively, the memory is viewed at the register level as a
device, M.
 Since it contains multiple locations, we must specify which
address in memory we will be using
 This is done by indexing memory references
 Memory is usually accessed in computer systems by putting
the desired address in a special register, the Memory Address
Register (MAR, or AR)
 When memory is accessed, the contents of the MAR get sent
to the memory unit’s address lines
M
AR Memory
unit
Read
Write
Data out Data in

 To read a value from a location in memory and load it into a
register, the register transfer language notation looks like
this:
R1 ¬ M[MAR]
 This causes the following to occur
 The contents of the MAR get sent to the memory address lines
 A Read (= 1) gets sent to the memory unit
 The contents of the specified address are put on the memory’s output data
lines
 These get sent over the bus to be loaded into register R1

 To write a value from a register to a location in memory looks
like this in register transfer language:
M[MAR] ¬ R1
 This causes the following to occur
 The contents of the MAR get sent to the memory address lines
 A Write (= 1) gets sent to the memory unit
 The values in register R1 get sent over the bus to the data input lines of
the memory
 The values get loaded into the specified address in the memory

A ¬ B Transfer content of reg. B into reg. A
AR ¬ DR(AD) Transfer content of AD portion of reg. DR into reg. AR
A ¬ constant Transfer a binary constant into reg. A
ABUS ¬ R1, Transfer content of R1 into bus A and, at the same time,
R2 ¬ ABUS transfer content of bus A into R2
AR Address register
DR Data register
M[R] Memory word specified by reg. R
M Equivalent to M[AR]
DR ¬ M Memory read operation: transfers content of
memory word specified by AR into DR
M ¬ DR Memory write operation: transfers content of
DR into memory word specified by AR

• Computer system microoperations are of four types:
- Register transfer microoperations
- Arithmetic microoperations
- Logic microoperations
- Shift microoperations
Arithmetic Microoperations

 The basic arithmetic microoperations are
 Addition
 Subtraction
 Increment
 Decrement
 The additional arithmetic microoperations are
 Add with carry
 Subtract with borrow
 Transfer/Load
 etc. …
Summary of Typical Arithmetic Micro-Operations
R3 ¬ R1 + R2 Contents of R1 plus R2 transferred to R3
R3 ¬ R1 - R2 Contents of R1 minus R2 transferred to R3
R2 ¬ R2’ Complement the contents of R2
R2 ¬ R2’+ 1 2's complement the contents of R2 (negate)
R3 ¬ R1 + R2’+ 1 subtraction
R1 ¬ R1 + 1 Increment
R1 ¬ R1 - 1 Decrement

B0 A0
FA C2
FA C1
FA FA
C0
S0
B1 A1
S1
B2 A2
S2
B3 A3
S3
C3
C4
Binary Adder-Subtractor
B0 A0
FA C1 FA
C0
S0
B1 A1
S1
B2 A2
FA C2
S2
B3 A3
FA C3
C4 S3
M
Binary Incrementer
A0 1
x y
HA
C S
S0
A1
x y
HA
C S
S1
A2
x y
HA
C S
S2
A3
x y
HA
C S
C4 S3
Binary Adder

S1
S0
3
M4Ux1X
012
X0
Y0
C0
FA
D0 C1
S1
S0
M4Ux1X
012 3
X1
Y1
C1
D1 FA
C2
S1
S0
3
M4Ux1X
012
X2
Y2
C2
D2 FA
C3
S1
S0
3
M4Ux1X
012
X3
Y3
C3
D3 FA
C4
Cout
A0
B0
A1
B1
A2
B2
A3
B3
0 1
SS01 Cin
S1 S0 Cin Y Output Microoperation
0 0 0 B D = A + B Add
0 0 1 B D = A + B + 1 Add with carry
0 1 0 B’ D = A + B’ Subtract with borrow
0 1 1 B’ D = A + B’+ 1 Subtract
1 0 0 0 D = A Transfer A
1 0 1 0 D = A + 1 Increment A
1 1 0 1 D = A - 1 Decrement A
1 1 1 1 D = A Transfer A

 Specify binary operations on the strings of bits in registers
 Logic microoperations are bit-wise operations, i.e., they work on the
individual bits of data
 useful for bit manipulations on binary data
 useful for making logical decisions based on the bit value
 There are, in principle, 16 different logic functions that can be
defined over two binary input variables
A B F0 F1 F2 … F13 F14 F15
 However, most systems only implement four of these
 AND (Ù), OR (Ú), XOR (Å), Complement/NOT
 The others can be created from combination of these
Logic Microoperations
0 0 0 0 0 … 1 1 1
0 1 0 0 0 … 1 1 1
1 0 0 0 1 … 0 1 1
1 1 0 1 0 … 1 0 1

• List of Logic Microoperations
- 16 different logic operations with 2 binary vars.
- n binary vars → 2 2 n functions
• Truth tables for 16 functions of 2 variables and the
corresponding 16 logic micro-operations
Micro-
Operations Name x 0 0 1 1
y 0 1 0 1
Boolean
Function
0 0 0 0 F0 = 0 F ¬ 0 Clear
0 0 0 1 F1 = xy F ¬ A Ù B AND
0 0 1 0 F2 = xy' F ¬ A Ù B’
0 0 1 1 F3 = x F ¬ A Transfer A
0 1 0 0 F4 = x'y F ¬ A’Ù B
0 1 0 1 F5 = y F ¬ B Transfer B
0 1 1 0 F6 = x Å y F ¬ A Å B Exclusive-OR
0 1 1 1 F7 = x + y F ¬ A Ú B OR
1 0 0 0 F8 = (x + y)' F ¬ (A Ú B)’ NOR
1 0 0 1 F9 = (x Å y)' F ¬ (A Å B)’ Exclusive-NOR
1 0 1 0 F10 = y' F ¬ B’ Complement B
1 0 1 1 F11 = x + y' F ¬ A Ú B
1 1 0 0 F12 = x' F ¬ A’ Complement A
1 1 0 1 F13 = x' + y F ¬ A’Ú B
1 1 1 0 F14 = (xy)' F ¬ (A Ù B)’ NAND
1 1 1 1 F15 = 1 F ¬ all 1's Set to all 1's

i 0
Function table
A
S1 S0 Output m-operation
0 0 F = A Ù B AND
0 1 F = A Ú B OR
1 0 F = A Å B XOR
1 1 F = A’ Complement
B
S
S
F
1
0
i
i
1
2
3
4 X 1
MUX
Select

 Logic microoperations can be used to manipulate individual bits
or a portions of a word in a register
 Consider the data in a register A. In another register, B, is bit
data that will be used to modify the contents of A
 Selective-set A ¬ A + B
 Selective-complement A ¬ A Å B
 Selective-clear A ¬ A • B’
 Mask (Delete) A ¬ A • B
 Clear A ¬ A Å B
 Insert A ¬ (A • B) + C
 Compare A ¬ A Å B
 . . .

 In a selective set operation, the bit pattern in B is used to set
certain bits in A
1 1 0 0 At
1 0 1 0 B
1 1 1 0 At+1 (A ¬ A + B)
 If a bit in B is set to 1, that same position in A gets set to 1,
otherwise that bit in A keeps its previous value

 In a selective complement operation, the bit pattern in B is used
to complement certain bits in A
1 1 0 0 At
1 0 1 0 B
0 1 1 0 At+1 (A ¬ A Å B)
 If a bit in B is set to 1, that same position in A gets
complemented from its original value, otherwise it is unchanged

 In a selective clear operation, the bit pattern in B is used to
clear certain bits in A
1 1 0 0 At
1 0 1 0 B
0 1 0 0 At+1 (A ¬ A × B’)
otherwise it is unchanged

 In a mask operation, the bit pattern in B is used to clear certain
bits in A
1 1 0 0 At
1 0 1 0 B
1 0 0 0 At+1 (A ¬ A × B)
otherwise it is unchanged

 In a clear operation, if the bits in the same position in A and B
are the same, they are cleared in A, otherwise they are set in A
1 1 0 0 At
1 0 1 0 B
0 1 1 0 At+1 (A ¬ A Å B)

 An insert operation is used to introduce a specific bit pattern
into A register, leaving the other bit positions unchanged
 This is done as
 A mask operation to clear the desired bit positions, followed by
 An OR operation to introduce the new bits into the desired positions
 Example
 Suppose you wanted to introduce 1010 into the low order four bits
of A: 1101 1000 1011 0001 A (Original)
1101 1000 1011 1010 A (Desired)
 1101 1000 1011 0001 A (Original)
1111 1111 1111 0000 Mask
1101 1000 1011 0000 A (Intermediate)
0000 0000 0000 1010 Added bits
1101 1000 1011 1010 A (Desired)

 There are three types of shifts
 Logical shift
 Circular shift
 Arithmetic shift
Shift Microoperations
 What differentiates them is the information that goes into
the serial input
• A right shift operation
Serial
input
• A left shift operation
Serial
input

 In a logical shift the serial input to the shift is a 0.
 A right logical shift operation:
 A left logical shift operation:
 In a Register Transfer Language, the following notation is used
 shl for a logical shift left
 shr for a logical shift right
 Examples:
 R2 ¬ shr R2
 R3 ¬ shl R3
0
0

 In a circular shift the serial input is the bit that is shifted out of
the other end of the register.
 A right circular shift operation:
 A left circular shift operation:
 In a RTL, the following notation is used
 cil for a circular shift left
 cir for a circular shift right
 Examples:
 R2 ¬ cir R2
 R3 ¬ cil R3

 An arithmetic shift is meant for signed binary numbers (integer)
 An arithmetic left shift multiplies a signed number by two
 An arithmetic right shift divides a signed number by two
 The main distinction of an arithmetic shift is that it must keep
the sign of the number the same as it performs the multiplication
or division
 A right arithmetic shift operation:
 A left arithmetic shift operation:
0
sign
bit
sign
bit

 An left arithmetic shift operation must be checked for the
overflow
0
V
Before the shift, if the leftmost two
bits differ, the shift will result in an
overflow
sign
bit
• In a RTL, the following notation is used
– ashl for an arithmetic shift left
– ashr for an arithmetic shift right
– Examples:
» R2 ¬ ashr R2
» R3 ¬ ashl R3

Select 0 for shift right (down)
1 for shift left (up)
S
01
MUX H0
S
01
MUX H1
S
01
MUX H2
S
01
MUX H3
Serial
input (IR)
A0
A1
A2
A3
Serial
input (IL)

C
Select
C 4 x 1
i+1 i
S3 S2 S1 S0 Cin Operation Function
0 0 0 0 0 F = A Transfer A
0 0 0 0 1 F = A + 1 Increment A
0 0 0 1 0 F = A + B Addition
0 0 0 1 1 F = A + B + 1 Add with carry
0 0 1 0 0 F = A + B’ Subtract with borrow
0 0 1 0 1 F = A + B’+ 1 Subtraction
0 0 1 1 0 F = A - 1 Decrement A
0 0 1 1 1 F = A TransferA
0 1 0 0 X F = A Ù B AND
0 1 0 1 X F = A Ú B OR
0 1 1 0 X F = A Å B XOR
0 1 1 1 X F = A’ Complement A
1 0 X X X F = shr A Shift right A into F
1 1 X X X F = shl A Shift left A into F
Arithmetic
Circuit
Logic
Circuit
MUX
0123
F
S3
S2
S1
S0
BA
i
A
D
A
E
shr
shl
i
i
i-1
i+1
i
i

Computer basic and cpu

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