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Computer Systems Organization Chapter 2
Central Processing Unit The organization of a simple computer with  one CPU and two I/O devices
CPU Organization The data path of a typical Von Neumann machine.
Instruction Execution Steps Fetch next instruction from memory into instr. register Change program counter to point to next instruction Determine type of instruction just fetched If instructions uses word in memory, determine where Fetch word, if needed, into CPU register Execute the instruction Go to step 1 to begin executing following instruction
Interpreter (1) An interpreter for a simple computer (written in Java). . . .
Interpreter (2) An interpreter for a simple computer (written in Java).
Design Principles for Modern Computers All instructions directly executed by hardware Maximize rate at which instructions are issued Instructions should be easy to decode Only loads, stores should reference memory Provide plenty of registers
Instruction-Level Parallelism A five-stage pipeline The state of each stage as a function of time. Nine clock cycles are illustrated
Superscalar Architectures (1) Dual five-stage pipelines with a common instruction fetch unit.
Superscalar Architectures (2) A superscalar processor with five functional units.
Processor-Level Parallelism (1) An array of processor of the ILLIAC IV type.
Processor-Level Parallelism (2) A single-bus multiprocessor. A multicomputer with local memories.
Primary Memory Memory Addresses (1) Three ways of organizing a 96-bit memory.
Primary Memory Memory Addresses (2) Number of bits per cell for some historically  interesting commercial computers
Byte Ordering (1) (a) Big endian memory  (b) Little endian memory
Byte Ordering (2) (a) A personal record for a big endian machine.  (b) The same record for a little endian machine. (c) The result of transferring from big endian to little endian. (d) The result of byte-swapping (c).
Error Correcting Codes (1) Number of check bits for a code that can correct a single error
Error Correcting Codes (2) (a) Encoding of 1100 (b) Even parity added (c) Error in AC
Error Correcting Codes (3) Construction of the Hamming code for the memory word 11110000010101110 by adding 5 check bits to the 16 data bits.
Cache Memory The cache is logically between the CPU and main memory. Physically, there are several possible places it could be located.
Memory Packaging and Types A single inline memory module (SIMM) holding 256 MB.  Two of the chips control the SIMM.
Memory Hierarchies A five-level memory hierarchy.
Magnetic Disks (1) A portion of a disk track.  Two sectors are illustrated.
Magnetic Disks (2) A disk with four platters.
Magnetic Disks (3) A disk with five zones.  Each zone has many tracks.
SCSI Disks Some of the possible SCSI parameters.
RAID (1)  R edundant  A rray of  I nexpensive  D isks RAID levels 0 through 2.  Backup and parity disks are shown shaded.
RAID (1)  R edundant  A rray of  I nexpensive  D isks RAID levels 3 through 5.  Backup and parity disks are shown shaded.
CD-ROMs (1) Recording structure of a Compact Disk or CD-ROM.
CD-ROMs (2) Logical data layout on a CD-ROM.
CD-Recordables Cross section of a CD-R disk and laser (not to scale).  A CD-ROM has a similar structure, except without the dye layer and with a pitted aluminum layer instead of a reflective layer.
DVD A double-sided, dual layer DVD disk.
Input/Output Buses (1) Physical structure of a personal computer.
Input/Output Buses (2) Logical structure of a simple personal computer.
Input/Output Buses (3) A typical modern PC with a PCI bus and an ISA bus.
CRT Monitors (a) Cross section of a CRT (b) CRT scanning pattern
Flat Panel Displays (a) The construction of an LCD screen. (b) The grooves on the rear and front plates are perpendicular to one another.
Mice A mouse being used to point to menu items.
Printers (1) (a) The letter “A” on a 5 x 7 matrix.  (b) The letter “A” printed with 24 overlapping needles.
Printers (2) Operation of a laser printer.
Printers (3) Halftone dots for various gray scale ranges.  (a) 0 – 6. (b) 14 – 20. (c) 28 – 34.  (d) 56 – 62.  (e) 105 – 111.  (f) 161 – 167.
Telecommunications Transmission of the binary number 01001010000100 over a  telephone line bit by bit.  (a) Two-level signal.  (b) Amplitude  modulation.  (c) Frequency modulation.  (d) Phase modulation.
Digital Subscriber Lines (1) Operation of ADSL.
Digital Subscriber Lines (2) A typical ADSL equipment configuration.
Internet over Cable (1) Frequency allocation in a typical cable TV system  used for Internet access
Internet over Cable (2) Typical details of the upstream and downstream channels in North America.  QAM-64 (Quadrature Amplitude Modulation) allows 6 bits/Hz but only works at high frequencies.  QPSK (Quadrature Phase Shift Keying) works at low frequencies  but allows only 2 bits/Hz.
Digital Cameras A digital camera.
ASCII Character Codes (1) The ASCII Character set: characters 0 – 31.
ASCII Character Codes (2) The ASCII Character set: characters 32 – 127.

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Computer Systems Organization