Introducing OMAP-L138/AM1808 Processor Architecture and Hawkboard Peripherals
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The document introduces the OMAP-L138/AM1808 processor architecture and peripherals on the Hawkboard. It discusses the OMAP-L138 processor which features an ARM9 and DSP subsystem. It also describes the programmable real-time unit (PRU) subsystem which provides additional control and customization. Finally, it provides an overview of various peripherals including SATA, MMC/SD, EMAC, USB, LCD controller, and pulse width modulators.
Introducing OMAP-L138/AM1808 Processor Architecture and Hawkboard Peripherals
- 1. Introducing OMAP-L138/AM1808 Processor Architecture and Hawkboard Peripherals Source: Hawkboard
- 2. Introduction Purpose To introduce Texas Instruments’ OMAP-L138/AM1808 Processor Architecture and Hawkboard Peripherals. Outline OMAP-L138 Processors Overview Programmable Real-Time Unit (PRU) Subsystem Peripheral Overview Hawkboard Content 29 pages
- 3. OMAP-L138(C6L138) Processors Benefits: 450 MHz ARM+DSP Lower power for longer battery life 12mW standby & 450mW active power Dynamic voltage & frequency scaling Large on chip memory, fewer external accesses Mobile DDR support Algorithm precision 32-bit to 64-bit precision floating-point Extended precision fixed-point Software Reuse Code compatibility with previous C6000 devices Scalability between pin-compatible ARM-, DSP-only and ARM+DSP parts Additional control and protocol expansion through PRU subsystem ARM9 Subsystem DSP Subsystem ARM 926EJ-S CPU C674x DSP Core Switched Central Resource (SCR) / EDMA Program/Data Storage I 2 C Serial Interfaces Connectivity System UART McASP SPI MMC/ SD Video I/O LCD Controller uPP McBSP Async EMIF 16-bit mDDR/ DDR2/ SDRAM 16-bit 128KB RAM PRUSS WD Timer PWM SATA UHPI USB2.0 HS USB 1.1 EMAC eCAP Peripherals L1P 32K L1D 32K L2 256K L1P 18K L1D 18K
- 4. Programmable Real-Time Unit (PRU) Subsystem What is PRU? Programmable Real-time Unit Subsystem Dual 32bit RISC processors running at ½ CPU freq. Local instruction and data RAM Access to chip-level resources Why PRU? Full programmability allows adding customer differentiation Efficient in performing embedded tasks that require manipulation of packed memory mapped data structures Efficient in handling of system events that have tight real-time constraints.
- 5. PRU Subsystem Block Diagram Provides two independent programmable real-time (PRU) cores 32-Bit Load/Store RISC architecture 4K Byte instruction RAM (1K instructions) per core 512 Bytes data RAM per core Power management via single power/sleep controller (PSC) PRU operation is little endian Includes Interrupt Controller for system event handling 30 input pins per PRU core 32 output pins per PRU core 32-bit Interconnect SCR PRU0 Core PRU1 Core Interrupt Controller (INTC) DRAM0 (512 Bytes) DRAM1 (512 Bytes) Master I/F (to chip level SCR) Slave I/F (from chip level SCR) 4KB IRAM 4KB IRAM PRU Subsystem Functional Block Diagram 32 GPO 30 GPI Interrupts to ARM INTC Events from Peripherals + PRUs 32 GPO 30 GPI
- 6. PRU Value Extend Connectivity and Peripheral capability Implement special peripherals and bus interfaces (e.g. UARTs) Implement smart data movement schemes. Especially useful for Audio algorithms (e.g. Reverb, Room Correction) Reduce System Power Consumption Allows switching off the ARM/DSP clocks Implement smart power controller by evaluating events before waking up ARM/DSP. Maximized power-down time. Accelerate System Performance Full programmability allows custom interface implementation Specialized custom data handling to offload ARM/DSP for innovative signal processing algorithm implementation TI provided PRU design tool / reference: Overview Programming Guide Software Development Package including assembler
- 8. Universal Parallel Port (uPP) Extends System Interconnect Options High Speed parallel data port Two Bidirectional and Independent 16bit channels Internal dedicated DMA to streamline data I/O Simple I/O Protocol Efficient Processor to FPGA communication enabled by high speed data I/O Enable multi-processor system design in various topologies Interface with high speed ADCs and DACs What Is uPP? Value of uPP Config Registers I/O Channel A I/O Channel B Internal DMA uPP Peripheral External Pins CPU Memory CPU Interrupt Configuration Throughput (MB/s) 1 Ch, 16-bit 120 2 Ch, 1 Way, 8-bit 120 2 Ch, 1 Way, 16-bit 160 2 Ch, 2 Way, 16-bit 240 HPI (16-bit) 50
- 9. Serial ATA (SATA) Interface Supports SATA specification 2.6 Supports Gen1 (1.5Gbits/Sec) and Gen2 (3.0Gbits/Sec) line speed. Cold Presence detect allows use of the SATA Connector capability for Hot Plug support Uses 8b/10b encoding/decoding scheme with a running disparity Supports AHCI Controller 1.1. Supports a single HBA port with the capability of scheduling the max supported number of commands, which is 32 commands. Supports hardware-assisted Native Command Queuing (NCQ) Has the support for an external Port Multiplier Supports Partial and Slumber Power-Down modes Benefit: HDD connectivity for large storage applications. SATA is a low pin count, high-speed serial interface.
- 10. MMC/SD Supports a MultiMediaCard (MMC) / Secure Digital Memory Card (8-bit data bus is available for MMC v4.0), up to 26 MHz The ability to use the MMC/SD protocol and SDIO protocol A programmable frequency of the clock that controls the timing of transfers between the MMC/SD Controller and memory card 512 bit Read/Write FIFO to lower system overhead Signaling to support DMA transfers (slave) 37.5 MHz maximum clock to SD (spec. V2.0) Benefit: Multimedia cards (MMC) and Secure Digital (SD) cards connectivity for medium storage applications plus a high speed interface used to achieve WiFi connectivity
- 11. EMIFA – External Memory Interfaces Benefit: Interface with external memory devices including SDR-SDRAM, ASRAM, NAND Flash & NOR Flash. SDR-SDRAM interface Supports JESD21-C standard compliant SDR SDRAM devices. 512 MB address range over 1 chip select 16-bit wide data bus CAS latencies of 2 & 3 / 1, 2 & 4 internal banks / 256, 512, 1024 & 2048 page sizes Self-refresh, power-down and ‘mclk’ gating for low power. Supports sequential burst type. (Interleaved burst type not supported). Burst length = 8 One CPU interrupt No support of an EDMA event Asyncronous Memory Interface 64MB address range on each of 4 chip selects. 8-bit and 16-bit wide data bus Programmable cycle timings for each chip select Supports page mode for NOR Flash Supports Ready input Supports 1-bit ECC & 4-bit ECC for 8 and 16-bit NAND Flash
- 12. DDR2/mDDR Controller Supports JESD79D-2A standard compliant DDR2 SDRAM 150MHz clock rate 512 MB memory space for DDR2, 256MB memory space for mDDR Supports 16-bit data bus width Supports CAS latencies of 2 – 5 (4 & 5 for DDR2 only) Supports 256, 512, 1024 & 2048 page sizes Supports ‘Self-Refresh’ and ‘Power Down’ modes for low power. Also supports ‘mclk’ gating for low power Supports partial array self refresh in mDDR Supports sequential burst type. (Interleaved burst type not supported) Burst length = 8 No event to EDMA supported Benefit: DDR2/mDDR is used to interface with external DDR2 or mobile DDR memory.
- 13. EMAC – Ethernet Media Access Controller Benefit: The EMAC module provides an efficient interface between the processor and the networked community. The EMAC supports both 10Base-T (10 Mbits/sec) and 100BaseTX (100 Mbits/sec), Standard Media Independent Interface (MII) and Reduced Media Independent Interface (RMII) to physical layer device (PHY) Half or Full duplex Hardware flow control and quality-of-service (QoS) support EMAC acts as DMA master to either internal or external memory space Includes MDIO module to communicate with PHY Eight receive channels with VLAN tag discrimination for receive quality of service (QoS) support Eight transmit channels with round-robin or fixed priority for transmit quality of service (QoS) support Ether-Stats and 802.3-Stats statistics gathering Transmit CRC generation selectable on a per channel basis
- 14. USB 2.0 On-The-Go Benefit: OTG controller provides a mechanism that complies with the USB2.0 standard for data transfer between USB devices up to 480 Mbps. Operating as a host, it complies with USB2.0 standard for high-speed, full-speed and low-speed operation with a peripheral Operating as a peripheral, it compiles with USB2.0 standard for high-speed and full-speed operation with a host Supports USB OTG extensions for Session Request (SRP) and Host Negotiation (HNP) Supports all modes of transfers (control, bulk, interrupt, and isochronous) Supports 4 simultaneous Transmit (TX) and 4 Receive (RX) endpoints, in addition to endpoint 0 Includes a DMA controller that supports 4 TX and 4 RX DMA channels with a max single data transfer size up to 4Mbytes Includes four types of Communications Port Programming Interface (CPPI) 4.1 DMA compliant transfer modes: Transparent, Generic RNDIS, RNDIS, and Linux CDC
- 15. USB 1.1 Host Benefit: OHCI controller makes connecting to devices/targets (e.g. Thumb Drive, HDD, Printer, etc) faster and easier up to a maximum speed of 12 Mbits/Sec. OHCI Host Controller Controller generates USB traffic based on data structures and data buffers stored in system memory Controller accesses the data structures without direct intervention by the processor, which reduces processor software and interrupt overhead. Full Speed rate of 12 Mbit/s Low speed rate of 1.5 Mbit/s
- 16. LCD Controller Supports asynchronous LCD interface (LIDD) to interface to character displays and a synchronous (raster-type) LCD interface to interface to graphical displays for image/video. LIDD mode supports up to 16-bit parallel data output and two displays using primary and secondary chip selects. Raster mode supports 1,2,4,8 bits per pixel passive (Super Twisted Nematic) matrix display and 1,2,4,8,16 bits per pixel active matrix (Thin Film Transistor) display. Raster mode supports up to 1024x1024 display (Frame-rate determined by pixel clock) Frame buffer is programmable and can use either internal or external memory Benefit: The liquid crystal display controller (LCDC) is used to interface to character display panels for text message display or to graphical display panels for image/video display.
- 17. High Resolution Pulse Width Modulators (eHRPWM) Benefit: The High Resolution Pulse Width Modulators (eHRPWM) can effectively generating complex pulse width waveforms with minimal CPU overhead or intervention. Two dedicated 16-bit time-base counter with period and frequency control Asynchronous override control of PWM signals through software Programmable phase-control support for lag or lead operation relative to other eHRPWM modules Dead-band generation with independent rising and falling edge delay control. Programmable trip zone allocation of both cycle-by-cycle trip and one-shot trip on fault conditions. Programmable event prescaling minimizes CPU interrupt overhead. High-resolution PWM allows finer time granularity control of edge positioning (~200 ps)
- 18. Capture Module (eCAP) Benefit: The Capture Module (ECAP) is essential in systems where accurate timing of external events is important. 32-bit time base counter 4-event time-stamp registers (each 32 bits) Edge polarity selection for up to four sequenced time-stamp capture events Interrupt on either of the four events Single shot capture of up to four event timestamps Continuous mode capture of timestamps in a four-deep circular buffer Absolute timestamp capture Difference (Delta) mode timestamp capture All above resources dedicated to a single input pin When not used in capture mode, the eCAP module can be configured as a single channel PWM output
- 19. Host Port Interface (HPI) Multiplexed address and data bus 16-bit data Both the host and the CPU can access the HPI control register (HPIC) and HPI address register (HPIA) Multiple strobes and control signals to allow flexible host connection An external host is capable of accessing most of the on chip memories Benefit: The Host Port Interface (HPI) is a parallel port through which a host processor can directly access program and data memory space. The host device functions as a master to the interface, which increases ease of access.
- 20. McASP – Multichannel Audio Serial Port Benefit: The McASP functions as a general-purpose audio serial port optimized for the needs of multichannel audio applications including time-division multiplexed (TDM) stream, Inter-Integrated Sound (I2S) protocols, and inter-component digital audio interface transmission (DIT). Two independent clock zones (transmit and receive), each with: Programmable high frequency and bit clock generators Programmable frame sync generator Up to 16 serial data pins, individually assignable as Rx or Tx TDM streams from 2 to 32, and 384 time slots Support for slot sizes of 8, 12, 16, 20, 24, 28, and 32 bits Data formatter for bit manipulation Supports I 2 S protocol Integrated digital audio interface transmitter (DIT) supports: S/PDIF, IEC60958-1, AES-3 formats Extensive error checking and recovery
- 21. McBSP – Multichannel Buffered Serial Port Benefit: The McBSP functions as a general-purpose serial port with programmable behavior to conform to multiple serial interface standards. The MCBSP is well-suited for applications with time-division multiplexed (TDM) data streams. Full-duplex communication 128-channel capability Programmable word width (8, 12, 16, 20, 32) Double-buffered data registers, which allow a continuous data stream Direct interface to industry-standard codecs, analog interface chips (AICs) and other serially connected analog-to-digital (A/D) and digital-to-analog (D/A) devices External shift clock or internal, programmable frequency shift for data transfer Transmit and receive FIFOs allow the McBSP to operate at higher sample rates by making it more tolerant to DMA latency.
- 22. SPI Benefit: The SPI is a high-speed synchronous serial input/output port providing an interface to microcontrollers, data converters and serial EEPROMs. Features of SPI include the following: 16-bit shift register 2 to 16 bit data width Receive buffer register (SPIBUF) and Transmit Data Register (SPIDAT0) 8-bit baud clock generator Programmable clock frequency, polarity, phase and character length Multiple SPI modes like 3-pin, 4-pin with Chip select, 4-pin with Enable and 5-pin Maximum SPI clock rate is 50 MHz Applications of SPI include the following: Interface with an external microcontroller Configure ADC’s, DAC’s, display drivers, shift registers Interface with an EEPROM
- 23. UART Benefit: The Universal Asynchronous Receiver/Transmitter (UART) performs serial-to-parallel conversion on data received from a peripheral device or modem, and parallel-to-serial conversion on data received from the internal busses. 16-byte storage space for both the transmitter and receiver FIFOs 1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA DMA signaling capability for both received and transmitted data Programmable auto-rts and auto-cts for autoflow control Frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates Fully programmable serial interface characteristics: 5, 6, 7, or 8-bit characters Even, odd, or no parity bit generation and detection 1, 1.5, or 2 stop bit generation Line break generation and detection Loopback controls for communications link fault isolation 16x or 13x over sampling Maximum UART baud rate: 12 Mbaud
- 24. I 2 C – Inter-Integrated Circuit Benefit: External components attached to the I 2 C bus serially transmit/receive up to 8-bit data to/from the device through the 2-wire I 2 C interface. Compliance with the Philips Semiconductors I 2 C-bus specification (v2.1) One read EDMA event and one write EDMA event, which can be used by the EDMA controller One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following conditions: transmit-data ready, receive-data ready, register-access ready, no-acknowledgement received, arbitration lost Module enable/disable capability Free data format mode
- 25. GPIO – General-Purpose Input/Output Benefit: The general-purpose input/output (GPIO) peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs When configured as an output, the state driven on the output pin is controlled by writing to an internal register When configured as an input, the state of the input pin is obtained by reading the state of an internal register In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different interrupt/event generation modes GPIOs are programmable on a per-pin basis Most pins on the device can be used as GPIO if not used for some other function through configuration of the pin muxing controls.
- 26. Timers Benefit: The device has 64-bit general-purpose timers that can be used to time events, count events, generate pulses, interrupt the CPU, and send synchronization events to the DMA. Each 64-bit timer can be alternately configured as two 32-bit timers. The timers can be clocked by an internal or an external source. The timers have an input pin and an output pin. The input and output pins (TM64P_IN and TM64P_OUT) can function as timer clock input and clock output. With an internal clock, for example, the timer can signal an external A/D converter to start a conversion, or it can trigger the DMA controller to begin a data transfer. With an external clock, the timer can count external events and interrupt the CPU after a specified number of events. Timer1 configurable as a watchdog timer to trigger a system reset.
- 27. Hawkboard Ultra low-cost Open Community Platform OMAP L138 ™ ( ARM- 9 and C674x Floating point DSP) UART Audio IN Audio Out SATA VGA Composite IN JTAG Ethernet USB Host Power Jack USB OTG /Power MMC/SD Expansion SPI uPP PRU VPIF GPIO MMC/SD UART I2C PWM eCAP 128MB DDR 128MB NAND
- 28. XDS100v2 Robust and efficient JTAG emulation controller Plug in and play operation. Twice as fast as XDS100 version 1 Available from Spectrum Digital Blackhawk Build your own! Additional information: http://tiexpressdsp.com/wiki/index.php?title=XDS100
- 29. Additional Resource For ordering OMAP-L138 processor or Hawkboard, please click the part list or Call our sales hotline For more product information go to http://focus.ti.com/docs/prod/folders/print/omap-l138.html http://www.hawkboard.org / Visit Element 14 to post your question www.element-14.com For additional inquires contact our technical service hotline or even use our “Live Technical Chat” online facility Newark Farnell
Editor's Notes
- #2: Welcome to the training module on Introducing OMAP-L138/AM1808 Processor Architecture and Hawkboard Peripherals.
- #3: This training module will introduce Texas Instruments’ OMAP-L138/AM1808 Processor Architecture and Hawkboard Peripherals.
- #4: The OMAP-L138 is a Low-power applications processor based on an ARM926EJ-S™ and a C674x DSP core. The dual-core architecture of the device provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core. The C674x DSP combines the performance of the C64x+ core with the floating-point capabilities and provides the extended precision necessary for high-precision algorithms on a variety of signed and unsigned 32-bit data types. The peripheral set includes: an Ethernet MAC (EMAC),one USB2.0 OTG interface, one USB1.1 OHCI interface, two inter-integrated circuit (I2C), one multichannel audio serial port (McASP), two multichannel buffered serial ports (McBSP), two SPI interfaces, four 64-bit general-purpose timers each configurable (one configurable as watchdog), a configurable 16-bit host port interface (HPI), up to 9 banks of 16 pins of general-purpose input/output (GPIO), three UART interfaces, two enhanced high-resolution pulse width modulator (eHRPWM) peripherals, and 3 32-bit enhanced capture (eCAP) module peripherals. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors.
- #5: The PRU real-time subsystem is a collection of two RISC cores, each with its own instruction and data memory, and fast I/O. The RISC cores of the PRUSS run at half the ARM/DSP clock frequency and have access to other SOC resources (e.g. external memory, peripheral registers, system DMA, etc.). The PRUSS is fully-programmable and can be used to add differentiation to customer products . The PRUSS is well equipped to perform embedded tasks that require manipulation of packed memory mapped data structures. It can also efficiently handle system events that have tight real-time constraints.
- #6: The PRUSS consists of the following blocks: two independent 32-bit RISC processors, each with 4KB of instruction RAM and 512 bytes of data RAM; an interrupt controller for system event handling; and a I/O interface with up to 30 input pins and 32 output pins per PRU core on the AM18x. The AM17x PRU does not support I/O pins but can still be used for a variety of purposes such as custom data movement schemes, custom timers, etc. Note that although PRU can only run from its dedicated instruction RAM, it can be reset and new code can be loaded. This allows you to use the PRU for multiple functions.
- #7: The PRUSS provides several benefits. It can be used to extend connectivity and enhance peripheral capability on AM1x devices. Customers can implement special peripherals (e.g. 9-bit UART) and bus interfaces. The PRU can also be used to implement smart data movement schemes (e.g. circular DMA). The PRUSS can also be used as a smart power controller. Allowing you to turn switch off the clock to the ARM; only waking up the core when specific events are detected. The PRUSS can be used to offload data handling tasks from the ARM, freeing up those core for other tasks. The full programmability of the PRU allows customers to implement custom interfaces.
- #8: Now let’s look at the rich peripheral set.
- #9: The universal parallel port (uPP) peripheral is a multichannel, high-speed parallel interface with dedicated data lines and minimal control signals. It is designed to interface cleanly with high-speed analog-to-digital converters (ADCs) or digital-to-analog converters (DACs) with up to 16-bit data width (per channel). It may also be interconnected with field-programmable gate arrays (FPGAs) or other uPP devices to achieve high-speed digital data transfer. It can operate in receive mode, transmit mode, or duplex mode, in which its individual channels operate in opposite directions. The uPP peripheral includes an internal DMA controller to maximize throughput and minimize CPU overhead during high-speed data transmission. All uPP transactions use the internal DMA to feed data to or retrieve data from the I/O channels. The DMA controller includes two DMA channels, which typically service separate I/O channels. The uPP peripheral also supports data interleave mode, in which all DMA resources service a single I/O channel. In this mode, only one I/O channel may be used. Maximum clock is ¼ of the CPU clock. Each channel can access 16 data signals. These signals are allocated to the channels depending on the mode of the UPP. The throughput data shown are about 80% of the maximum theoretical through put to account for other system traffic. The uPP is pin multiplexed with the video port input, HPI, PRU Subsystem, EMAC RMII and LCD interfaces, but since pin muxing is programmable on a per pin basis, many configurations are possible to support several of these peripherals at once.
- #10: Parallel ATA (PATA) design throughput has maximum data transfer to 133MBytes/Sec and was unable to increase transmission rate due to hardware limitation. This limitation birthed SATA. SATA has lower pin count, operates at a much lower signal level (500mW peak-to-peak), and is scalable with frequency. Gen3 is now delivering 6GBits/Sec raw bandwidth. SATA uses two bi-directional differential data lines. While one is being used to transmit data and the other being used for transmitting status. So the 1.5Gbits/Sec and 3Gbits/Sec of throughput is the throughput on the transmit differential data line only. Differential lines makes design more robust making it immune from noise and less susceptible to EMI. No skew issues exist as when you have a single data line. Lower pin counts implies lower complexity of board design and lower cost. The 8b/10b encoding increases the size of the data by 25% since an 8-bit data is encoded to a 10-bit data prior to transmission. This allows for sufficient 1-to-0 and 0-to-1 transition in the bit stream allowing for clock recovery and eliminating a high-frequency clock signal. Reliability and performance comes with a price tag. Also 8b/10b encoding scheme makes uses of a running disparity scheme, i.e., maintains the balance of 1’s and 0’s transmitted or DC Balanced. Running Disparity protocol also has transmission error capability, errors introduced on the bus altering disparity would be identified. Legacy Mode is not supported, i.e., does not have shadow task file registers, and command processing is performed based on AHCI operation. AHCI makes use of data structures and Frame Information Structure (FIS). However AHCI maintains the software compatibility with legacy software and complies with the ATA/ATAPI-7 PATA Command Execution specification. NCQ allows devices to execute commands not only out of order but also execute commands partially minimizing access latency. H/W assist allows the Device to control the onboard SATA Controller DMA to fetch data from AM18x memory. A Port Multiplier allows up to 15 devices to be attached to a single HBA Port and the SATA controller has the H/W support to enable that.
- #11: In SD mode, 1-bit and 4-bit data buses are supported, as is SDHC (Class 2, 4, and 6 cards ranging from 4GB to 32GB have been verified up to 37.5MHz). In MMC mode, 1-bit, 4-bit, and 8-bit buses have been verified up to 26MHz. This peripheral should also support 1- and 4-wire SD cards and SDHC, but these configuration shave not yet been confirmed by TI.
- #12: The EMIFA is one of two memory interfaces on AM1x devices. The EMIFA is used to interface with external memory devices including SDR-SDRAM, ASRAM, NAND Flash & NOR Flash. The CPU, EDMA, and other master peripherals use the EMIFA to access data in external memory. The EMIFA can interface with up to 128Mbytes of single data rate (SDR) SDRAM over a 16-bit bus. Configurable CAS latencies and memory timings allow the EMIFA to support a wide range of SDRAM devices. Through its asynchronous interface, the EMIFA can also connect w/o glue logic to memory devices like ASRAM, NAND Flash, and NOR Flash as well as ASICs and FPGAs. The EMIFA supports both 8- and 16-bit devices and it’s programmable cycle timings allow for a wide range of memory devices to be supported. For 8- and 16-bit NAND flash, the EMIFA supports 1-bit and 4-bit ECC.
- #13: The DDR2/mDDR controller is one of two memory interfaces on AM18x devices. The DDR2/mDDR controller is used to interface with DDR2 and mDDR SDRAM devices. The CPU, EDMA, and other master peripherals use the DDR2/mDDR controller to access data and instructions in external memory. The DDR2/mDDR controller can interface with up to 512Mbytes of double data rate (DDR) SDRAM over a 32-bit bus. Configurable CAS latencies and memory timings allow the DDR2/mDDR controller to support a wide range of DDR SDRAM devices.
- #14: The EMAC module on AM1x supports the standard RMII interface to connect with Ethernet PHYs. The MII interface is available on AM18x only, and only one EMAC interface (RMII or MII) can be enabled at a time because there is only one physical EMAC module. Both 10- and 100-Mbps speeds are supported at full- and half-duplex modes. A local CPPI memory is included to store EMAC packet descriptors. When connected to a multi-port switch PHY, the VLAN tag support allows the EMAC to discriminate between multiple virtual networks. A “Clause 22” MDIO interface is included to handle the configuration and management of connected Ethernet PHYs. Aside from the intended purpose of interfacing with ethernet PHYs, the EMAC module can also be used to enable communication between embedded processors that also have EMAC interfaces. This application is not officially supported.
- #15: USB 2.0 h as built in PHY with UTMI interface. It supports all three speeds/devices via a 2.0 Hub when operating as a Host. As a Host it supports a Multi-point setup where multiple devices are connected via a Hub. It has dedicated hardware, USB_DRVVBUS, that is directly controlled by the USB controller, to enable/disable external power logic (charge pump). Endpoints 1 to 4 are all capable of handling all the four transfers. Endpoint 0 is serviced via CPU only. EPs 1 to 4 are serviced via CPU as well as DMA. A 4KBytes of FIFO RAM is available for user software to configure as application desires. DMA makes use of Descriptors and Multiple queues easing the use of scatter gather functionality and allowing multiple transactions to be queued. Without a support of queue, only a single transfer can be handled one at a time which is a burden for a busy CPU.
- #16: USB 1.1 is an OHCI controller with an internal PHY. It supports both full speed and low speed in host mode only.
- #17: Realistically, a 50MHz pixel-clock is supported across operating modes. The memory bandwidth has been successfully stress-tested with a continuous 75MHz pixel-clock, where concurrent activity is managed with priority settings. **** However, the datasheet spec for max pixel-clock frequency is the current performance limiter **** TI is evaluating whether this spec can be raised. There is a wiki article on LCDC throughput performance: http://tiexpressdsp.com/index.php/OMAP-L1x/C674x/AM1x_LCD_Controller_%28LCDC%29_Throughput_and_Optimization_Techniques
- #18: The Enhanced High Resolution Pulse Width Modulators (eHRPWM) can effectively generating complex pulse width waveforms with minimal CPU overhead or intervention. There are three eHRPWMs available on AM1707, and two eHRPWMs on AM1808.
- #19: The Enhanced Capture Module is essential in systems were accurate timing of external events is important. Some of the uses for eCAP include sample rate measurements of audio inputs, speed measurements of rotating machinery (for example, toothed sprockets sensed via Hall sensors), elapsed time measurements between position sensor pulses, period and duty cycle measurements of pulse train signals, and decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors.
- #20: The HPI provides a memory-like interface where an external host can gain access to memory inside the AM1x. This can be used for boot purposes or to exchange data in a multi-processor system. The interface is similar to an asynchronous memory.
- #21: The McASP is designed for audio applications. Each McASP module is highly configurable for format (data size and alignment) and supports multiple streams of synchronized serial data – thus multiple channels of audio can be transported simultaneously. AM1x includes McASP data FIFOs that are designed to relax real-time requirements (enhancement over previous devices). EDMA is the recommended resource to service McASP. Aside from the standard audio application, it’s possible to retask the McASP for other functions such as generating arbitrary waveforms at slow frequencies. For example, the McASP can be configured to operate at 50MHz with a single 32-bit slot; with this setup, a 1.56MHz (50MHz/32-bits) square wave can be created with 20ns of resolution for modifying the pulse-width (potential PWM). This application is not officially supported.
- #22: The McBSP is designed to interface to a variety of serial industry standard devices. Receive and transmit are fully independent and have flexible programmability of clock, phase and frame behavior. The McBSP can work with TDM data streams of up to 128 channels. AM18x includes McBSP data FIFOs that are designed to relax real-time requirements by making the port less sensitive to DMA latencies.
- #23: The Serial Port Interface is a synchronous serial input/output port that enables interfacing with external microcontrollers and EEPROMs. It can also be used to configure ADC’s, DAC’s display drivers, shift registers etc. Multiple SPI Modes are supported , like 3 pin, 4 pin with Chip Select , 4 pin with Enable and 5-pin. The SPI can be a master or slave.
- #24: The UART is used to interface to peripheral devices or modems. The UART supports autoflow control signals (CTS and RTS) as well as modem control functions (DSR, DTR, RI, DCD). Through its frequency pre-scaler, multiple baud rates can be supported including: 9600, 14400, 19200, 38400, 57600, and 115200 . The UART also supports 13x and 16x oversampling.
- #25: I 2 C module allows AM1x to communicate with other board components using a 2-pin shared bus in both Master and Slave configurations. The I2C specification is supported by a large number of manufacturers for common interoperability.
- #26: The general-purpose input/output (GPIO) peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different interrupt/event generation modes.
- #27: The device has 64-bit general-purpose timers that can be used to time events, count events, generate pulses, interrupt the CPU, and send synchronization events to the DMA. It has an interrupt/event enable/status register. Read Reset timer mode to reset the timer count when the counter registers are read. Reload registers to automatically update the Period register and restart the timer counter when the initial timeout Period is reached. Capture registers to record the counter value of a timer upon a timeout or external event. 8 Compare registers with individual interrupts that trigger when the counter matches the compare values.
- #28: Now let’s look at the development tool - Hawkboard. The Hawkboard is an open-source community board that was developed by an external vendor using the OMAP-L138 processor. It’s intended to showcase the performance of the high-precision floating-point DSP with the flexible ARM9 processor in an ultra low-cost development environment. This development platform has all the basic components needed for full feature development and is support totally by the Hawkboard community at www.hawkboard.org.
- #29: A brand new product, the XDS100v2 is a very inexpensive JTAG emulator solution. For less than $80, you get the capability to interact and control the AM1x. This emulator is powered by and works using USB, and is available from Spectrum Digital and Blackhawk. TI makes the design files available so you can EVEN BUILD YOUR OWN. If you have the board space available, one idea is to design this down onto your own product as a debugging section for development purposes. The XDS100v2 only works with CCS4 and later. For additional information, you can go to the wiki page shown here.
- #30: Thank you for taking the time to view this presentation on “ Introducing OMAP-L138/AM1808 Processor Architecture and Hawkboard Peripherals ” . If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simply call our sales hotline. For more technical information you may either visit the Hawkboard or TI site, or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility. You may visit Element 14 e-community to post your questions.