Computer Organisation and Architecture

Basic Processing Unit
Mr. SUBHASIS DASH
SCHOLE OF COMPUTER ENGINEERING.
KIIT UNIVERSITY, BHUBANESWAR, ORISSA

Basic Processing Unit
• Introduction
• Single Bus Organization
• Register transfer operation
• Fetch & store of a word (Memory)
• Execution of a complete instruction
• Multiple Bus Organization
• Hardwired & Micro-programmed Control

Fundamental Concepts
 Processor fetches one instruction at a time and
perform the operation specified.
 Instructions are fetched from successive
memory locations until a branch or a jump
instruction is encountered.
 Processor keeps track of the address of the
memory location containing the next instruction
to be fetched using Program Counter (PC).
 Instruction Register (IR)

Executing an Instruction
 Fetch the contents of the memory location
pointed to by the PC. The contents of this
location are loaded into the IR (fetch phase).
IR ← [[PC]]
 Assuming that the memory is byte addressable,
increment the contents of the PC by 4 (fetch
phase).
PC ← [PC] + 4
 Carry out the actions specified by the instruction
in the IR (execution phase).

Single Bus Organization
MDR HAS TWO
INPUTS AND
TWO
OUTPUTS
lines
Data
Address
lines
bus
Memory
Carry-in
ALU
PC
MAR
MDR
Y
Z
Add
XOR
Sub
bus
IR
TEMP
R0
control
ALU
lines
Control signals
R n 1-( )
Instruction
decoder and
Internal processor
control logic
A B
Single-bus organization of the data path inside a processor.
MUXSelect
Constant 4

Operational steps of single bus organization
 Data & address lines of external memory bus is connected to
the internal processor bus via MDR, MAR respectively.
 MDR has two input & two output because LOAD & STORE
operations on MDR can be performed through external memory
or internal processor bus.
 Control lines of memory bus are connected to instruction
decoder & control logic block, to issue signals that control
operations of all units in processor.
 A set of GPR used by users.
 A set of special register Y [input], Z [output] & TEMP (Never
used in instructions but only used for processor at the time of
execution).
 MUX select either data from Y or CONSTANT value (4) as input A
& another operand directly from internal processor bus to ALU
for execution.
 Register, ALU & interconnecting bus are collectively referred as
data path.

Operational steps of single bus organization
 Transfer a word of data from one
processor register to another or to the
ALU.
 Perform an arithmetic or a logic operation
and store the result in a processor
register.
 Fetch the contents of a given memory
location and load them into a processor
register.
 Store a word of data from a processor
register into a given memory location.

Register Transfers
 For each register, two control signals
are used one is to place the content of
the register on bus or to load data from
bus into register.
 I/P & O/P of Ri are connected to the bus
through switches by the signals Riin
&
Riout
respectively.
 Riin
= 1 then data on bus is loaded to Ri .
 Riout
= 1 then contains of Ri is loaded to
bus.
 EXAMPLE:- R1  R4
 R1out
= 1 contains of R1 is loaded to
bus.
 R4in
= 1 load data from processor
bus to R4.

Performing an Arithmetic or Logic
Operation
 The ALU is a combinational circuit that has no internal
storage.
 ALU gets the two operands from MUX (operand A)and
bus(operand B). The result is temporarily stored in
register Z.
 What is the sequence of operations to execute
R3  M[R1]+R2 ???
1. R1out, Yin
2. R2out, Select Y, Add, Zin
3. Zout, R3in

Fetching a Word from Memory
 Address into MAR; Issue read operation; Data into MDR.
MDR
Memory bus
Connection and control signals for register MDR
data lines
Internal processor
busMDR out
MDR outE
MDR in
MDR inE

 Processor has to specify memory location where data is stored &
request a read operation.
 Transfer the address to MAR whose output is connected to address
lines of memory bus & control lines identify the READ operation.
 Receive the data from memory & stored at MDR. It has 4 control
signals.[MDR in & MDR out ] [ MDR inE &MDR outE ]
 READ & WRITE operation must be synchronized as per the internal
processor clock.
 The response time of each memory access varies (cache miss,
memory-mapped I/O,…).
 To accommodate this, the processor waits until it receives an indication
that the requested operation has been completed (Memory-Function-
Completed, MFC).

Timing
Diagram
Assume MAR
is always available
on the address lines
of the memory bus.
R2 ← [MDR]
MAR ← [R1]
Start a Read operation on the memory bus
Wait for the MFC response from the memory
Load MDR from the memory bus
Figure 7.5. Timing of a memory Read operation.
1 2
Clock
Address
MR
Data
MFC
Read
MDR
inE
MDR
out
Step 3
MAR
in
MDRinE = 1

• Consider the instruction Move (R1), R2 {R2  M[R1]}
• The actions needed to execute this instruction
1. MAR ← [R1]
2. Start a Read operation on the memory bus
3. Wait for the MFC response from the memory
4. Load MDR from the memory bus
5. R2 ← [MDR]
 The above steps can be described by signals being activated as
follows :-
1. R1out , MARin , READ
2. MDRinE, WMFC
3. MDRout, R2in

Storing a Word in Memory
• Consider the instruction Move R2, (R1) {M[R1]  [R2]}
• The actions needed to execute this instruction
1. MAR ← [R1]
2. Start a Write operation on the memory bus
3. MDR  [R2]
4. Write commend is issued through memory external bus.
5. Wait for the MFC response from the memory.
 The above steps can be described by signals being activated
as follows :-
1. R1out , MARin
2. R2out , MDRin, WRITE
3. MDRoutE, WMFC

Execution Of A Complete Instruction
 Consider the instruction Add (R3), R1 { R1  R1+[R3] }
 The actions needed to execute this instruction
1. Fetch the instruction is performed by ACTION 1,2,3.
a. Instruction fetch operation is initiated by loading the content of PC into MAR & sending a
READ request to memory.
b. The SELECT signal is set to select4, which causes t MUX to select constant 4. This value
is added to operand at input B, which is the content of PC & result is stored in register Z.
[The above both steps are during ACTION 1]
c. The updated value is moved from register Z back to PC during ACTION 2 while waiting for
the memory to respond.
d. The word fetched from the memory is loaded into IR during ACTION 3.
2. Fetch the both the operand to Perform the addition by ACTION 4,5,6.
a. Instruction decoding circuit interprets the contains of the IR like mode of execution, op-
code, operand during ACTION 4.
b. Contains of the register R3 are transferred to MAR & memory READ operation is initiated
during ACTION 4.
c. Contains of R1 is transferred to input register Y & wait for memory read operation to
complete during ACTION 5.
d. When memory READ operation is completed, operand is available in register MDR. Then
contains of MDR goes to input register B of the ALU as 1st
operand & register Y is selected
as the 2nd
operand. The addition operation is performed & result is stored in register Z
during ACTION 6.
3. Load the result into R1 performed by ACTION 7.
a. Transfer the result from register Z to R1 & END signal causes a new instruction fetch cycle
to begin by returning to ACTION 1.

Execution of a Complete Instruction
Add (R3), R1 R1  R1+[R3]
lines
Data
Address
lines
bus
Memory
Carry-in
ALU
PC
MAR
MDR
Y
Z
Add
XOR
Sub
bus
IR
TEMP
R0
control
ALU
lines
Control signals
R n 1-( )
Instruction
decoder and
Internal processor
control logic
A B
Single-bus organization of the data path inside a processor.
MUXSelect
Constant 4
Step Action
1 PC out , MAR in , Read, Select4,Add, Zin
2 Zout , PC in , Yin , WMFC
3 MDR out , IRin
4 R3out , MAR in , Read
5 R1out , Yin , WMFC
6 MDR out , SelectY, Add, Zin
7 Zout , R1in , End
Con trol sequenceforexecutionofthe instructionAdd (R3),R1.

Execution of Branch Instructions
 A branch instruction replaces the contents of PC with the branch target
address, which is usually obtained by adding an offset X given in the
branch instruction.
 The offset X is usually the difference between the branch target
address and the address immediately following the branch instruction.
 The offset value is extracted from IR by instruction decoding circuit.
 PC is already available in register Y & offset is added to it during
ACTION 4.
 The result which is the branch target address, is loaded into the PC.
 NOTE:
1. Signal Yin, There is no need to copy the updated contains of the PC into
register Y when executing addition instruction during ACTION 2.
2. But, in branch instruction the updated value of the PC is needed to
compute the branch address.
3. To speed up the execution of branch instructions, updated value of the
PC is stored in register Y in ACTION 2.
4. As ACTION 2 is the part of instruction fetch, this action will be
performed for all instructions. This does no harm because register Y is
not used for any other purpose at the same time.

Execution of Branch Instructions
Step Action
1 PCout, MAR in , Read,Select4, Add,Zin
2 Z out ,PC in , Yin, WMFC
3 MDRout , IR in
4 Offset-field-of-IR out,Add,Zin
5 Zout, PCin , End
Control sequence for an unconditional branch instruction.

Execution of Conditional Branch Instruction
ActionStep
1 PCout, MAR in , Read,Select4, Add,Zin
2 Z out,PC in , Yin, WMFC
3 MDRout , IR in
4 Offset-field-of-IR out,Add,Zin
5 Zout, PCin , End
Control sequence for an conditional branch instruction.
1. Check the status of the
condition code before
loading a new value
into PC.
2. Ex. Branch if
negative instruction
If N= 0 then End
Processor returns to
step No. 1 immediately
after step 4.
If N= 1
Then step 5 is performed to load a new
value into PC to start branch operation

Drawback  In single bus structure the resulting control
sequences are quite long because only one
data can be transferred over the bus in a
clock cycle.
Hence to reduce the number control
sequences, most of the processors provide
multiple internal paths that enable several
transfers to take place in parallel.
Why Multiple-Bus Organization

Multiple-Bus Organization
■ There are 3 internal bus structure to connect registers & ALU of
processor.
 Register File  All GPR are combined into a single block. [ Due to VLSI]
 Register file have 3 ports.
 Two O/P port allow contains of two different to be accessed
simultaneously & place those contains on bus A & B.
 One I/P allows data on bus C to be loaded into a 3rd
register during
same clock cycle.
 Bus A & B used to transfer source operand to A & B inputs of ALU.
 Result is transferred to destination through Bus C.
 If needed, ALU can pass one of its two operands unmodified [ Without
operation ] to bus C. ALU control signal for such operation is R=A or
R=B.
 Incrementer unit eliminates the need to add 4 to PC to update its
location using main ALU.
 But the source for CONSTANT 4 at ALU input is still useful, to increment
other addresses like memory addresses in LOADMULTIPLE &
STOREMULTIPLE type instructions.

Memory b us
data lines
Three-b us or g anization of the datapath.
Bus A Bus B Bus C
Instruction
decoder
PC
Re gister
file
Constant 4
ALU
MDR
A
B
R
MUX
Incrementer
Address
lines
MAR
IR

 Consider the instruction Add R4, R5, R6 R6  R4+R5
 The actions needed to execute this instruction
1. Fetch the instruction is performed by ACTION 1,2,3.
a. PC value is passed through ALU using R=B control signal, & loaded into MAR to start
memory read operation. [During ACTION 1]
b. Processor wait for MFC & load data received from memory through data line into MDR &
then transfer the same data to IR . [During ACTION 2 & 3 respectively.]
2. Execution of instruction by ACTION 4.
a. Execution phase of the instruction transfers both the operands from R4 & R5 through
bus A & B. Then store the result through bus C to R6.

 Add R4, R5, R6 R6  R4 + R5
Step Action
1 PCout, R=B, MARin, Read, IncPC
2 WMFC
3 MDRoutB, R=B, IRin
4 R4 ,
outA
R5
outB
SelectA,,Add, R6in
, End
Control sequence for the instruction. Add R4,R5,R6,
for the three-bus organization
,
Memory bus
data lines
Three-bus organization of the datapath.
Bus A Bus B Bus C
Instruction
decoder
PC
Register
file
Constant 4
ALU
MDR
A
B
R
MUX
Incrementer
Address
lines
MAR
IR

TYPES OF CONTROL SIGNAL
 To execute instructions, the processor
must have some means of generating the
control signals needed in the proper
sequence.
 Two categories:
1. Hardwired control
2. Micro-programmed control
 Hardwired system can operate at high
speed; but with little flexibility.

HARDWIRED CONTROL
 The sequence of control signal describes fetch of an instruction from memory within 3
non-overlapping clock cycles & execution of an instruction are also in various non-
overlapping clock cycles.
 All time cycles are equal of equal duration & must be at least of such a duration which
large enough to complete the specified action.
 CU use a counter which is driven by a clock signal for each step being required for
complete execution of an instruction.
 Required control signal are uniquely determined by the following facts:-
1. Contains of the control step counter.
2. Contains of the instruction register.
3. Contains of the condition codes & status flags.
4. External input signal such as MFC & interrupt request.
 The decoder / encoder block is a combinational circuit which generates required control
signal depending on the state of all inputs.
 Step decoder is placed at the control step counter to provide separate signal line for each
step or clock cycle, in the control sequence.
 Instruction decoder decodes each instruction to specify type of operation to be
performed & maintains separate lines for each machine instruction.

DETAILED BLOCK DESCRIPTION
HARDWIRED CONTROL
External
inputs
Separation of the decoding and encoding functions.
Encoder
Reset
CLK
Clock
Control signals
counter
Run End
Condition
codes
decoder
Instruction
Step decoder
Control step
IR
T
1
T
2
T
n
INS
1
INS
2
INS
m

HARDWIRED CONTROL
Continued
 For any instruction loaded in IR one of the out put lines INS1 through INSm is set to 1
& all other line are set to 0.
 The output of the step decoder, instruction decoder, condition codes & status flag
can be applied as combined input to encoder to produce a set of control signals at
each step of an instruction.
 The END signal starts a new instructions fetch cycle by resetting the control step
counter to its starting value.
 The RUN control signal is used to issue WMFC, to cause processor to wait for the
replay from memory.
 When RUN = 1, causes the counter to be incremented by 1 at end of every clock
cycle & RUN = 0, counter stops counting.
 Sequence of operations carried out by machine is determined by wiring of the logic
elements, hence named as hardwired.

Generating Zin Signal
Zin = T1 + T6 • ADD + T4 • BR + …
Generation of the Zin control signal for single bus processor .
T1
AddBranch
T4 T6
Step Action
1 PC out , MAR in , Read, Select4, Add, Zin
2 Zout , PC in , Yin , WMF C
3 MDR out , IRin
4 R3out , MAR in , Read
5 R1out , Yin , WMF C
6 MDR out , SelectY, Add, Zin
7 Zout , R1in , End
Con trol sequencefor execution of the instruction Add (R3),R1.

Generating End Signal
End = T7 • ADD + T5 • BR + (T5 • N + T4 • N) • BRN +…
Generation of the End control signal.
T7
Add Branch
Branch < 0
T5
End
NN
T4
T5

MICRO-INSTRUCTION AN EXAMPLE
Step Action
1 PC
out
, MAR
in
, Read, Select4, Add, Z
in
2 Z
out
, PC
in
, Y
in
, WMF C
3 MDR
out
, IR
in
4 R3
out
, MAR
in
, Read
5 R1
out
, Y
in
, WMF C
6 MDR
out
, SelectY, Add, Z
in
7 Z
out
, R1
in
, End
Con trol sequence for execution of the instruction Add (R3),R1.
Add (R3), R1 R1  R1+[R3]

MICRO-INSTRUCTION AN EXAMPLE
 Control signals are generated by a program similar to machine
language programs.
 Control Word (CW); micro-routine; microinstruction
PCin
PCout
MARin
Read
MDRout
IRin
Yin
Select
Add
Zin
Zout
R1out
R1in
R3out
WMFC
End
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
1
0
0
Micro -
instruction
1
2
3
4
5
6
7
Example of micro-instructions

MICROPROGRAMMED CONTROL
 An alternative approach to hardwired control is micro-programmed control in
which control signals are generated by a program.
 Control Word (CW) :-
1. A word whose individual bits represents various control signals.
2. Each of control step in control sequence of an instruction can be
defined as control word.
3. A control word always unique combination of 0 & 1.
4. A sequence of control word corresponding to the sequence of control
steps of an instruction is known as micro-routine for that instruction.
5. Individual control word in micro-routine is called as micro instruction.
6. Micro-routines corresponding to an instruction set, of a computer
program are stored in a special memory called as micro-program
memory/control store.

7. Control unit can generate control signals for any instruction by
sequentially reading control word of the corresponding micro-routine
from control store.
8. To read control word sequentially from control store, a micro-program
counter [µPC] is used.
9. Each time a new instruction is loaded into IR, the output of the block
labeled “Starting Address Generator” is loaded into the µPC.
10. The µPC is then automatically incremented by the clock, causing
successive micro-instructions to b read from the control store.
11. Therefore the control signals are delivered to the various parts of the
processor in the correct sequence.

 Control store
One Function
Cannot Be Carried
Out By This Simple
Organization.
Basic organization of a micro-programmed control unit.
store
Control
generator
Starting
address
CW
Clock µ PC
IR

 Control flag & Status flag :-
1. When conditional branch instruction is used, the micro-instruction set expand
to include some conditional branch micro-instruction.
2. Apart from branch address instructions, these micro-instructions can specify
which of the external inputs / status flags, condition code or bits of IR should
checked as condition for branching to take place [Branch untaken / taken].
3. If condition satisfied then branch target address is the output of starting
branch address generator & input to µPC to start branch micro-instruction
execution.
 To enable execution of micro-instructions in proper sequence, µPC is incremented
each time to a new micro-instruction fetched from micro-program memory, except
in following manner:-
1. When a new instruction is loaded into IR, the µPC is loaded with the starting
address of the micro-routine for that instruction.
2. When a branch micro-instruction is fetched & branch condition is satisfied, µPC
is loaded with the branch target address.
3. When an end micro-instruction is encountered, µPC is loaded with address of
the first control word in the micro-routine for the instruction fetch cycle.

Conditional Branch Micro-instruction
Execution
 INSTRUCTION BRANCH<0
 Once the branch instruction is loaded into the IR, the branch micro-
instruction transfers control to the corresponding micro-routine, which
is assume to be start at location 25.
 The address is the output of the starting branch address generator
block.
 The micro-instruction at location 25 tests the N-bit of the condition
codes.
 If this bit N=0,
1. Then a branch take place to a location 0 to fetch a new machine instruction.
[ Branch Untaken ]
2. Otherwise [ N < 0 ], the micro-instruction at location 26 is executed to put the
branch target address into Z register. [ Branch Taken ]
 The micro-instruction in the location 27 loads this address into µPC.

Organization of control unit to allow conditional branching in microprogram.
Control
store
Clock
generator
Starting and
branch address
Condition
codes
inputs
External
CW
IR
µ PC

 The previous organization cannot handle the situation when the
control unit is required to check the status of the condition codes
or external inputs to choose between alternative courses of action.
 Use conditional branch microinstruction.
Address Microinstruction
0 PC out , MAR in , Read, Select4, Add, Z in
1 Zout , PC in , Y in , WMF C
2 MDR out , IR in
3 Branch to starting address of appropriate microroutine
. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ... ..
25 If N=0, then branch to microinstruction 0
26 Offset-field-of-IR out
, SelectY, Add, Z in
27 Zout , PC in , End
Figure 7.17. Microroutine for the instruction Branch<0.

Microinstructions
 A straightforward way to structure microinstructions is to assign one
bit position to each control signal.
 However, this is very inefficient.
 The length can be reduced: most signals are not needed
simultaneously, and many signals are mutually exclusive.
 All mutually exclusive signals are placed in the same group in binary
coding.
Further Improvement
 Enumerate the patterns of required signals in all possible
microinstructions. Each meaningful combination of active control
signals can then be assigned a distinct code.
 Vertical organization
 Horizontal organization

Wilkes Control
 1951 Wikes first proposed the use of microprogrammed control unit WILK51
& further WILK53.
 The main part of the system is Matrix partially filled with diodes.
 During cycle, one row of matrix is activated with a pulse
1. Generates signals where diode present [A dot in diagram]
2. First part of row generates control signal which controls operation of processor.
3. Second part of row generates address of row to be pulsed for next M/C cycle.
4. Each row of matrix is one instruction & layout of matrix is the control memory.
 At beginning of cycle, address of row to be pulsed is contained in REGISTER I
 As clock pulse activates, same address is input to decoder & activates 1 row
of matrix.
 Depending on the control signal,
1. EITHER the opcode is in the instruction register
2. OR second part of the pulsed row is passed into the REGISTER II
 Register I & II both are gated with same clock to alternate clock pulse used
to activate row of matrix & transfer from Register II & I.
 NOTE:- COMPARISION  In Microprogrammed control unit, control address
register incremented by 1 to get next address but in Wilkes scheme the next
address is in microinstruction. To permit branching, a row must be contain 2
address parts controlled by a conditional signal.

Wilkes's Microprogrammed Control Unit
PART 1
PART 2

Computer Organisation and Architecture

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