Computer Organisation Part 4
Download as PPTX, PDF7 likes1,770 views
The document provides information about basic computer organization including the CPU, memory, buses, and input/output components. It discusses the CPU components like the ALU, registers, and control unit. It describes different types of memory like RAM, ROM, and I/O. It also explains the various buses used in a computer like the address bus, data bus, and control bus.
![1. ADD[6] Direct Pointer (The address of operand is available in instruction (ORIGINAL WORKING)) At location 6 (0110) , we are having address 9 (1001) of operand (1001011101).2. Add 6 Immediate (Data is part of instruction , data is not in any register or memory) Here, data is available is Instruction, 6 (0110) is itself is dataIADD[6] Indirect (Pointer) At location 6 (0110) , we are having address 9 (1001), of memory location which is having address of operand (1001011101).It means it is concept of pointer to pointer0110100110011001011101011010011001110011001001011101Krishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com](https://image.slidesharecdn.com/coa-1four-090729080935-phpapp02/85/Computer-Organisation-Part-4-14-320.jpg)
![Implied Mode : ( operand is at CPU’s register ) CMA Compliment ACC. STC Set CarryImmediate Mode : ( data is part of Instruction ) ADD 6 Add 6 to AccumulatorRegister Mode : ( Operand is available in GPR ) ADD B A A + B ADD A , B A A + B ADD R1 R0 R0 + R1Register Indirect Mode : IADD B A A + [M]B the content of Memory M whose address is given by register B must be Added to AKrishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com](https://image.slidesharecdn.com/coa-1four-090729080935-phpapp02/85/Computer-Organisation-Part-4-15-320.jpg)
Computer Organisation Part 4
- 1. BASIC COMPUTER ORGANISATIONGod’s Organisation Krishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 2. CPUTRIODEI/OMEMORYBuses :A Bus (Address Bus)D Bus (Data Bus)C Bus (control Bus)System Buses (Collection of A,B,C)Note : Primary Memory directly addressable by CPU Secondary Memory not directly addressable by CPUKrishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 3. MemoryRAMROMIOCI/P 1VFLAGINTERFACEI/P 2...ALUI/P nGPRACCO/P 1O/P 2...PCSPO/P mIRI/OTIMING &CONTROLKrishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 4. Krishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.comBus Convention :A/B BusC BusExchange of Information : UnidirectionalNote :I / O Control : South BridgeMemory Control : North BridgeNote :Memory which can be change itself is known as register.Note :Every CPU is microprocessor, But every microprocessor is not CPU
- 5. Transformation mechanism that transforms the given input into a desired O/P is typically called a PROCESSEntity that perform these task (transformation) is typically called PROCESSORThe method followed where processor is performing a process is typically called PROCESSING(Process is being processed by processor is PROCESSING)Role of Flags : 2 flags are affected when we go for A – B and they are Z (Zero) and B (Borrow). Z B 0 0 A>B 0 1 A<B 1 0 A=B 1 1 X Z . B + Z . B = S1 Z . B = S2Krishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 6. =x+zyRole of Register : Pentium processor contains only 4 register (Register is nothing but a scratch pad memory) x = y + z According to programming language: MOV R0 , y MOV R1 , z ADD R0 , R1 MOV x , R0L Value R Value Translated by CompilerThis is Parse Tree Or Syntax Tree Note : Accumulator is represented by ( R0 / A ) ( Most General Purpose Register )Krishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 7. Role of Special Purpose Register (SPR):Program Counter / Instruction Counter( It holds address of next instruction to be executed )101100PC101Instruction RegisterNext Instruction’s address is in PC now, instruction at that address is read out and put it in Instruction Register. (Click any where to move)This all process is maintained by Operating SystemStack Pointer ( It can not contain address of any empty location and when it not point to any thing than it contain NULL )Krishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 8. Role of Instruction Register (IR):100guatda.com/cmx.p100...1. Fetching of Instruction2. Decoding of Instruction ( What to do ? )3. Fetching of Data ( if any )4. Execution5 Stores ResultMachine OperationsMachine Operation (M.O.) + (M.O.) + (M.O.) + (M.O.) + . . . = Macro Operation(Micro Operation) ( 1 Instruction Execution )Krishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 9. Instruction and Addressing Mode :ADD A , BOperandOperationClassification Zero Addressing InstructionOne Addressing InstructionTwo Addressing InstructionThree Addressing InstructionZero Register Processor (C.P.U) OR Stack Oriented Computer OR Zero Register Organised C.P.UNot a single GPR is available not even ACCSingle Register Processor Only one Register ACCGeneral Register Organisation More than one register ( ACC + many other register ) Krishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 10. Given Equation : X = ( A * B ) + ( C * D ) 3 Address Instruction MUL R1 , A B MUL R2 , C DADD X , R1 R2MUL A , BMUL C , DADD A , CMOV X , AIn this case we will loose value of A and C therefore not feasible2 Address Instruction MOV R1 , AMOV R1 , BMOV R2 , CMOV R2 , DMOV R1 , R2MOV X , R11 Address Instruction LOAD A ( R0 A )MUL B ( R0 R0 * B )STORE T1LOAD CMUL DADD T1STORE XNote : Implicit operand is ACC / A / R0Krishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 11. 0 Address Instruction PUSH APUSH DDCAA * BPUSH BMUL BC * DAA * BMUL ADDA * B(A*B) + (C*D)PUSH CSTORE XC(A*B) + (C*D)(Calculated)A * BX(in Memory)Krishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 12. TYPEOPERATORDESTINATION / SOURCE 1SOURCE 200 ADD / AND01 SUB / OR10 MUL / XOR11 DIV / NOTInstruction Construction :0 ADD1 SUB00 R001 R110 R211 M OPERATOR DESTINATION / SOURCE 1 SOURCE 21225 bits000 R0 001 R1010 R2. .. .. .111 R70 ARITHEMATIC1 LOGICALKrishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 13. RegisterOperandInput OutputOperandMemoryOperandAddressing Mode :( How you are getting data )InstructionOperand OR OperatorDirectIndirectImmediateRegister-Register IndirectRegister-Memory IndirectMemory-Memory IndirectMemory-Register IndirectKrishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 14. 1. ADD[6] Direct Pointer (The address of operand is available in instruction (ORIGINAL WORKING)) At location 6 (0110) , we are having address 9 (1001) of operand (1001011101).2. Add 6 Immediate (Data is part of instruction , data is not in any register or memory) Here, data is available is Instruction, 6 (0110) is itself is dataIADD[6] Indirect (Pointer) At location 6 (0110) , we are having address 9 (1001), of memory location which is having address of operand (1001011101).It means it is concept of pointer to pointer0110100110011001011101011010011001110011001001011101Krishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 15. Implied Mode : ( operand is at CPU’s register ) CMA Compliment ACC. STC Set CarryImmediate Mode : ( data is part of Instruction ) ADD 6 Add 6 to AccumulatorRegister Mode : ( Operand is available in GPR ) ADD B A A + B ADD A , B A A + B ADD R1 R0 R0 + R1Register Indirect Mode : IADD B A A + [M]B the content of Memory M whose address is given by register B must be Added to AKrishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 16. Memory4096 X 16PC ( Program Counter )1 2 3 . . . . . .16MAR1 2 3 . . . 121 2 31IOPRMBR11 2 3 . . . . . .16EAC1 2 3 . . . . . .16Krishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 17. ADIC BUSCPUCPUVIDEOBUSFSBDVDHOST PORTMAINMEMORYNORTH BRIDGEAGPPORTAGP POINTMONITORLOCAL VIDEO MEMORYPCI SLOTPCI BUSIDESOUTHBRIDGESCSIETHERNETUSBIRCHDDCDROMINTERRUPTIOAPICISA BUSSUPERI/OISASLOTFDDBIOSKBRPINTERSOUNDCHIPMOUSECOM 1COM 2BUSESKrishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 18. 1I/OPROCESSORMEMORYCONTROL2O/PPRIMITIVE BUS ARCHITECTUREThe drawback of this technique is that a double side bus is neededKrishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 19. BACKPLANE BUSPROCESSORI/OI/OI/OMEMORYSHARED BUS ARCHITECTUREDifferent i/o has different data transmission protocoland also having different speed (mismatch) for that, and this is all burden taken care by one deviceShared Bustypically called Backplane BusKrishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 20. Processor Memory Bus(PMB)ProcessorMemoryBusAdaptorBusAdaptorBusAdaptorI/O BusI/O BusI/O BusThe previously said bus system is also having disadvantage of CPU Overheads,to remove this we have two type of Level Architecture : 1. 2 Leveled Architecture 2. 3 Leveled Architecture 2 Leveled ArchitectureNote : Conflicts and Mismatch can be taken care by Bus Adaptor now this not burden for CPUKrishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 21. Processor Memory Bus(PMB)ProcessorMemoryMBABABackplane BusBA3 Leveled ArchitectureNote : PMB is not directly connected to I/O, rather connected to MBAKrishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 22. TransferVideo camera To PCProprietaryand rest all are FreeKrishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 23. SUDUValid DataDataStrobet3t4t2t1BUS TRANSFER : Strobe MethodHandshake MethodStrobe Method : (source initiated)Block DiagramTiming DiagramKrishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 24. SUDUValid DataDataStrobeStrobe Method : (destination initiated)Block DiagramTiming DiagramKrishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 25. SUDUData BusDAVDAC2. Handshaking Method : ( Source Initiated )Block DiagramSUDUDACDAV 0101Data ValidData AcceptKrishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.comClick for Every Action
- 26. Place Data on BUSEnable DAVAccept DataEnable DACDisable DAVDisable DAVTiming DiagramValid DataDataDAVDACKrishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 27. 2. Handshaking Method : ( Destination Initiated )Block DiagramSUDUData BusDAVRFDSUDUDACDAV 0011Data ValidData AcceptReady to Accept DataClick for Every ActionKrishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 28. Ready to accept DataEnable DACPlace Data on BUSEnable DAVAccept Data from Enable DACDisable DAVTiming DiagramDataValid DataKrishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 29. Bus Scheduling :Daisy Chaining PollingIndependentDaisy ChainingBus ControlUnit(BCU)U1U2UnBus Grant. . .Bus RequestBus BusyBUSKrishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 30. Case 1: U1 is requesting for BUSNote: (Sequential processing)Therefore Un have lowest priority and U1 have highest priority.If U1 leave then only other gets the chance.(as shown in diagram)Case 2: U2 is requesting for BUS...Case 3: Un is requesting for BUSU1 grab the BusBus ControlUnit(BCU)U1U2UnBus Grant. . .Bus RequestBus BusyBUSKrishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 31. Polling111000001. . .U1U2UnBus ControlUnit(BCU)Poll countBRBB8 devices : 3 poll count16 devices : 4 poll countKrishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 32. IndependentU1U2UnBus ControlUnit(BCU). . .Poll countKrishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 33. STARTA=0, QN-1=0M=MULTIPLECANDQ=MULTIPLIERCOUNT =N=10=01Q0QN-1=11=00A=A+MA=A-MArithmetic Shift RightA Q QN-1 COUNT=NNoCOUNT =0?YesSTOPBooth Algorithm :(Using 2’s compliment)Krishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 34. Multiplication Algorithm :(Using Signed Magnitude)STARTBsMULTIPICAND BMULTIPLIER QAs = Qs + BsQs = Qs + BsA = 0 , E = 0SC = n - 1AsQsEAQQN=1QN-1=?=0EA=A+BSHR EA QSC=SC-1Not 0SC=?=1STOPKrishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 35. Division Algorithm :Basic Steps:“A trial division” is made by subtracting the y register from Accumulator after the subtraction one of the following is executed 1. if Result is – ve the divisor will not go so a ZERO is placed in rightmost bit of the B register and Accumulator is restored. The combined B register and Accumulator are shifted Left. 2. if Result of subtraction is + ve or Zero, then the trail division is succeeded. The Accumulator and B register both are shifted left and then 1 is placed in the right most bit of B. Krishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com
- 36. CBest of LuckKrishna Kumar Bohra (KKB), MCA LMCSTwww.selectall.wordpress.com