Computer Organisation (DFT1113)
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1) Cache memory is RAM that can be accessed more quickly than regular RAM by the microprocessor. It stores frequently used data from main memory to enable faster access. 2) Cache memory is organized into multiple levels based on their closeness to the microprocessor core. Level 1 (L1) cache is closest while level 2 (L2) cache and main memory are farther. 3) Direct memory access (DMA) allows certain hardware systems to access memory independently of the CPU. This avoids occupying the CPU during lengthy input/output operations.
Computer Organisation (DFT1113)
- 1. Nama Ahli Kumpulan : 1) Siti Soleha Binti Mazlan 2) Nurul Fatihah Binti Mat Hussain 3) Nurfaten Afifi Binti Shahruddin Kelas : DIP1-S2 Pensyarah : Pn. Siti Nasrah Binti Mukhtar
- 3. DEFINITION Cache memory is random access memory (RAM) that a computer microprocessor can access more quickly than it can access regular RAM. As the microprocessor processes data, it looks first in the cache memory and if it finds the data there (from a previous reading of data), it does not have to do the more time-consuming reading of data from larger memory. Cache memory is sometimes described in levels of closeness and accessibility to the microprocessor. An L1 cache is on the same chip as the microprocessor. (For example, the PowerPC 601 processor has a 32 kilobyte level-1 cache built into its chip.) L2 is usually a separate static RAM (SRAM) chip. The main RAM is usually a dynamic RAM (DRAM) chip. In addition to cache memory, one can think of RAM itself as a cache of memory for hard disk storage since all of RAM's contents come from the hard disk initially when you turn your computer on and load the operating system (you are loading it into RAM) and later as you start new applications and access new data. RAM can also contain a special area called a disk cache that contains the data most recently read in from the hard disk. RELATED GLOSSARY TERMS: server-side flash, nonvolatile storage (NVS), solid-state storage, solid-state drive (SSD), resistive RAM (RRAM), nonvolatile memory, flash memory , P/E cycle, multi-level cell (MLC) flash.
- 4. Direct Mapping Remember that direct mapping assigned each memory block to a specific line in the cache. If a line is all ready taken up by a memory block when a new block needs to be loaded, the old block is trashed.
- 5. Full Associative Mapping In full associative, any block can go into any line of the cache. This means that the word id bits are used to identify which word in the block is needed, but the tag becomes all of the remaining bits.
- 7. To allow model variable values to be used as values in a module, you must define module variables as either module inputs or module outputs. A module input is a variable in the module (a stock, a flow, or a converter) that contains information that the module needs in order to run. Although you can explicitly define a variable as a module input, you are not required to, when you assign a variable as a module input (by using the Assign Input To command), that variable is automatically made a module input. A module output is a variable in the module that contains information generated by the module and that can supply a value to other connected entities or modules. Variables directly connected into a module (via a connector from the variable to the module) can be assigned to a module input in the connected module without explicitly defining them as outputs. These variables are providing data into the connected module. On the other hand, variables that are providing data out of the module (into the model that contains the module, or into another module) must be explicitly defined as outputs.
- 12. Asynchronous Serial Transfer The transfer of data between two units in parallel or serial. in parallel data transmission, total message is transmitted at the same time. In serial data transmission, each bit in the message is sent in sequence one at a time. In asynchronous transmission, binary information is sent only when it is available and the line remains idle when there is no information to be transmitted. Asynchronous serial transmission is character oriented. Each character transmitter consists of a start bit, character bits, and stop bits. The first bit is called the start bit. It is always a 0 and is used to indicate the beginning of a character. The last bit called the stop bit is always 1.
- 13. 1.Programmed I/O Mode:- In programmed I/O mode data are exchanged between the processor and the I/O module. When a processor is executing a program and encounters an instruction relating to I/O, it executes that instruction by issuing a command to that appropriate I/O module. With programmed I/O the I/O module will perform the requested action and then set the appropriate bit in the I/O status register .
- 14. • the programmed I/O method, the CPU stays in a program loop until the I/O unit indicates that it is ready for data transfer. This is a time-consuming process since it keeps the processor busy needlessly. • can be avoided by using an interrupt facility and special commands to inform the interface to issue an interrupt request signal when the data are available from the device. • the meantime the CPU can proceed to execute another program. The interface meanwhile keeps monitoring the device. When the interface determines that the device is ready for data transfer, it generates an interrupt request to the computer. • Upon detecting the external interrupt signal, the CPU momentarily stops the task it is processing, branches to a service program to process the I/O transfer, and then returns to the task it was originally performing. Example of Interrupt initiated I/O: • Vectored interrupt • Non vectored interrupt 1. Vectored interrupt : In vectored interrupt, the source that interrupts supplies the branch information to the computer. This information is called the interrupt vector. 2. Non vectored interrupt In a non vectored interrupt, the branch address is assigned to a fixed location in memory.
- 15. Direct memory access (DMA) is a feature of computers that allows certain hardware subsystems within the computer to access system memory independently of the central processing unit (CPU). Without DMA, when the CPU is using programmed input/output, it is typically fully occupied for the entire duration of the read or write operation, and is thus unavailable to perform other work. With DMA, the CPU initiates the transfer, does other operations while the transfer is in progress, and receives an interrupt from the DMA controller when the operation is done. This feature is useful any time the CPU cannot keep up with the rate of data transfer, or where the CPU needs to perform useful work while waiting for a relatively slow I/O data transfer. Many hardware systems use DMA, including disk drive controllers, graphics cards, network cards and sound cards. DMA is also used for intra-chip data transfer in multi-core processors. Computers that have DMA channels can transfer data to and from devices with much less CPU overhead than computers without DMA channels. Similarly, a processing element inside a multi-core processor can transfer data to and from its local memory without occupying its processor time, allowing computation and data transfer to proceed in parallel. DMA can also be used for "memory to memory" copying or moving of data within memory. DMA can offload expensive memory operations, such as large copies or scatter-gather operations, from the CPU to a dedicated DMA engine. An implementation example is the I/O Acceleration Technology.
- 16. • http://en.wikipedia.org/wiki/Direct_memory_access • http://aspersky.wordpress.com/2011/05/16/input- and-output-organisation/ • http://www.ustudy.in/node/8176 • http://csciwww.etsu.edu/tarnoff/labs4717/x86_sim/di rect.html