![❏ Instruction Cycle
D'7IT3: AR ¬ M[AR]
D'7I'T3: Nothing
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.
= 0 (Memory-reference)](https://image.slidesharecdn.com/coaunit2-240410132503-1438b8ef/85/Computer-Organization-Architecture-COA-Unit-2-27-320.jpg)
![❏ FLOWCHART FOR INTERRUPT CYCLE
R = Interrupt
f/f
- The interrupt cycle is a HW implementation of a branch
and save return address operation.
- At the beginning of the next instruction cycle, the
instruction that is read from memory is in address 1.
- At memory address 1, the programmer must store a branch instruction
that sends the control to an interrupt service routine
- The instruction that returns the control to the original
I/O and Interrupt
Store return address
R =1
=0
in location 0
M[0] ← PC
Branch to location 1
PC ←
1
IEN ←
0
R ← 0
Interrupt cycle
Instruction cycle
Fetch and decode
instructions
IEN
FGI
FGO
Execute
instructions
R ←
1
=1
=1
=1
=0
=0
=0](https://image.slidesharecdn.com/coaunit2-240410132503-1438b8ef/85/Computer-Organization-Architecture-COA-Unit-2-39-320.jpg)
![❏ REGISTER TRANSFER OPERATIONS IN INTERRUPT
CYCLE
Register Transfer Statements for Interrupt Cycle
- R F/F ← 1 if IEN (FGI + FGO)T0′T1′T2′
⇔ T0′T1′T2′ (IEN)(FGI + FGO): R ← 1
- The fetch and decode phases of the instruction cycle
must be modified 🡺Replace T0, T1, T2 with R'T0, R'T1,
R'T2
- The interrupt cycle :
RT0: AR ← 0, TR ← PC
RT1: M[AR] ← TR, PC ← 0
After interrupt cycle
0 BUN 1120
0
1
PC = 256
255
1 BUN 0
Before interrupt
Mai
n
Program
1120
I/O
Program
0
BUN
1120
0
PC = 1
256
255
1 BUN 0
Memory
Mai
n
Program
1120
I/O
Program
256
I/O and Interrupt](https://image.slidesharecdn.com/coaunit2-240410132503-1438b8ef/85/Computer-Organization-Architecture-COA-Unit-2-40-320.jpg)
Computer Organization & Architecture (COA) Unit 2
- 1. Laxmi Institute of Technology, Sarigam Academic Year - 2023-2024 COMPUTER SCIENCE AND ENGINEERING DEPARTMENT CLASS: B.E, 2nd Year, Semester - 4th Faculty Name: Ms. Sanchi Upadhyay CSE Department LIT, Sarigam Subject: Computer Organization & Architecture Subject Code: 3140707 Semester: IV
- 2. Subject: Computer Organization & Architecture Subject Code: 3140707 Semester: IV Teaching and Examination Scheme:
- 3. Subject Overview Sr. No. Units 1 Computer Data Representation & Register Transfer and Micro-operations 2 Basic Computer Organization and Design 3 Assembly Language Programming 4 Microprogrammed Control Organization 5 Central Processing Unit 6 Pipeline And Vector Processing 7 Computer Arithmetic 8 Input-Output Organization 9 Memory Organization 10 Multiprocessors
- 4. ❏ Topics to be covered ➔ Instruction codes ➔ Computer registers ➔ Computer instructions ➔ Timing and Control ➔ Instruction cycle ➔ Memory-Reference Instructions ➔ Input-output and interrupt ➔ Complete computer description ➔ Design of Basic computer ➔ Design of Accumulator Unit
- 5. ❏ ALU (Adder & Logic Circuits) Design of AC Logic
- 6. ❏ INTRODUCTION • Every different processor has its own design (different registers, buses, micro-operations, machine instructions, etc) • Modern processor is a very complex device • It contains – Many registers – Multiple arithmetic units, for both integer and floating point calculations – The ability to pipeline several consecutive instructions to speed execution – Etc. • However, to understand how processors work, use a simplified processor model • This is similar to what real processors were like ~25 years ago
- 7. ❏ THE BASIC COMPUTER • The Basic Computer has two components, a processor and memory • The memory has 4096 words in it – 4096 = 212, so it takes 12 bits to select a word in memory • Each word is 16 bits long CPU RAM 0 4095 0 15
- 8. ❏ INSTRUCTIONS Instruction codes • Program – A sequence of (machine) instructions • (Machine) Instruction – A group of bits that tell the computer to perform a specific operation (a sequence of micro-operation) • The instructions of a program, along with any needed data are stored in memory • The CPU reads the next instruction from memory • It is placed in an Instruction Register (IR) • Control circuitry in control unit then translates the instruction into the sequence of microoperations necessary to implement it
- 9. ❏ INSTRUCTION FORMAT Instruction codes • A computer instruction is often divided into two parts – An opcode (Operation Code) that specifies the operation for that instruction – An address that specifies the registers and/or locations in memory to use for that operation • In the Basic Computer, since the memory contains 4096 (= 212) words, we needs 12 bit to specify which memory address this instruction will use • In the Basic Computer, bit 15 of the instruction specifies the addressing mode (0: direct addressing, 1: indirect addressing) • Since the memory words, and hence the instructions, are 16 bits long, that leaves 3 bits for the instruction’s opcode
- 10. ❏ ADDRESSING MODES Instruction codes • The address field of an instruction can represent either – Direct address: the address in memory of the data to use (the address of the operand), or – Indirect address: the address in memory of the address in memory of the data to use 0 ADD 457 22 Operand 457 1 ADD 300 35 1350 300 Operand 1350 + AC + AC Direct addressing Indirect addressing
- 11. ❏ PROCESSOR REGISTERS Instruction codes • A processor has many registers to hold instructions, addresses, data, etc • The processor has a register, the Program Counter (PC) that holds the memory address of the next instruction – Since the memory in the Basic Computer only has 4096 locations, the PC only needs 12 bits • In a direct or indirect addressing, the processor needs to keep track of what locations in memory it is addressing: The Address Register (AR) is used for this – The AR is a 12 bit register in the Basic Computer • When an operand is found, using either direct or indirect addressing, it is placed in the Data Register (DR). The processor then uses this value as data for its operation • The Basic Computer has a single general purpose register – the Accumulator (AC)
- 12. ❏ PROCESSOR REGISTERS Instruction codes • The significance of a general purpose register is that it can be used for loading operands and storing results – e.g. load AC with the contents of a specific memory location; store the contents of AC into a specified memory location • Often a processor will need a scratch register to store intermediate results or other temporary data; in the Basic Computer this is the Temporary Register (TR) • The Basic Computer uses a very simple model of input/output (I/O) operations – Input devices are considered to send 8 bits of character data to the processor – The processor can send 8 bits of character data to output devices • The Input Register (INPR) holds an 8 bit character gotten from an input device • The Output Register (OUTR) holds an 8 bit character to be send to an output device
- 13. ❏ BASIC COMPUTER REGISTERS List of Reg DR 16 Data Register Holds memory AR 12 Address Register Holds address for m AC 16 Accumulator Process IR 16 Instruction Register Holds instruction co PC 12 Program Counter Holds address of in TR 16 Temporary Register Holds temporary dat INPR 8 Input Register Holds input characte OUTR 8 Output Register Holds output charac Registers Registers in the Basic Computer 1 1 0 PC 15 0 IR 15 0 TR 7 0 OUTR 15 0 DR 15 0 AC 1 1 0 AR INPR 0 7 Memory 4096 x 16 CPU
- 14. ❏ COMMON BUS SYSTEM Registers • The registers in the Basic Computer are connected using a bus • This gives a savings in circuitry over complete connections between registers
- 15. Registers ❏ COMMON BUS SYSTEM
- 16. ❏ COMMON BUS SYSTEM Registers AR PC DR L I C L I C L I C AC L I C ALU E IR L TR L I C OUTR L INPR Memory 4096 x 16 Address Read Write 16-bit Common Bus 7 1 2 3 4 5 6 S0 S1 S2
- 17. ❏ COMMON BUS SYSTEM Registers • Three control lines, S2, S1, and S0 control which register the bus selects as its input • Either one of the registers will have its load signal activated, or the memory will have its read signal activated – Will determine where the data from the bus gets loaded • The 12-bit registers, AR and PC, have 0’s loaded onto the bus in the high order 4 bit positions • When the 8-bit register OUTR is loaded from the bus, the data comes from the low order 8 bits on the bus 0 0 0 x 0 0 1 AR 0 1 0 PC 0 1 1 DR 1 0 0 AC 1 0 1 IR 1 1 0 TR 1 1 1 Memory S2 S1 S0 Register
- 18. ❏ BASIC COMPUTER INSTRUCTIONS Instructions • Basic Computer Instruction Format Memory-Reference Instructions (OP-code = 000 ~ 110) Register-Reference Instructions (OP-code = 111, I = 0) Input-Output Instructions (OP-code =111, I = 1)
- 19. ❏ BASIC COMPUTER INSTRUCTIONS Instructions
- 20. ❏ INSTRUCTION SET COMPLETENESS • Instruction Types Set of instructions using which user can construct machine language programs to evaluate any computable function. Functional Instructions - Arithmetic, logic, and shift instructions - ADD, CMA, INC, CIR, CIL, AND, CLA (other than ADD/AND?) Transfer Instructions - Data transfers between the main memory and the processor registers - LDA, STA Control Instructions - Program sequencing and control - BUN, BSA, ISZ Input/Output Instructions - Input and output - INP, OUT Instructions
- 21. ❏ CONTROL UNIT Instruction codes • Control unit (CU) of a processor translates from machine instructions to the control signals (for the microoperations) that implement them • Control units are implemented in one of two ways • Hardwired Control – CU is made up of sequential and combinational circuits to generate the control signals • Microprogrammed Control – A control memory on the processor contains microprograms that activate the necessary control signals • We will consider a hardwired implementation of the control unit for the Basic Computer
- 22. ❏ Timing and Control
- 23. ❏ Control Unit ➔ Components of Control unit are 1. Two decoders 2. A sequence counter 3. Control logic gates ➔ An instruction read from memory is placed in the instruction register (IR). ➔ In control unit the IR is divided into three parts: I bit, the operation code (12-14)bit, and bits 0 through 11. ➔ The operation code in bits 12 through 14 are decoded with a 3 x 8 decoder. ➔ Bit-15 of the instruction is transferred to a flip-flop designated by the symbol I. ➔ The eight outputs of the decoder are designated by the symbols D0 through D7. ➔ Bits 0 through 11 are applied to the control logic gates. ➔ The 4‐bit sequence counter can count in binary from 0 through 15. The outputs of counter are decoded into 16 timing signals T0 through T15. ➔ The sequence counter SC can be incremented or cleared synchronously. ➔ Most of the time, the counter is incremented to provide the sequence of timing signals out of 4 X 16 decoder. ➔ Once in awhile, the counter is cleared to 0, causing the next timing signal to be T0.
- 24. ❏ Control Organization ● Control unit (CU) of a processor translates from machine instructions to the control signals (for the microoperations) that implement them. ● Control units are implemented in one of two ways: ● Hardwired Control ○ The control logic is implemented with gates, flips-flops, decoders and other digital circuits. ○ It can be optimized to produce a fast mode of operation. ○ It requires changes in the wiring among the various components if the design has to be modified or changed. ● Microprogrammed Control ○ The control information is stored in a control memory. ○ The control memory is programmed to initiate the required sequence of micro- operations. ○ Any required changes or modifications can be done by updating the microprogram in control memory.
- 25. ❏ Timing Cycle for D3T4: SC ← 0 ● Example: T0, T1, T2, T3, T4, T0, T1, . . . ➔ Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.
- 26. ❏ Instruction Cycle ● In Basic Computer, a machine instruction is executed in the following cycle: 1. Fetch an instruction from memory 2. Decode the instruction and calculate effective address (EA) 3. Read the EA from memory if the instruction has an indirect address (Fetch operand) 4. Execute the instruction ● After an instruction is executed, the cycle starts again at step 1, for the next instruction ● Note: Every different processor has its own (different) instruction cycle ● After step 4, the control goes back to step 1 to fetch, decode and execute the next instruction. ● This process continues unless a HALT instruction is encountered.
- 27. ❏ Instruction Cycle D'7IT3: AR ¬ M[AR] D'7I'T3: Nothing D7I'T3: Execute a register-reference instr. D7IT3: Execute an input-output instr. = 0 (Memory-reference)
- 28. ❏ Memory Reference Instructions ● The effective address of the instruction is in AR and was placed there during timing signal T2 when I = 0, or during timing signal T3 when I = 1. ● Memory cycle is assumed to be short enough to complete in a CPU cycle ● The execution of MR instruction starts with T4
- 29. ❏ Memory Reference Instructions
- 30. ❏ Memory Reference Instructions
- 31. ❏ FLOWCHART FOR MEMORY REFERENCE INSTRUCTIONS
- 32. ❏ REGISTER REFERENCE INSTRUCTIONS
- 33. ❏ INPUT-OUTPUT AND INTERRUPT
- 35. PROGRAM CONTROLLED DATA TRANSFER /* Input */ /* Initially FGI = 0 */ loop: If FGI = 1 goto loop INPR ← new data, FGI ← 1 loop: If FGO = 1 goto loop consume OUTR, FGO ← 1 -- CPU -- -- I/O Device -- loop: If FGI = 0 goto loop AC ← INPR, FGI ← 0 /* Output */ /* Initially FGO = 1 */ loop: If FGO = 0 goto loop OUTR ← AC, FGO ← 0 I/O and Interrupt Start Input FGI=0 AC ← INPR More Character END Start Output FGO ← 1 FGO=1 More Character END consume OUTR yes no yes no FGI=0 FGO=1 yes yes no no
- 36. INPUT-OUTPUT INSTRUCTIONS D7IT3 = p IR(i) = Bi, i = 6, …, 11 p: SC ← 0 Clear SC INP pB11: AC(0-7) ← INPR, FGI ← 0 Input char. to AC OUT pB10: OUTR ← AC(0-7), FGO ← 0 Output char. from AC SKI pB9: if(FGI = 1) then (PC ← PC + 1) Skip on input flag SKO pB8: if(FGO = 1) then (PC ← PC + 1) Skip on output flag ION pB7: IEN ← 1 Interrupt enable on IOF pB6: IEN ← 0 Interrupt enable off CPU Side
- 37. ❏ PROGRAM-CONTROLLED INPUT/OUTPUT • Program-controlled I/O - Continuous CPU involvement I/O takes valuable CPU time - CPU slowed down to I/O speed - Simple - Least hardware I/O and Interrupt Input LOOP SKI DEV BUN LOOP INP DEV Output LDA DATA LOOP SKO DEV BUN LOOP
- 38. ❏ INTERRUPT INITIATED INPUT/OUTPUT - Open communication only when some data has to be passed --> interrupt. - The I/O interface, instead of the CPU, monitors the I/O device. - When the interface founds that the I/O device is ready for data transfer, it generates an interrupt request to the CPU - Upon detecting an interrupt, the CPU stops momentarily the task it is doing, branches to the service routine to process the data transfer, and then returns to the task it was performing. * IEN (Interrupt-enable flip- flop) - can be set and cleared by instructions - when cleared, the computer cannot be interrupted
- 39. ❏ FLOWCHART FOR INTERRUPT CYCLE R = Interrupt f/f - The interrupt cycle is a HW implementation of a branch and save return address operation. - At the beginning of the next instruction cycle, the instruction that is read from memory is in address 1. - At memory address 1, the programmer must store a branch instruction that sends the control to an interrupt service routine - The instruction that returns the control to the original I/O and Interrupt Store return address R =1 =0 in location 0 M[0] ← PC Branch to location 1 PC ← 1 IEN ← 0 R ← 0 Interrupt cycle Instruction cycle Fetch and decode instructions IEN FGI FGO Execute instructions R ← 1 =1 =1 =1 =0 =0 =0
- 40. ❏ REGISTER TRANSFER OPERATIONS IN INTERRUPT CYCLE Register Transfer Statements for Interrupt Cycle - R F/F ← 1 if IEN (FGI + FGO)T0′T1′T2′ ⇔ T0′T1′T2′ (IEN)(FGI + FGO): R ← 1 - The fetch and decode phases of the instruction cycle must be modified 🡺Replace T0, T1, T2 with R'T0, R'T1, R'T2 - The interrupt cycle : RT0: AR ← 0, TR ← PC RT1: M[AR] ← TR, PC ← 0 After interrupt cycle 0 BUN 1120 0 1 PC = 256 255 1 BUN 0 Before interrupt Mai n Program 1120 I/O Program 0 BUN 1120 0 PC = 1 256 255 1 BUN 0 Memory Mai n Program 1120 I/O Program 256 I/O and Interrupt
- 41. ❏ FURTHER QUESTIONS ON INTERRUPT ● How can the CPU recognize the device requesting an interrupt ? ● Since different devices are likely to require different interrupt service routines, how can the CPU obtain the starting address of the appropriate routine in each case ? ● Should any device be allowed to interrupt the CPU while another interrupt is being serviced ? ● How can the situation be handled when two or more interrupt requests occur simultaneously ? I/O and Interrupt
- 42. Description ❏ COMPLETE COMPUTER DESCRIPTION Flowchart of Operations
- 43. ❏ COMPLETE COMPUTER DESCRIPTION Microoperations Description
- 44. Description ❏ COMPLETE COMPUTER DESCRIPTION Microoperations
- 45. ❏ DESIGN OF BASIC COMPUTER(BC) Design of Basic Computer
- 46. ❏ CONTROL OF REGISTERS AND MEMORY Design of Basic Computer
- 47. ❏ CONTROL OF FLAGS Design of Basic Computer
- 48. ❏ CONTROL OF COMMON BUS Design of Basic Computer
- 49. Design of AC Logic
- 50. ❏ CONTROL OF AC REGISTER Gate structures for controlling the LD, INR, and CLR of AC Design of AC Logic
- 51. ❏ Design of Accumulator Logic ● In order to design the logic associated with AC, it is necessary to extract all the statements that change the content of AC.
- 52. ❏ Design of Accumulator Logic Circuit associated with AC Adder and logic circuit Accumulator register (AC) Control gates CL R INR LD Cloc k From DR From INPR 16 16 16 16 8 To bus
- 53. ❏ Design of Accumulator Logic 16 To bus
- 54. ❏ Question asked in GTU examination. 1 Write a detailed note on instruction cycle with neat diagrams. 2 Explain control unit of basic computer and its working with diagram. 3 For the basic computer explain following instructions 1. LDA 2. ADD 3. AND 4. CLA 4 Draw and explain flowchart for interrupt cycle. 5 For the basic computer explain following instructions 1. BUN 2. BSA 3. CIL 4. SZE 6 Explain how Input/Output can be performed using interrupts. 7 State the differences between hardwired control and microprogrammed control. 8 Draw and explain basic computer instruction formats.
- 55. ❏ Question asked in GTU examination. 9 A computer uses a memory unit with 256K words of 32 bits each. A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code, a register code part to specify one of 64 registers, and an address part. 1) How many bits are there in operation code, the register code part, and the address part? 2) Draw the instruction word format and indicate the number of bits in each part. 3) How many bits are there in the data and address inputs of the memory? 10 Differentiate MRI and non-MRI. 11 Explain Direct and Indirect Addressing. 12 Give an example of register transfer of data through accumulator. 13 What is Interrupt? How it is useful for a system? 14 Explain CLA, ISZ, INP instruction. 15 Explain seven register common bus system.
- 56. ❏ Question asked in GTU examination. 16 Explain with clear diagram, how data can be input to the computer using INP instruction. 17 What is a Program Counter? 18 What is an Accumulator? 19 What is an Instruction Register? 20 What do you understand by Memory Address? 21 What is a Carry Flag? 22 Explain Instruction Fetch. 23 Explain Instruction Decode. 24 Enlist major components of CPU. 25 Effective address.
- 57. Thank You!