I/O system in intel 80386 microcomputer architecture

Microcomputer Architecture
Intel 80386
Input/Output System
Submitted by,
M. Kavitha M.Sc.,
N.S.College Arts & Science

Input/Output System:
* The 80386 input/output system is the same as
that found in any Intel 8086 family microprocessor-based
system.
* There are 64K different bytes of I/O space
available if isolated I/O is implemented the I/O port
address appears on address bus connection A15-A2 with
BE3–BE0 used to select a byte, word, or double word of
I/O data.
* If memory mapped I/O is implemented, then the
number of I/O locations can be any amount up to 4G bytes.

Bank 3 Bank 2 Bank 1 Bank 0
FFFF FFFC
0003 0000
Fig 1: The 80386 I/O map four bank address 64K
different location 0000H to FFFFH

* The only new feature that was added to the 80386
with respect to I/O is the I/O privilege information added to
the tail end of the TSS when the 80386 is operated in
protected mode.
* The section on memory management, an I/O
location can be blocked or inhibited in the protected mode.
* If the blocked I/O location is addressed, an interrupt
(type 13, general fault) is generated.
* This scheme is added so that I/O access can be
prohibited in a multiuser environment.
* Blocking is an extension of the protected mode
operation, as are privilege levels.

Memory and I/0 Control Signals:
* The memory and I/O are controlled with separate
signals. The M/IO signal indicates whether the data transfer is
between the microprocessor and the memory (M/IO=1 ) or I/O
(M/IO=0).
* M/IO the memory and I/O systems must read or write
data. The W/R signal is a logic 0 for a read operation and a
logic 1 for a write operation.
* The ADS signal is used to qualify the M/IO and W/R
control signals.

* There are two control signals are
developed for memory control (MRDC and MWTC)
and two for I/O control (IORC and IOWC).
* There are two type of memory and I/O
Control Signals.
* Timing
* Wait States

Fig 2 : Memory and I/O control signals for the 80386,
80486, and Pentium.

Timing:
* Timing is important for understanding memory
and I/O to the 80386 microprocessor.
* The timing diagram of a non pipelined memory
read cycle. Note that the timing is referenced to the CLK2
input signal and that a bus cycle consists of four clocking
periods.
* Each bus cycle contains two clocking states with
each state T1and T2 containing two clocking periods.
* The 16 MHz version allows memory an access
time of 78 ns before wait states are inserted in this non
pipelined mode of operation.

Wait States Used the non pipeline 80386 signals:
A31–A2 Address bus connections address any of
the 1G × 32 (4G bytes) memory locations found
in the 80386 memory system. The 80386SX
contains a 16-bit data bus in place of the 32-bit
data bus found on the 80386DX, A1 is present on
the 80386SX, and the bank selection signals are
replaced with BHE and BLE. The BHE signal
enables the upper data bus half; the BLE signal
enables the lower data bus half.
D31–D0 Data bus connections transfer data between
the microprocessor and its memory and I/O
system. Note that the 80386SX contains D15–D0.

CLK2 Clock times 2 is driven by a clock signal
that is twice the operating frequency of the
80386. For example, to operate the 80386 at
16MHz, apply a 32 MHz clock to this pin
ADS The address data strobe becomes active
whenever the 80386 has issued a valid
memory or I/O address. This signal is
combined with the W/R signal to generate the
separate read and write signals present in the
earlier 8086–80286 microprocessor-based
systems.

Fig 3 : The non pipelined read timing for the 80386
microprocessor.

Timing Used the pipeline 80386 Signals :
A31–A2 Address bus connections address any of the
1G × 32 (4G bytes) memory locations found in
the 80386 memory system. The 80386SX
contains a 16-bit data bus in place of the 32-bit
data bus found on the 80386DX, A1 is present
on the 80386SX, and the bank selection signals
are replaced with BHE and BLE. The BHE
signal enables the upper data bus half; BLE
signal enables the lower data bus half.
D31–D0 Data bus connections transfer data between
the microprocessor and its memory and I/O
system. Note that the 80386SX contains D15-D0.

CLK2 Clock times 2 is driven by a clock signal
that is twice the operating frequency of
the 80386. For example, to operate the
80386 at 16MHz, apply a 32 MHz clock to
this pin.
ADS The address data strobe becomes active
whenever the 80386 has issued a valid
memory or I/O address. This signal is
combined with the W/R signal to generate
the separate read and write signals present
in the earlier 8086–80286 microprocessor-
base systems.
NA Next Address causes the 80386 to output the
address of the next instruction or data in the
current bus cycle. This pin often used for
pipelining the address.

Fig 4 : The pipelined read timing for the 80386
microprocessor.

Wait States:
* Wait states are needed if memory access times are
long compared with the time allowed by the 80386 for
memory access.
* A non pipelined 33 MHz system, memory access
time is only 46 ns. A few DRAM memories exist that have
an access time of 46 ns.
* This means that often wait states must be
introduced to access the DRAM (one wait for 60 ns
DRAM) or an EPROM that has an access time of 100 ns
(two waits).
* Wait state is built into a motherboard and cannot be
removed.

* The READY input controls or not wait states are
inserted into the timing. The READY input on the
80386 is a dynamic input that must be activated during
each bus cycle.
* The READY signal is sampled at the end of a bus
cycle to determine if the clock cycle is T2 or TW.
* If READY=0 at time, it is the end of the bus cycle
or T2. If READY is 1 at the end of a clock cycle, the cycle
is a TW and the microprocessor continues to test
READY,

I/O system in intel 80386 microcomputer architecture

READY Ready controls the number of wait
states inserted into the timing to
lengthen memory accesses.

Fig 5 : A non pipelined 80386 with 0 and 1 wait states.

Fig 6 : Timing that selects 1 wait state for DRAM and 2
waits for EPROM.

I/O system in intel 80386 microcomputer architecture

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