PAI Unit 3 Multitasking in 80386

04/02/20 1
Multitasking
Subject : Processor Architecture & Interfacing
Class : SEIT
Prepared By,
Ms. K. D. Patil, AP
Department of IT, Sanjivani COE, Kopargaon.

04/02/20 2
Multitasking

A task can be a single program or it can be a group of related programs.

A multi-user system also implies multitasking but reverse is not true.

In multitasking operation, 80386 is actually serving only one task/user
for a short time & then moving onto the next task/user & so on.

Each task/user is allotted a time slice (a small fraction of second) .

When the current task/user has used up its time slice, the 80386 saves
all of the current context information & directs towards next task/user.

After serving all tasks/users, 80386 will return to the first task/user ,
pick up where it left off & do as much work as it is able in a time slice.

This technique is known as timesharing.

04/02/20 3
Support Registers and Data
Structures
To provide efficient, protected multitasking, the 80386
employs several special data structures.

The registers and data structures that support
multitasking are:
 Task state segment
 Task state segment descriptor
 Task register
 Task gate descriptor

With these structures the 80386 can rapidly switch
execution from one task to another, saving the context of
the original task so that the task can be restarted later.

04/02/20 4
Task State Segment (TSS)

All the information the processor needs in order to manage a task is
stored in a special type of segment called as task state segment (TSS)

In 80386, a task is any collection of code & data that has a Task State
Segment (TSS) assigned to it.

80386 stores a task’s vital information when the task is not running.

80386 finds all of the information necessary to restart that task when
its turn comes again.

TSS is an area of read/write memory like data segment which is not
accessible to the general user program even at PL0.

The space defined within a TSS is available to 80386 only.

This is it’s private cold storage.

04/02/20 5
Task State
Segment
I/O map base

04/02/20 6

The fields of a TSS belong to two classes:

1. A dynamic set that the processor updates with each
switch from the task. This set includes the fields that
store:
 The general registers (EAX, ECX, EDX, EBX, ESP, EBP, ESI,
EDI). They are stored in the same order in which PUSHAD
instruction would save them onto the stack.
 The segment registers (ES, CS, SS, DS, FS, GS).
 The flags register (EFLAGS). Saving EFLAGS guarantees
that conditional instructions will behave properly when the
task is restarted.
 The instruction pointer (EIP).
 Back Link Field : Keep Track of Task chain. The selector of
the TSS of the previously executing task (updated only when
a return is expected).

04/02/20 7

2. A static set that the processor reads but does
not change. This set includes the fields that
store:
 The selector of the task's LDT.
 The register (PDBR) that contains the base address of the
task's page directory (read only when paging is enabled).
Imply that page Directory can be changed as per Task basis.
 Pointers to the stacks for privilege levels 0-2.
 The T-bit (debug trap bit) which causes the processor to
raise a debug exception when a task switch occurs.
 The I/O map base (I/O permission Bit Map Field) refers to an
additional privilege-related information/function.

04/02/20 8
• I/O permission bit map affects the hardware privilege checking only
for IO instructions like IN, INS, OUT, OUTS, CLI, STI.
• Without I/O permission bit map, a program can execute these I/O
instructions only if CPL is less than or equal to IOPL which is stored in
EFLAGS register.
• When I/O permission bit map is defined for a task, code within that
task has another option to use I/O instructions.
• If the standard I/O permission check fails then 80386 consults the I/O
permission bit map for the particular I/O addresses. If the permission
bit for this I/O address is 0 then the I/O instruction is allowed
otherwise 80386 generates a general protection fault.

04/02/20 9

TSS may reside anywhere in the linear space. The
only case that requires caution is when the TSS spans
a page boundary and the higher-addressed page is
not present. In this case, the processor raises an
exception if it encounters the not-present page while
reading the TSS during a task switch. Such an
exception can be avoided by either of two strategies:
1. By allocating the TSS so that it does not cross a page
boundary.
2. By ensuring that both pages are either both present or both not-
present at the time of a task switch. If both pages are not-present,
then the page-fault handler must make both pages present before
restarting the instruction that caused the task switch.

TSS Descriptor
•
The TSS is defined by a segment descriptor which is
known as TSS descriptor.
•
It appears only in GDT.
04/02/20 10

TSS Descriptor
•
The base address field determines the starting address of
TSS. It must point to physically writable memory. If paging
is enabled in your system, the TSS should be mapped to a
present page of RAM.
•
The limit field determines the size of TSS. As 80386
requires 104 bytes of storage in order to perform a context
save, the limit field must never be less than 00067H. It can
made larger upto 4GB.
•
The DPL field does not imply a privilege level for the TSS
itself. It determines what software can reference the task
defined by this TSS.
04/02/20 11

TSS Descriptor

The B-bit in the type field indicates whether the task is
busy. A type code of 9 indicates a non-busy task; a
type code of 11 indicates a busy task. The B-bit allows
the processor to detect an attempt to switch to a task
that is already busy.

DPL fields of TSS descriptors should be set to zero, so
that only trusted software has the right to perform task
switching.

Other bits are same as data segment descriptor.

The task register (TR) identifies the currently
executing task by pointing to the TSS.
04/02/20 12

Task Register
•
It holds the 16-bit selector. The initial selector must be loaded into TR
which starts the initial task. The selector is changed automatically
whenever the 80386 perform a task switch.
•
TR is used to locate a descriptor in the GDT. The corresponding task
state segment (TSS) descriptor gets automatically read from the global
memory & is loaded into task descriptor cache.
•
This descriptor defines TSS & provides the starting address (BASE)
& the size (LIMIT) of the present segment.
•
Every task has its own TSS which holds the information needed to
initiate the task.
•
TR is always current and self-maintaining. To initialize TR , use the
instruction LTR.
•
On every Task Switch, the processor automatically sets the TS (Task
Switch flag) in register CR0. This bit will never be cleared unless you
do in new Task
04/02/20 13

Task Switching
●
A Task Switch can be initiated by software in any of four cases.
●
The current task executes a JMP or CALL that refers to a TSS
descriptor.
●
The current task executes a JMP or CALL that refers to a task gate.
●
An interrupt or exception vectors to a task gate in the IDT. (An
exception or interrupt causes a task switch when it vectors to a task
gate in the IDT. If it vectors to an interrupt or trap gate in the IDT, a
task switch does not occur.)
●
The current task executes an IRET when the NT flag is set.
●
When 80386 performs Task Switch, no information crosses Task
Boundries. Two Tasks are as seperate as they can be and still run on
same processor. This is necessary
●
To keep one Task’s work seperate from another
●
Tasks can be stopped and started at any time without side effects.
04/02/20 15

Task Switching Operation Steps
1. Checking that the current task is allowed to switch to the designated
task. Data-access privilege rules apply in the case of JMP or CALL
instructions. The rule is
MAX (CPL, RPL) < = TSS DPL or Task Gate DPL
2. Checking that the TSS descriptor of the new task is marked present
and has a valid limit. Any errors up to this point occur in the context of
the outgoing task. Errors are restartable and can be handled in a way
that is transparent to applications procedures.
3. Saving the state of the current task. The processor finds the base
address of the current TSS cached in the task register. It copies the
registers into the current TSS (EAX, ECX, EDX, EBX, ESP, EBP, ESI,
EDI, ES, CS, SS, DS, FS, GS, and the flag register). The EIP field of the
TSS points to the instruction after the one that caused the task switch.
04/02/20 16

Task Switching Operation Steps
4. Loading the task register with the selector of the incoming task's TSS
descriptor, marking the incoming task's TSS descriptor as busy, and
setting the TS (task switched) bit of the MSW. The selector is either the
operand of a control transfer instruction or is taken from a task gate.
5. Loading the incoming task's state from its TSS and resuming
execution. The registers loaded are the LDT register; the flag register;
the general registers EIP, EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI;
the segment registers ES, CS, SS, DS, FS, and GS; and PDBR. Any
errors detected in this step occur in the context of the incoming task. To
an exception handler, it appears that the first instruction of the new task
has not yet executed.
04/02/20 17

Task Gate Descriptor
04/02/20 18

Task Gate Descriptor
●
Like Call Gates, Task Gates are special system descriptor.
●
Available in IDT, LDT
●
Task Gate Descriptor does not define a memory segment but instead
acts as an interface point between user code and a TSS.
●
A task gate descriptor provides an indirect, protected reference to a TSS.
●
The SELECTOR field of a task gate must refer to a TSS descriptor.
The value of the RPL in this selector is not used by the processor.
●
When you use selector to a Task Gate in your code, you are indirectly
referencing a TSS descriptor which uniquely identifies a task.
●
The selector to the task gate can be used in place of a selector to a code
segment in FAR JMP and Far CALL instructions.
●
The DPL field of a task gate controls the right to use the descriptor to
cause a task switch. The current program is privileged enough to invoke
the task gate. The Rule is as follows
Max (CPL, RPL) of selector <= Task Gate DPL04/02/20 19

Need of Task Gate Descriptor
●
A procedure that has access to a task gate has the power to cause a task
switch, just as a procedure that has access to a TSS descriptor.
●
The 80386 has task gates in addition to TSS descriptors to satisfy three
needs:
1. The need for a task to have a single busy bit. Because the busy-bit
is stored in the TSS descriptor, each task should have only one such
descriptor. There may, however, be several task gates that select the
single TSS descriptor.
2. The need to provide selective access to tasks. Task gates fulfill this
need, because they can reside in LDTs and can have a DPL that is
different from the TSS descriptor's DPL. A procedure that does not have
sufficient privilege to use the TSS descriptor in the GDT (which usually
has a DPL of 0) can still switch to another task if it has access to a task
gate for that task in its LDT. With task gates, systems software can limit
the right to cause task switches to specific tasks.04/02/20 20

Need of Task Gate Descriptor
3. The need for an interrupt or exception to cause a task switch.
Task gates may also reside in the IDT, making it possible for interrupts
and exceptions to cause task switching. When interrupt or exception
vectors to an IDT entry that contains a task gate, the 80386 switches to
the indicated task. Thus, all tasks in the system can benefit from the
protection afforded by isolation from interrupt tasks.
04/02/20 21

Task Gate Indirectly identifies a task

Task Switching : Direct to TSS
●
Instead of using Task Gate decriptor as an object of an intersegment
Transfer instruction, You can use a selector of the TSS decriptor.
●
The Rule is as follows
MAX (CPL, RPL) < = TSS DPL
●
Depending upon the form you use, 80386 test either TSS Decriptor or
Task Gate task switching is performed.
●
TSS Descriptor is per task and they appear in GDT, all programs or
Tasks have access to it and cause Task Switching assuming they were
privileged enough.
●
If you define Task Gate for that decriptor and locate them in LDTs, you
are restricting Task Switching privileges to only those Tasks with the
gate in their LDTs as well those that run at PL0.
04/02/20 23

Figure : Task
Switching through
TSS

References
● James Turley, “Advanced 80386 programming
Techniques”, Tata McGraw Hill Edition
● http://www.logix.cz/michal/doc/i386/chp07-
00.htm

PAI Unit 3 Multitasking in 80386

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