Evolution of microprocessors and 80486 Microprocessor.
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The document discusses the evolution of Intel x86 microprocessors from 80186 to 80486. It describes the key features and improvements introduced in each generation, including additional instructions, memory management capabilities, and on-chip cache in 80486. The 80486 is a 32-bit processor compatible with 80386 with enhanced performance due to its highly integrated design and 8KB internal cache. It has the same 4GB memory address space and register set as 80386 but provides faster execution through fewer clock cycles and additional instructions.
Evolution of microprocessors and 80486 Microprocessor.
- 1. Evolution of microprocessors and 80486 Microprocessor.. 1
- 2. Necessity of the x86 family.. To avoid external interfacing,i.e; to provide built in interfacing c Extension of the memory capacity which was prior limited to ph Protecting the data and code. To increase the overall system performance. 2
- 3. 80186.. - Reduced number of chips. - In-built Programmable interrupt controller, DMAC ,Chip select logic,3-Timers. - No need of 8087 math co-processor. - Extension of instruction set. 3
- 4. 80286.. - First processor to incorporate the concept of virtual - Two modes of operation:Real and protected. - MMU(Memory management unit). - Added hardware multi-tasking. - Increased performance. 4
- 5. Limitations of 80286 that lead to 80386 - 80286 has only a 16 bit processor. - Maximum segment size of 80286 is 64 KB. - 80286 cannot be easily switched between real mode and protected mode because resetting was required. - The amount of memory addressable by the 80286 is 16M byte. - To increase the over all system performance. 5
- 6. 80386.. - A 32-bit microprocessor introduced by Intel in 1985. - Logical extension of 286.More highly pipelined. - 32 bit data and address bus. - 4GB physical memory and VM extended to 64TB. - It has 32 bit data bus 32 bit address bus. - The execution of the instructions is highly pipelined and the processor is designed to operate in a multiuser and multitasking. 6
- 7. - 80387 coprocessor is used. - Two modes of operation: Paged mode:Pages of 4KB each can be swapped. Non-paged mode:Similar to 80286. - The processor can operate in two modes: In the real mode physical address space is 1Mbytes and maximum size of segment is 64KB. In the protected mode address space is 4G bytes and maximum size of segment is upto entire physical addressing space. 7
- 8. Register set-80386 8 It included all eight general purpose registers plus the four segment registers. The general purpose registers were 16 bit wide in earlier machines, but in 386 these registers can be extended to 32 bit. Their new names are EAX,EBX,ECX and so on. Two additional 16 bit segment are included FS and GS.
- 9. Memory System of the 80386 1G*8 1G*8 1G*8 1G*8 Bank 0Bank3 Bank 2 Bank1 32 bit The memory bank are accessed via four bank enable signals BE0,BE1,BE2 and BE3. BE0,BE1,BE2 and BE3 are active low signals. 9
- 10. 80486 - Higly integrated device,with 1.2 million transistors - 32 bit microprocessor that is compatible with 80386. - Has inbuilt MMU(memrory management unit),numeric coprocessor compatible with 80387,high speed level 1 8KBcache . 10
- 11. Types of 80486.. - 80486DX:Has inbuilt numeric processor. - 80486SX:Doesn’t contain the numeric processor,hence cheaper. 11
- 12. 80486 features.. - 80486 is the next in Intel’s upward compatible 80x86 architecture. - Only few differences between the 80486 and 80386, but these differences created a significant performance improvement. - 32 bit microprocessor and same register set as 80386. - Few additional instructions were added to its instruction set. - 4 gigabyte addressing space . 12
- 13. Improvements made in 80486 over 80386 - 80486 was powered with a 8KB cache memory. - This improved the speed of 80486 processor to great extent. - Some new 80486 instructions are included to maintain the cache. - It uses four way set associative cache. - 80486 also uses a co-processor similar to 80387 used with 80386. - But this co-processor is integrated on the chip allows it to execute instructions 3 times faster as 386/387 combination. 13
- 14. - The new design of 80486 allows the instruction to execute with fewer clock cycles. - 486 is packed with 168 pin grid array package instead of the 132 pin used for 386 processor. - This additional pin’s made room for the additional signals. - This new design of 80486 allows the instruction to execute with fewer clock cycles. - These small differences made 80486 more powerful processor. 14
- 16. contd. - 168 pin PGA(pin grid array.) - All Vcc and Vss need to be connected to 5.0 with upto 1.2A. - The average supply current is 650 mA for the 33 MHz version. - Intel has also produced a 3.3 V version that requires an average of 500 mA at a triple-clock speed of 100 MHz. 16
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- 21. 80486 Signal Group - The 80486 data bus, address bus, byte enable, ADS#, RDY#, INTR, RESET, NMI, M/IO#, D/C#, W/R#, LOCK#, HOLD, HLDA and BS16# signals function as we described for 80386. - The 80486 requires 1 clock instead of 2 clock required by 80386. - A new signal group on the 486 is the PARITY group DP0-DP3 and PCHK#. - These signals allow the 80486 to implement parity detection / generation for memory reads and memory writes. - During a memory write operation, the 80486 generates an even parity bit for each byte and outputs these bits on the DP0-DP3 lines. 21
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- 23. 23 - These bits will store in a separate parity memory bank. - During a read operation the stored parity bits will be read from the parity memory and applied to the DP0-DP3 pins. - The 80486 checks the parities of the data bytes read and compares them with the DP0-DP3 signals. If a parity error is found, the 80486 asserts the PCHK# signal. - Another new signals group consists of the BURST ready signal BRDY# and BURST last signal BLAST#. These signals are used to control burst-mode memory reads and writes.
- 24. 24 - A normal 80486 memory read operation to read a line into the cache requires 2 clock cycles. However, if a series of reads is being done from successive memory locations, the reads can be done in burst mode with only 1 clock cycle per read. - To start the process the 80486 sends out the first address and asserts the BLAST# signal high. When the external DRAM controller has the first data bus, it asserts the BRDY# signal. - The 80486 reads the data word and outputs the next address. Since the data words are at successive addresses, only the lower address bits need to be changed. If the DRAM controller is operating in the page or the static column modes then it will only have to output a new column address to the DRAM.
- 25. 25 - In this mode the DRAM will be able to output the new data word within 1 clock cycle. - When the processor has read the required number of data words, it asserts the BLAST# signal low to terminate the burst mode. - The final signal we want to discuss here are the bus request output signal BREQ, the back-off input signal BOFF#, the HOLD signal and the hold-acknowledge signal HLDA. - These signals are used to control sharing the local 486 bus by multiple processors ( bus master). - When a master on the bus need to use the bus, it asserts its BERQ signal .
- 26. 26 - An external parity circuit will evaluate requests to use the bus and grant bus use to the highest – priority master. To ask the 486 to release the bus , the bus controller asserts the 486 HOLD input or BOFF# input. - If the HOLD input is asserted, the 486 will finish the current bus cycle, float its buses and assert the HLDA signal. - To prevent another master from taking over the bus during a critical operation, the 486 can assert its LOCK# or PLOCK# signal.
- 27. EFLAG Register Of The 80486 27 - The extended flag register EFLAG is illustrated in the figure. The only new flag bit is the AC alignment check, used to indicate that the microprocessor has accessed a word at an odd address or a double word boundary. - Efficient software and execution require that data be stored at word or doubleword boundaries.
- 28. GENERAL PURPOSE REGISTERS INSTRUCTION POINTER AND FLAG REGISTER SEGMENT REGISTERS CODE SEGMENT DATA SEGMENT CS SS DS ES FS GS EIP EFLAGS IP FLAGS 01631 15 ESP EBP EDI ESI EDX ECX EBX EAX SP BP DI SI DX CX BX AX 01631 15 STACK SEGMENT 28
- 29. CFVM RF 0 NT IOPL OF IF TF SF ZF 0 AF 0 PF 1 0123456789101112131415 DF 16171831 RESERVED FOR INTEL E F L A G FLAGS Flag Register of 80486 AC CF: Carry Flag AF: Auxiliary carry ZF: Zero Flag SF : Sign Flag TF : Trap Flag IE : Interrupt Enable DF : Direct Flag OF : Over Flow IOPL : I/O Privilege Level NT : Nested Task Flag RF : Resume Flag VM : Virtual Mode AC : Alignment Check 29
- 30. 80486 Memory System 30 - The memory system for the 486 is identical to 386 microprocessor. The 486 contains 4G bytes of memory beginning at location 00000000H and ending at FFFFFFFFH. - The major change to the memory system is internal to 486 in the form of 8K byte cache memory, which speeds the execution of instructions and the acquisition of data. - Another addition is the parity checker/ generator built into the 80486 microprocessor. - Parity Checker / Generator : Parity is often used to determine if data are correctly read from a memory location. INTEL has incorporated an internal parity generator / decoder.
- 31. P A R I T Y 1G X 8 ___ BE 3 ___ BE 2 ___ BE 1 ___ BE 0 1G X 8 1G X 81G X 8 P A R I T Y P A R I T Y P A R I T Y DP3 D31- D24 DP2 DP1 DP 0 D23- D16 D15- D8 D7 - D0 31
- 32. 32 - Parity is generated by the 80486 during each write cycle. Parity is generated as even parity and a parity bit is provided for each byte of memory. The parity check bits appear on pins DP0-DP3, which are also parity inputs as well as parity outputs. - These are typically stored in memory during each write cycle and read from memory during each read cycle. - On a read, the microprocessor checks parity and generates a parity check error, if it occurs on the PCHK# pin. A parity error causes no change in processing unless the user applies the PCHK signal to an interrupt input.
- 33. 33 - Interrupts are often used to signal a parity error in DS-based computer systems. This is same as 80386, except the parity bit storage. - If parity is not used, Intel recommends that the DP0 – DP3 pins be pulled up to +5v. - CACHE MEMORY: The cache memory system stores data used by a program and also the instructions of the program. The cache is organised as a 4 way set associative cache with each location containing 16 bytes or 4 doublewords of data. - Control register CR0 is used to control the cache with two new control bits not present in the 80386 microprocessor.
- 34. PEM PE MT SN E W PAMW TCEPG 31 16 15 0 Control Register Zero ( CR0)For The 80486 Microprocessor 34
- 35. 35 - The CD ( cache disable ) , NW ( non-cache write through ) bits are new to the 80486 and are used to control the 8K byte cache. - If the CD bit is a logic 1, all cache operations are inhibited. This setting is only used for debugging software and normally remains cleared. The NW bit is used to inhibit cache write-through operation. As with CD, cache write through is inhibited only for testing. For normal operations CD = 0 and NW = 0. - Because the cache is new to 80486 microprocessor and the cache is filled using burst cycle not present on the 386.
- 36. 80486 Memory Management 36 - The 80486 contains the same memory-management system as the 80386. This includes a paging unit to allow any 4K byte block of physical memory to be assigned to any 4K byte block of linear memory. The only difference between 80386 and 80486 memory-management system is paging. - The 80486 paging system can disabled caching for section of translation memory pages, while the 80386 could not. - If these are compared with 80386 entries, the addition of two new control bits is observed ( PWT and PCD ). - The page write through and page cache disable bits control caching.
- 37. P R W U S P W T P C D ADOO OS BITS PAGE TABLE OR PAGE FRAME Page Directory or Page Table Entry For The 80486 Microprocessor 31 0123456789101112 37
- 38. 38 - The PWT controls how the cache functions for a write operation of the external cache memory. It does not control writing to the internal cache. The logic level of this bit is found on the PWT pin of the 80486 microprocessor. Externally, it can be used to dictate the write through policy of the external caching. - The PCD bit controls the on-chip cache. If the PCD = 0, the on-chip cache is enabled for the current page of memory. - Note that 80386 page table entries place a logic 0 in the PCD bit position, enabling caching. If PCD = 1, the on-chip cache is disable. Caching is disable regard less of condition of KEN#, CD, and NW.
- 39. Cache Test Registers 39 - The 80486 cache test registers are TR3, TR4, TR5. - Cache data register (TR3) is used to access either the cache fill buffer for a write test operation or the cache read buffer for a cache read test operation. - In order to fill or read a cache line ( 128 bits wide ), TR3 must be written or read four times. - The contents of the set select field in TR5 determine which internal cache line is written or read through TR3. The 7 bit test field selects one of the 128 different 16 byte wide cache lines. The entry select bits of TR5 select an entry in the set or the 32 bit location in the read buffer.
- 40. 031 31 31 0 0 ConEntSet select Tag Valid LRU Bits Valid bits 3711 11 10 24 3 Cache test register of the 80486 microprocessor TR 3 40
- 41. GENERAL PURPOSE REGISTERS INSTRUCTION POINTER AND FLAG REGISTER SEGMENT REGISTERS CODE SEGMENT DATA SEGMENT CS SS DS ES FS GS EIP EFLAGS IP FLAGS 01631 15 ESP EBP EDI ESI EDX ECX EBX EAX SP BP DI SI DX CX BX AX 01631 15 STACK SEGMENT 41
- 42. 42 - The control bits in TR5 enable the fill buffer or read buffer operation ( 00 ) - Perform a cache write ( 01 ), Perform a cache read ( 10 ) - Flush the cache ( 11 ). - The cache status register (TR4) hold the cache tag, LRU bits and a valid bit. This register is loaded with the tag and valid bit before a cache a cache write operation and contains the tag, valid bit, LRU bits, and 4 valid bits on a cache test read. - Cache is tested each time that the microprocessor is reset if the AHOLD pin is high for 2 clocks prior to the RESET pin going low. This causes the 486 to completely test itself with a built in self test or BIST.
- 43. 43 - The BIST uses TR3, TR4, TR5 to completely test the internal cache. Its outcome is reported in register EAX. If EAX is a zero, the microprocessor, the coprocessor and cache have passed the self test. - The value of EAX can be tested after reset to determine if an error is detected. In most of the cases we do not directly access the test register unless we wish to perform our own tests on the cache or TLB.
- 44. 80486 architecture. The architecture of the 80486DX is almost identical to the 80386.Added to the 80386 architecture inside the 80486DX is - A math coprocessor and - An 8K-byte level 1 cache memory. The 80486SX is almost identical to an 80386 with an 8K-byte cache, but no numeric coprocessor. 44
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- 46. contd. 80486 has nine functional units.. - Bus interface unit. - Instruction prefetch unit. - Instruction decoding unit. - Control and protection unit. - Execution unit. - Floating-point coprocessor. - Segmentation unit. - Popping unit. - Cache unit. 46
- 47. - The instruction to the decoder decides the instruction in the queue and passes to protection unit. - The execution unit executes a series of micro instruction while executing an instruction. - The segmentation unit computes physical address from logical address. - The paging unit converts linear address to physical address also logical address to physical address conversion is required. 47
- 48. - The paging unit has TLB which holds 32 most recent page transition address. - If TLB contains translation ,page directory and page table are not accessed int he memory,and the translation is obtained directly from the table. - The 80486 has a built in math co-processor . - The cache unit consists of an 8KB code and data. - During the system operation cache memory contains recently used information. 48
- 50. The Pentium Processor 50 - Upward compatibility has been maintained. - It can run all programs written for any 80x86 line, but does so at a double the speed of fastest 80486. - Pentium is mixture of both CISC and RISC technologies. - All the prior 80x86 processor are considered as CISC processor. - The addition of RISC aspects lead to additional performance improvement.
- 51. B3B7 B6 B5 B4 B2 B1 B0 BE0BE7 BE6 BE5 BE4 BE3 BE2 BE1 Memory System of Pentium 64 bit 51
- 52. Improvements of Pentium over 80x86 52 - Separate 8KB data and instruction cache memory. - Dual Integer pipelines are present but only single integer pip - Branch Prediction Logic.
- 53. Cache Memory 53 - The Pentium contains two 8K-byte cache. - An 8 byte instruction cache, which stores the instruction. - An 8 byte data cache, stores the data used by the instructions. - In the 80486 with unified cache, a program that was data intensive quickly fills the cache, allowing less room for instructions. - In Pentium this cannot occur because of the separate instruction cache.
- 54. PIPELINING 54 - It is a technique used to enable one instruction to complete with each clock cycle. - In Pentium there are two instruction pipelines, the U pipeline and V pipeline. - These pipelines are responsible for executing 80x86 instructions. - During Execution the U and V pipelines are capable of executing two integer instructions at the same time and one floating point instructions.
- 55. I1 I1 I1 I2 I2 I2 I3 I3 I3 I1 I2 I3 I4 I5 I1 I2 I3 I4 I1 I2 I3 Clock Cycle 1 2 3 4 5 6 7 8 9 F D E F D E F D E F D E Clock Cycle 1 2 3 4 5 55 Pipelining
- 56. 56 - On a non pipelined machine 9 clock cycles are needed for the individual fetch, decode and execute cycle. - On a pipelined machine fetch, decode and execute operations are performed in parallel only 5 cycles are needed to execute the same three instructions. - The First instructions needed 3 cycles to complete. - Additional instructions complete at rate of 1 per cycle.
- 57. 57 - The Instruction pipelines are five-stage pipelines and capable of independent operations. - The Five-Stages are, - PF – PreFetch - D1 – Instruction Decode - D2 – Address Generate - EX - Execute Cache and ALU Access. - WB – Write Back - The U pipeline can execute any processor instruction where as V pipeline only execute Simple Instruction.
- 58. Branch Prediction Logic 58 - The purpose of branch prediction logic is to reduce the time required for a branch caused by internal delays. - The microprocessor begins pre-fetch instruction at the branch address. - The instructions are loaded into the instruction cache. - When the branch occurs, the instruction are present and allow the branch to execute in one clock period. - If the branch prediction logic errs, the branch requires an extra three clock cycles.
- 59. Speed of Processors 59 The 80286 - 25 MHz The 80386 - 40MHz The 80486 - 60 MHz The Pentium -90 MHz
- 60. Thank you 60