PAI Unit 2 Segmentation in 80386 microprocessor

Segmentation in 80386
Subject : Processor Architecture & Interfacing
Class : SEIT
Prepared By
Ms. K. D. Patil, AP
Department of IT, Sanjivani COE, Kopargaon.
2020/1/16 Prepared By: Ms. K. D. Patil 1

Types of Address spaces
● Logical / Virtual address: Virtual addresses are used by an application
program. They consist of a 16-bit selector and a 32-bit offset. In the flat
memory model, the selectors are preloaded into segment registers CS, DS,
SS, and ES, which all refer to the same linear address.
● Linear Addresses: Linear addresses are calculated from virtual/logical
addresses by segment translation (Segmentation). The base of the segment
referred to by the selector is added to the virtual offset, giving a 32-bit linear
address. In segmentation, when paging is disabled linear address = physical
address
● Physical Address: Physical Address is nothing but, the address value that
appears on pins of processor during a memory read/memory write
operations. Physical addresses are calculated from linear addresses through
paging. The linear address is used as an index into the Page Table where the
CPU locates the corresponding physical address.

Physical Address Formation in Real
Mode

Physical Address Formation in Real
Mode
● In the real mode, the 80386 can address at the most 1Mbytes of physical memory using
address lines A 0 -A 19 .
● Paging unit is disabled in real addressing mode, and hence the real addresses are the same as
the physical addresses.
● To form a physical memory address, appropriate segment registers contents (16-bits) are
shifted left by four positions and then added to the 16-bit offset address formed using one of
the addressing modes, in the same way as in the 80386 real address mode.
● The segment in 80386 real mode can be read, write or executed, i.e. no protection is available.
● Any fetch or access past the end of the segment limit generate exception 13 in real address
mode.
● The segments in 80386 real mode may be overlapped or non- overlapped.
● The interrupt vector table of 80386 has been allocated 1Kbyte space starting from 00000H to
003FFH.

Address Translation in 80386
● 80386 transforms logical addresses into physical
address two steps:
● Segment translation: a logical address is converted
to a linear address.
● Page translation: a linear address is converted to a
physical address (optional)
● These translations are performed in a way that is not
visible to applications programmers.

Address Translation in 80386

Protected Mode Addressing
● In this mode, the contents of segment registers are used as selectors to
address descriptors which contain the segment limit, base address and
access rights byte of the segment.
● The effective address (offset) is added with segment base address to
calculate linear address. This linear address is further used as physical
address, if the paging unit is disabled, otherwise the paging unit
converts the linear address into physical address.
● The paging unit is a memory management unit enabled only in
protected mode. The paging mechanism allows handling of large
segments of memory in terms of pages of 4Kbyte size.
● The paging unit operates under the control of segmentation unit. The
paging unit if enabled converts linear addresses into physical address,
in protected mode.

Segmentation
● Addressable space of processor is divided into small parcels
called as segments.
● Segmentation is one method of memory management.
● Segmentation provides the basis for protection.
● Segments are used to encapsulate regions of memory which have
common attributes.
● For example, all of the code of a given program could be
contained in a segment, or an operating system table may reside
in a segment.

Segmentation
● Segments can be defined in 8 basic types
– Data segments with or without write permission
– Stack segments with or without write permission
– Executable code segments with or without data read
permission
– Executable code segments with or without privilege
protection

Segmentation
● Segments are
– Areas of memory
– Defined by programmer
– Used for different purposes such as code, data and stack
● Segments are not
– All the same size
– Necessarily paragraph aligned
– Limited to 64KB

Logical to Physical/ Linear Address
Translation

Memory Management Through
Segmentation
● Contents of segment registers (CS, DS, SS, ES, FS,GS) are used as
selectors to address descriptors which contain the segment limit, base
address and access rights byte of the segment.
● The processor must examine the value loaded in segment register. If
TI (Table Indicator) bit is not set, processor uses index portion (bit 3
through 15) of selector as a pointer to GDT to find correct segment
descriptor as well its upper limit can be located through GDTR.
● The processor then concentrates the fragments of base address field in
the segment descriptor and comes up with the base address of
respective segment.
● To this base address, it adds the offset. This is the linear address where
operand actually located.

Segment Selector
● Segment Registers (CD,DS,SS,ES,FS,GS) are called
as segment selectors OR
● Any 16 bit value that you write into segment register
is called as selector because it selects a segment
descriptor from a descriptor table.
● Segment registers selects segment Descriptors

Segment Selector
● There are 3 fields in segment selector
– Index (Descriptor Index) (bit 3 through 15) : This value
selects one of the 8192 descriptors in the descriptor table
(8192*16 bit = 65536 bytes = 64KB long)
– Table Indicator (bit 2) : Indicates which descriptor table
you want to refer
● When TI = 0 , the index portion refers to descriptor in GDT
● When TI = 1 , the index portion refers to descriptor in LDT
– Privilege checking (bit 0 & 1) : Used for privilege
checking by the protection mechanism

Segment Descriptor
● All information about a segment is stored in an 8
byte data structure called a descriptor.
● All of the descriptors in a system are contained in
tables recognized by hardware.
● Exactly one descriptor must be defined for each
segment of memory to be used in running system
● Created by programmer
● Determines a segment’s base address

Segment Descriptor
● Determines
– segment’s use
– segment’s size
– segment’s privilege level
– whether segment has been accessed before
● Defines type of segment
● Defines Segment limit

Segment Descriptor Format

Segment Descriptor
● Base Address Bits
– Lower 24 bits of segment address : 16 through 39
– Upper 8 bits of segment address : 56 through 63
– By internally concatenating the two portions of the base address field,
the processor can determine the linear address at which segment starts.
● Limit Field
– Lower 16 bits : 0 through 15
– Upper 4 bits : 48 through 51
– It is defined as length of segment in bytes minus 1
– The actual segment length is not used. The segment that is 1 byte length
would have limit of 0

Segment Descriptor
● A (Access, Bit 40)
– 80386 automatically sets this bit whenever a memory
reference is made using the segment that this descriptor
defines
● Type (Segment Type, Bit 41 through 43)
– This 3 field indicates the types of segment you are defining,
like code, data and stack
● S (System, Bit 44)
– If this bit is clear, it indicates that it is a system segment
descriptor. If it is clear it is non-system (code,data,stack)
segment descriptor2020/1/16 Prepared By: Ms. K. D. Patil 21

Segment Descriptor
● DPL (Descriptor Privilege Level, bit 45 and 46)
– Indicates the level of privilege associated with the memory
space that the descriptor defines. DPL 0 is most privilege and
DPL3 is least privilege
● P (Present, bit 47)
– If this bit is clear, address range that the descriptor defines is
considered to be temporarily not present in physical memory
● U (User, bit 52)
– Undefined and 80386 ignores this bit

Segment Descriptor
● D (Default size, bit 54)
– When it is cleared, operands within the segment are assumed
to be 32 bits
● G (Granularity, bit 55)
– When it is cleared, 20 bit limit field is assumed to be
measured in units of 1 byte. If it is set, Limit field is units of
4096 bytes

Types of Segment Descriptors

Non-system Segment Descriptors
● The format of descriptor is same , only the access byte rights
changes.
● Type 0: Data segment with read permission
● Type 1: Data segment with read/ write permission
● Type 2,3: Stack segment
● The addressable range of a segment stretches from the base
address to the base address plus limit definition.
● Valid offset ranges from 0 to limit. Any offset greater than limit
are not considered part of the segment and are not addressable.

Expansion Direction

Expansion Direction
● In the stack segment, if the type field defines a stack
(Type 2,3) then the limit field indicates what area of
segment is not addressable.
● In the stack segment, all offsets must be greater than
the limit.
● In case of data segments, all offsets less than or
equal to limit are valid. The first addressable byte is
at offset 0 and the last is at offset 1FFF, making data
segment 2000 bytes (8KB) long

Expansion Direction
● In the stack segment, the first addressable byte is at offset 2000, and
the last is at FFFF. Offset address 0 is not valid.
● In data segment, lower limit is set by base address field of the
descriptor and upper limit is set by limit field.
● For stack segment, the lower limit is set by limit field and upper limit
have 2 choices,
- if D = 0, the upper limit is equal to the base address plus constant value
FFFF (64KB)
- if D = 1, the upper limit is equal to base address plus FFFFFFFF (4GB)
● A stack segment has minimum size when the limit is either FFFF (D =
0) or FFFFFFFF (D=1) producing a null segment with value zero
length.

● Type 4,5,6,7: Defines Executable segments. Here the code exists.
● Read permission is optional for the segments. If read permission
is denied (Type 4), the segment must contain pure code, no
constants are allowed since they cannot read out. Only code
fetching is allowed.
● If read permission is given (type 5), you can embed constants in
the code itself. Writing is never allowed to the executable code
segment.
● The two executable code segments are repeated with the
conforming attribute set (type 6,7). Conforming means these
code segments voluntarily forgo their privilege level protection.

● The format of descriptor is same , only the access
byte rights changes.

System Segment Descriptors

System Segment Descriptors
● LDT Descriptor (Type 2)
– They are Local descriptor tables, present only in GDT.
– They contain information about LDT.
– Can be accessed only at privilege level 0.
● Gate Descriptor (Type 4,5,6,7,C,E,F)
– Allows 80386 to automatically perform the protection check
– Call Gate: Changes privilege level
– Task Gate: Performs a task switch
– Interrupt Gate/ Trap Gate: Used to specify the interrupt service routines
● TSS (Task State Segment) Descriptor (Type 1,3,9, B)
– When one task switches to another task, it stores all necessary information required to
restart the task, where it was left
– TSS stores the state/context of the task (location, size and privilege level) & linkage of
next task

References
● James Turley, "Advanced 80386 Programming
Techniques", McGraw Hill Education.
● Slides shared by Prof. Tushar Kute at the time of
PAI FDP

PAI Unit 2 Segmentation in 80386 microprocessor

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