Correction subcircuits.pdf

g ¡¢£¤¥¦§¨g©©©¨¤nd
Ed.) Homework Solutions: 9/21/2002 1
Chapter 3 Homework Solutions
Problem 3.1-1
Sketch to scale the output characteristics of an enhancement n-channel device if VT = 0.7
volt and ID = 500 µA when VGS = 5 V in saturation. Choose values of VGS = 1, 2, 3, 4,
and 5 V. Assume that the channel modulation parameter is zero.
0.00E+00
1.00E-04
2.00E-04
3.00E-04
4.00E-04
5.00E-04
6.00E-04
0 1 2 3 4 5 6
VGS
IDS
€ !#$ %'()
Sketch to scale the output characteristics of an enhancement p-channel device if VT = -0.7
volt and ID = -500 µA when VGS = -1, -2, -3, -4, and -6 V. Assume that the channel
modulation parameter is zero.
-6.00E-04
-5.00E-04
-4.00E-04
-3.00E-04
-2.00E-04
-1.00E-04
0.00E+00
-6 -5 -4 -3 -2 -1 0
VGS
IDS

01234567890@ABC@DEFG@95HInd
Problem 3.1-3
In Table 3.1-2, why is γP greater than γN for a n-well, CMOS technology?
The expression for γ is:
γ =
2εsi q NSUB
Cox
Because γ is a function of substrate doping, a higher doping results in a larger value for γ.
In general, for an nwell process, the well has a greater doping concentration than the
substrate and therefore devices in the well will have a larger γ.
Problem 3.1-4
A large-signal model for the MOSFET which features symmetry for the drain and source
is given as
iD = K'
W
L !

#
$
%

[(vGS − VTS)2 u(vGS − VTS)] − [(vGD − VTD)2 u(vGD − VTD)]
where u(x) is 1 if x is greater than or equal to zero and 0 if x is less than zero (step
function) and VTX is the threshold voltage evaluated from the gate to X where X is either S
(Source) or D (Drain). Sketch this model in the form of iD versus vDS for a constant value
of vGS (vGS VTS) and identify the saturated and nonsaturated regions. Be sure to extend
this sketch for both positive and negative values of vDS. Repeat the sketch of iD versus
vDS for a constant value of vGD (vGD VTD). Assume that both VTS and VTD are positive.
vGS
constant
vGD
constant vGD-VTD0
vGS-VTS0vGS-VTS0
vGD-VTD0
K'(W/L)(vGS-VTS)2
-K'(W/L)(vGD-VTD)2

qrstuvwxyq‚ƒ„…‚†‡ˆ‰‚v‘nd
iD = K'
W
2L (vGS − VT)2
'
)
*
,1 + λ (vDS − vDS(sat)) , 0 (vGS − VT) ≤ vDS
When vDS = vDS(sat) , this expression agrees with the non-saturation equation at the
point of transition into saturation. Beyond saturation, channel-length modulation is
applied to the difference in vDS and vDS(sat) .
Problem 3.2-1
Using the values of Tables 3.1-1 and 3.2-1, calculate the values of CGB, CGS, and CGD
for a MOS device which has a W of 5 µm and an L of 1 µm for all three regions of
operation.
We will need LD in these calculations. LD can be approximated from the value given for
CGSO in Table 3.2-1.
LD =
220 × 10-12
24.7 × 10-4 ≅ 89 × 10-9
Off
CGB = C2 + 2C5 = Cox(Weff)(Leff) + 2CGBO(Leff)
Weff = 5 µm
Leff = 1 µm - 2×89 nm = 822 × 10-9
CGB = 24.7 × 10-4 × (5× 10-6)( 822 × 10-9) + 2×700 × 10-12×822 × 10-9
CGB = 11.3 × 10-15 F
CGS = C1 ≅ Cox(LD)(Weff) = CGSO(Weff)
CGS = ( 220 × 10-12) ( 5 × 10-6) = 1.1 × 10-15
CGD = C2 ≅ Cox(LD)(Weff) = CGDO(Weff)
CGD = ( 220 × 10-12) ( 5 × 10-6)= 1.1 × 10-15
Saturation
CGB = 2C5 = CGBO (Leff)

’“”•–—˜™de’fghifjklmfe—nond
CGB = 700 × 10-12 (822 × 10-9) = 575 × 10-18
CGS = CGSO(Weff) + 0.67Cox(Weff)(Leff)
CGS = 220 × 10-12 × 5 × 10-6 + 0.67 × 24.7 × 10-4 × 822 × 10-9 × 5 × 10-6
CGS = 7.868 × 10-15
CGD = CGDO(Weff) = 220 × 10-12 × 5 × 10-6 = 1.1 × 10-15
Nonsaturated
CGB = 2C5 = CGBO (Leff)
CGB = CGBO (Leff) = 700 × 10-12 × 822 × 10-9 = 574 × 10-18
CGS = (CGSO + 0.5CoxLeff)Weff
CGS = (220 × 10-12 + 0.5 × 24.7 × 10-4 × 822 × 10-9) × 5 × 10-6 = 6.18 × 10-15
CGD = (CGDO + 0.5CoxLeff)Weff
CGD = (220 × 10-12 + 0.5 × 24.7 × 10-4 × 822 × 10-9) × 5 × 10-6 = 6.18 × 10-15
Problem 3.2-2
Find CBX at VBX = 0 V and 0.75 V of Fig. P3.7 assuming the values of Table 3.2-1 apply
to the MOS device where FC = 0.5 and PB = 1 V. Assume the device is n-channel and
repeat for a p-channel device.
Change problem to read: “|VBX |==== 0 V and 0.75 V (with the junction always reverse
biased)…”
pqrµm
Figure P3.2-2
2.0µm
Polysilicon
Metal
Active Area
sqtµm

uvwxyz{|}~u€‚ƒ„…†~z‡ˆnd
AX = 1.6 × 10-6 × 2.0 × 10-6 = 3.2 × 10-12
PX = 2×1.6 × 10-6 + 2.0 × 2.0 × 10-6 = 7.2 × 10-6
NMOS case:
CBX =
(CJ)(AX)
'
(
)
*
+
,
1 −
-
.
/
0
1
2vBX
PB
MJ +
(CJSW)(PX)
'
(
)
*
+
,
1 −
-
.
/
0
1
2vBX
PB
MJSW
CBX =
(770 × 10-6)( 3.2 × 10-12)
'
(
)
*
+
,
1 −
-
.
/
0
1
20
PB
MJ +
(380 × 10-12)( 7.2 × 10-6)
'
(
)
*
+
,
1 −
-
.
/
0
1
20
PB
MJSW = 5.2 × 10-15
PMOS case:
CBX =
(560 × 10-6)( 3.2 × 10-12)
'
(
)
*
+
,
1 −
-
.
/
0
1
20
PB
MJ +
(350 × 10-12)( 7.2 × 10-6)
'
(
)
*
+
,
1 −
-
.
/
0
1
20
PB
MJSW = 4.31 × 10-15
|vBX | = 0.75 volts reverse biased
NMOS case:
CBX =
(CJ)(AX)
'
(
)
*
+
,
1 −
-
.
/
0
1
2vBX
PB
MJ +
(CJSW)(PX)
'
(
)
*
+
,
1 −
-
.
/
0
1
2vBX
PB
MJSW ,
CBX =
(770 × 10-6)( 3.2 × 10-12)
'
(
)
*
+
,
1 −
-
.
/
0
1
2-0.75
1
0.5
+
(380 × 10-12)( 7.2 × 10-6)
'
(
)
*
+
,
1 −
-
.
/
0
1
2-0.75
1
0.38
CBX =
2.464 × 10-15
1.323
+
2.736 × 10-15
1.237
= 4.07 × 10-15
PMOS case:
CBX =
(560 × 10-6)( 3.2 × 10-12)
'
(
)
*
+
,
1 −
-
.
/
0
1
2-0.75
1
0.5
+
(350 × 10-12)( 7.2 × 10-6)
'
(
)
*
+
,
1 −
-
.
/
0
1
2-0.75
1
0.35
CBX =
1.79 × 10-15
1.323
+
2.52 × 10-15
1.216
= 3.425 × 10-15

‰Š‹ŒŽ‘’‰“”•–“—˜™š“’Ž›œnd
Problem 3.2-3
Calculate the value of CGB, CGS, and CGD for an n-channel device with a length of 1 µm
and a width of 5 µm. Assume VD = 2 V, VG = 2.4 V, and VS = 0.5 V and let VB = 0 V.
Use model parameters from Tables 3.1-1, 3.1-2, and 3.2-1.
LD =
220 × 10-12
24.7 × 10-4 ≅ 89 × 10-9
Leff = L - 2 × LD = 1 × 10-6 − 2 × 89 × 10-9 = 822 × 10-9
VT = VT0 + γ [ ]2|φF| + vSB − 2|φF|
VT = 0.7 + 0.4 [ ]0.7 + 0.5 − 0.7 = 0.803
vGS − vT =2.4 − 0.5 − 0.803 = 1.096 vDS thus saturation region
CGB = CGBO x Leff = 700 × 10-12 × 822 × 10-9 = 0.575 fF
CGS = 220 × 10-12 × 5 × 10-6 + 0.67 × 24.7 × 10-4 × 822 × 10-9 × 5 × 10-6
CGS = 7.868 × 10-15
CGD = CGDO(Weff) = 220 × 10-12 × 5 × 10-6 = 1.1 × 10-15
Problem 3.3-1
Calculate the transfer function vout(s)/vin(s) for the circuit shown in Fig. P3.3-1. The
W/L of M1 is 2µm/0.8µm and the W/L of M2 is 4µm/4µm. Note that this is a small-
signal analysis and the input voltage has a dc value of 2 volts.

žŸ ¡¢£¤¥¦§¨©ª§«¬®§¦¢¯°nd
±²³´µ¶·¸¹¸º»
5 Volts
vIN = 2V(dc) + 1mV(rms)
vout
+
-
W/L = 2/0.8
W/L = 4/4
M1
M2
vIN
= 2V(dc)
+ 1mV(rms)
R
M1
C
M2
±²³´µ¶·¸¹¸º»¼
vout
+
-
½out(s)
vIN (s)
=
1/SCM2
RM1 + 1/SCM2
=
1
SCM2RM1 + 1
VT1 = VT0 + γ [ ]2|φF| + vSB − 2|φF|
VT1 = 0.7 + 0.4 [ ]0.7 + 2.0 − 0.7 = 1.02
RM1 =
1
K'(W/L)M1 (vGS1 − VT1)
= 1.837 kΩ
CM2 = WM2 × LM2 × Cox = 4 × 10-6 × 4 × 10-6 × 24.7 × 10-4 = 39.52 × 10-15
RM1CM2 = 1.837 kΩ × 39.52 × 10-15 = 72.6 × 10-12
vout(s)
vIN (s) ==
1
S
13.77 × 109 + 1
Problem 3.3-2
Design a low-pass filter patterened after the circuit in Fig. P3.3-1 that achieves a -3dB
frequency of 100 KHz.
1
2πRC
= 100,000
There is more than one answer to this problem because there are two free parameters.
Use the resistance from Problem 3.3-1.

¾¿ÀÁÂÃÄÅÆÇ¾ÈÉÊËÈÌÍÎÏÈÇÃÐÑnd
RM1 = 1.837 kΩ
CM2 =
1
2π ×1.837× 103×1 × 105 = 866.4 pF
Choose W = L
CM2 = WM2 × LM2 × Cox = W
2
M2 × 24.7 × 10-4 = 866.4 × 10-12
W
2
M2 = 350.8 × 10-9
WM2 = 592 × 10-6
Problem 3.3-3
Repeat Examples 3.3-1 and 3.3-2 if the W/L ratio is 100 µm/10 µm.
Problem correction: Assume λλλλ = 0.01.
Repeat of Example 3.3-1
N-Channel Device
gm = (2K'W/L)|ID|
gm = 2×110 × 10-6 ×10 × 50 × 10-6 = 332 × 10-6
gmbs = gm
γ
2(2|φF| + VSB)1/2
gmbs = 332 × 10-6 0.4
2(0.7+2.0)1/2 = 40.4 × 10-6
gds = ID λ
gds = 50 × 10-6 × 0.01 = 500 × 10-9
P-Channel Device
gm = (2K'W/L)|ID|

PQRSTUVWXYP`abc`defh`YUipnd
Problem 3.1-5
Equation (3.1-12) and Eq. (3.1-18) describe the MOS model in nonsaturation and
saturation region, respectively. These equations do not agree at the point of transition
between saturation and nonsaturation regions. For hand calculations, this is not an issue,
but for computer analysis, it is. How would you change Eq. (3.1-18) so that it would
agree with Eq. (3.1-12) at vDS = vDS (sat)?
iD = K'
W
L '
(
)
*
+
,
(vGS − VT) −
vDS
2
vDS (3.1-12)
iD = K'
W
2L
(vGS − VT)2
(1 + λvDS), 0 (vGS − VT) ≤ vDS (3.1-18)
What happens to Eq. 3.1-12 at the point where saturation occurs?
iD = K'
W
L '
(
)
*
+
,
(vGS − VT) −
vDS (sat)
2 vDS(sat)
vDS (sat)= vGS − VT
then
iD = K'
W
L '
(
(
)
*
+
+
,
(vGS − VT) vDS(sat) −
v
2
DS
(sat)
2
iD = K'
W
L '
(
)
*
+
,
(vGS − VT) (vGS − VT) −
(vGS − VT)2
2
iD = K'
W
L '
(
)
*
+
,
( vGS − VT) 2 −
(vGS − VT)2
2
= K'
W
L '
(
)
*
+
,(vGS − VT)2
2
iD = K'
W
L '
(
)
*
+
,(vGS − VT)2
2
which is not equal to Eq.(3.1-18) because of the channel-length modulation term.
Since Eq. (3.1-18) is valid only during saturation when vDS vDS(sat) we can subtract
vDS(sat) from the vDS in the channel-length modulation term. Doing this results in the
following modification of Eq. (3.1-18).

æçèéêëìíîïæðñòóðôõö÷ðïëøùnd
gds = β(VGS − VT − VDS) = 10 ×50 × 10-6 (5 − 1.144− 1) = 1.428 × 10-3
Problem 3.3-4
Find the complete small-signal model for an n-channel transistor with the drain at 4 V,
gate at 4 V, source at 2 V, and the bulk at 0 V. Assume the model parameters from Tables
3.1-1, 3.1-2, and 3.2-1, and W/L = 10 µm/1 µm.
VT = VT0 + γ [ ]2|φF| + vSB − 2|φF|
VT = 0.7 + 0.4 [ ]0.7 + 2.0 − 0.7 = 1.02
ID =
K'W
2L ( )vGS − vT
2
(1 + λ vDS) =
110 × 10-6 ×10
2 ( )2 - 1.02 2(1 + 0.4×2) = 570 × 10-6
gm = (2K'W/L)|ID|
gm = 2×110 × 10-6 ×10 × 570 × 10-6 = 1.12 × 10-3
gmbs = gm
γ
2(2|φF| + VSB)1/2
gmbs = 1.12 × 10-3 0.4
2(0.7+2.0)1/2 = 136 × 10-6
gds = ID λ
gds = 570 × 10-6 × 0.04 = 22.8 × 10-9
LD =
220 × 10-12
24.7 × 10-4 ≅ 89 × 10-9
Leff = L - 2 × LD = 1 × 10-6 − 2 × 89 × 10-9 = 822 × 10-9
CGB = CGBO x Leff = 700 × 10-12 × 822 × 10-9 = 0.575 fF

úûüýþÿg ¡¢ ú£¤¥¦£§ ¨©£¢ÿ
nd
CGS = 220 × 10-12 × 10 × 10-6 + 0.67 × 24.7 × 10-4 × 822 × 10-9 × 10 × 10-6
CGS = 15.8 × 10-15
CGD = CGDO(Weff)
CGD = CGDO(Weff) = 220 × 10-12 × 10 × 10-6 = 2.2 × 10-15
Problem 3.3-5
Consider the circuit in Fig P3.3-5. It is a parallel connection of n mosfet transistors.
Each transistor has the same length, L, but each transistor can have a different width, W.
Derive an expression for W and L for a single transistor that replaces, and is equivalent to,
the multiple parallel transistors.
The expression for drain current in saturation is:
ID =
K'W
2L ( )vGS − vT
2
(1 + λ vDS)
For multiple transistors with the same drain, gate, and source voltage, the drain current
can be expressed simply as
ID(i) =
-
.
/
0
1
2W
L i
( )vGS − vT
2
(1 + λ vDS)
The drain current in each transistor is additive to the total current, thus
ID(TOTAL) = ( )vGS − vT
2
(1 + λ vDS)
'
(
)
*
+
,
3-
.
/
0
1
2W
L i
Since the lengths are the same, we have
ID(TOTAL) =
1
L( )vGS − vT
2
(1 + λ vDS)
'
(
)
*
+
,
3Wi
Problem 3.3-6
Consider the circuit in Fig P3.3-6. It is a series connection of n mosfet transistors. Each
transistor has the same width, W, but each transistor can have a different length, L.
Derive an expression for W and L for a single transistor that replaces, and is equivalent to,
the multiple parallel transistors. When using the simple model, you must ignore body
effect.
Error in problem statement : replace “parallel” with “series”

! #$%#' ()0# 12
nd
Figure P3.3-6
M1
M2
Mn
Assume that all devices are in the non-saturation region.
Consider the case for two transistors in series as illustrated below.
M1
M2
v1
v2
vG
w3
v2
vG
„45 6789@ AB775@C 9@ DE 9F
i1 =
K'W
L '
(
(
)
*
+
+
,
(vGS − VT) vDS −
v
2
DS
2
i1 = β1 '
(
(
)
*
+
+
,
(vGS − VT) v1 −
v
2
1
2 = β1 '
(
(
)
*
+
+
,
(vG − VT) v1 −
v
2
1
2
i1 = β1 '
(
(
)
*
+
+
,
Von v1 −
v
2
1
2
where

GHIP QRSTUV GWXY`Wa bcdWVR ef
nd
Von = vG − VT
v1 = Von − V
2
on
−
2i1
β1
v
2
1 = 2Von − 2Von V
2
on
−
2i1
β1
−
2i1
β1
The drain current in M2 is
i2 = β2 '
(
)
*
+
,
(vG − v1 − VT)( v2 − v1) −
( v2 − v1)
2
2
i2 = β2 '
(
)
*
+
,
( Von − v1)( v2 − v1) −
( v2 − v1)
2
2
i2 = β2 '
(
(
)
*
+
+
,
Von v2 − Vonv1 +
v
2
1
2 −
v
2
2
2
Substitue the earlier expression for v1 and equate the drain currents (drain currents must
be equal)
i2 =
β1 β2
β1 + β2 '
(
(
)
*
+
+
,
Von v2 −
v
2
2
2
The expression for the current in M3 is
i3 = β3 '
(
(
)
*
+
+
,
(vGS − VT) v2 −
v
2
2
2
= β3 '
(
(
)
*
+
+
,
Von v2 −
v
2
2
2
The drain current in M3 must be equivalent to the drain current in M1 and M2, thus
β3 =
β1 β2
β1 + β2
=
-
.
/
0
1
21
β1
+
1
β2
-1
=
-
.
/
0
1
2L1
K'W1
+
L2
K'W2
-1

‘’“ ”•–—˜™ defgdh ijkd™• lm
nd
fast = 0.0259 (1 + .453 + 0.739) = 56.77 × 10-3
von = VT + fast =0.0259 + 56.77 × 10-3 = 82.67 × 10-3
Problem 3.5-2
Develop an expression for the small signal transconductance of a MOS device operating
in weak inversion using the large signal expression of Eq. (3.5-5).
iD ≅
W
L IDO exp
-
.
/
0
1
2vGS
n(kT/q)
gm =
∂ID
∂VGS
=
W
L -
.
/
0
1
21
n(kT/q) IDO exp
-
.
/
0
1
2vGS
n(kT/q) =
ID
n(kT/q)
Problem 3.5-3
Another way to approximate the transition from strong inversion to weak inversion is to
find the current at which the weak-inversion transconductance and the strong-inversion
transconductance are equal. Using this method and the approximation for drain current in
weak inversion (Eq. (3.5-5)), derive an expression for drain current at the transition
between strong and weak inversion.
gm =
W
L -
.
/
0
1
21
n(kT/q)
IDO exp
-
.
/
0
1
2vGS
n(kT/q) = (2K'W/L)ID
-
.
/
0
1
2W
L
2
-
.
/
0
1
21
n(kT/q)
2
I
2
DO
exp
-
.
/
0
1
22vGS
n(kT/q) = (2K'W/L)ID
ID =
-
.
/
0
1
21
2K' -
.
/
0
1
2W
L -
.
/
0
1
2IDO
n(kT/q)
2
exp
-
.
/
0
1
22vGS
n(kT/q)
ID =
-
.
/
0
1
21
2K' IDO -
.
/
0
1
21
n(kT/q)
2
exp
-
.
/
0
1
2vGS
n(kT/q)
×
-
.
/
0
1
2W
L IDO exp
-
.
/
0
1
2vGS
n(kT/q)
ID =
-
.
/
0
1
21
2K' IDO -
.
/
0
1
21
n(kT/q)
2
exp
-
.
/
0
1
2vGS
n(kT/q) × ID
2K' [n(kT/q)]
2
= IDO exp
-
.
/
0
1
2vGS
n(kT/q) =
ID
W/L

nopq rstuvw nxyz{x| }~xws €
nd
ID = 2K'
W
L [n(kT/q)]
2
Problem 3.6-1
Consider the circuit illustrated in Fig. P3.6-1. (a) Write a SPICE netlist that describes
this circuit. (b) Repeat part (a) with M2 being 2µm/1µm and it is intended that M3 and
M2 are ratio matched, 1:2.
Part (a)
Problem 3.6-1 (a)
M1 2 1 0 0 nch W=1u L=1u
M2 2 3 4 4 pch w=1u L=1u
M3 3 3 4 4 pch w=1u L=1u
R1 3 0 50k
Vin 1 0 dc 1
Vdd 4 0 dc 5
.MODEL nch NMOS VTO=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
.MODEL pch PMOS VTO=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8
.op
.end
Part (b)
Problem 3.6-1 (b)
M1 2 1 0 0 nch W=1u L=1u
M2 2 3 4 4 pch w=1u L=1u M=2
M3 3 3 4 4 pch w=1u L=1u
R1 3 0 50k
Vin 1 0 dc 1
Vdd 4 0 dc 5
.MODEL nch NMOS VTO=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
.MODEL pch PMOS VTO=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8
.op
.end
Problem 3.6-2
Use SPICE to perform the following analyses on the circuit shown in Fig. P3.6-1: (a) Plot
vOUT versus vIN for the nominal parameter set shown. (b) Separately, vary K' and VT by
+10% and repeat part (a)—four simulations.
Parameter N-Channel P-Channel Units
VT 0.7 -0.7 V
K' 110 50 µA/V2
l 0.04 0.05 V-1

‚ƒ„… †‡ˆ‰Š‹ ‚ŒŽŒ ‘’“Œ‹‡ ”•
nd
–
IN
vOUT
R =50kΩ
1
2
3
4
Figure P3.6-1
VDD = 5 V
M1
M2
M3
W/L = 1µ/1µ W/L = 1µ/1µ
W/L = 1µ/1µ
Problem 3.6-2
M1 2 1 0 0 nch W=1u L=1u
M2 2 3 4 4 pch w=1u L=1u
M3 3 3 4 4 pch w=1u L=1u
R1 3 0 50k
Vin 1 0 dc 1
Vdd 4 0 dc 5
*.MODEL nch NMOS VTO=0.7 KP=110U LAMBDA=0.04
*.MODEL pch PMOS VTO=-0.7 KP=50U LAMBDA=0.05
*
*
*
*
.MODEL nch NMOS VTO=0.7 KP=110U LAMBDA=0.04
.MODEL pch PMOS VTO=-0.7 KP=55U LAMBDA=0.05
.dc vin 0 5 .1
.probe
.end

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nd
«¬ ¬ 4V
«¬
2V
4V
K'N
=121u
VTN
= 0.77
K'
P
= 55u
V
TP
= -0.77
VOUT
V
IN
®¯°±²³´ µ¶·¸µ
Use SPICE to plot i2 as a function of v2 when i1 has values of 10, 20, 30, 40, 50, 60, and
70 µA for Fig. P3.6-3. The maximum value of v2 is 5 V. Use the model parameters of VT
= 0.7 V and K' = 110 µA/V2 and λ = 0.01 V-1. Repeat with λ = 0.04 V-1.
¹
2
Figure P3.6-3
M1 M2
W/L = 10µm/2µm
i1 i2
W/L = 10µm/2µm
+
−
º»¼½¾»
M1 1 1 0 0 nch l = 2u w = 10u
M2 2 1 0 0 nch l = 2u w = 10u
I1 0 1 DC 0
V1 3 0 DC 0
V_I2 3 2 DC 0
.MODEL nch NMOS VTO=0.7 KP=110U LAMBDA=0.01 GAMMA = 0.4 PHI = 0.7
*.MODEL nch NMOS VTO=0.7 KP=110U LAMBDA=0.04 GAMMA = 0.4 PHI = 0.7
.dc V1 0 5 .1 I1 10u 80u 10u
.END

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nd
VGS 3 0 DC 0
VDS 4 0 DC 0
V_IDS 4 2 DC 0
.MODEL nch NMOS VTO=1 KP=110U LAMBDA=0.01 GAMMA = 0.4 PHI = 0.7
.dc VDS 0 5 .1 VGS 0 5 1
.END
é
DS
IDS
2mA
4mA
1 2 3 4 50
0
VGS= 5
VGS= 4
VGS= 3
VGS= 2
Problem 3.6-5
Repeat Example 3.6-1 if the transistor of Fig. 3.6-5 is a PMOS having the model
parameters given in Table 3.1-2.
p3.6-5
V_IDS 5 2 DC 0
VGS 3 0 DC 0
VDS 5 0 DC 0
M1 2 3 0 0 pch l = 1u w = 5u
.MODEL pch PMOS VTO=-0.7 KP=50U LAMBDA=0.051 GAMMA = 0.57 PHI = 0.8
.dc VDS 0 -5 -.1 VGS 0 -5 -1
.END

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nd
þ
DS
IDS
-1mA
-4 -3 -2 -1 0-5
-2mA
-3mA
0mA
VGS= -5
VGS= -4
VGS= -3
VGS= -2
Problem 3.6-6
Repeat Examples 3.6-2 through 3.6-4 for the circuit of Fig. 3.6-2 if R1 = 200 KΩ.
0V 2V 4V
0V
2V
4V
VIN
VOUT

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AC Analysis
-20
20
40
e2 e4 e6 e8
0
Frequency
vdb(2)
e e e e!
0
-90
Frequency
vp(2)
E
Transient Analysis

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2us 6us
0V
2V
4V
4us
0V
2V
4V
0
V(2)

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