Cortex_M3 Instruction SetCortex_M3 Instruction SetCortex_M3 Instruction Set.pptx

ARM Cortex-M3 Processor
Dr. Aruru Sai Kumar
Assistant Professor
VNRVJIET

ARM Cortex-M3 Instruction Set and Memory System
• UNIT – V:
• ARM Cortex-M3 Instruction Set Instruction Sets: ARM Cortex-M3 16-bit and 32-bit Instruction
Set, Unified Assembler Language, Data Processing Instructions, Branch Instructions, Load and Store
Instructions
• Memory System: Memory Maps, Memory Access Attributes, Default Memory Access Permissions,
Bit-Band Operations, Unaligned Transfers, Exclusive accesses, Pipeline

Topics
• ARM Cortex-M3 Instruction Set
• ARM Cortex-M3 16-bit Instruction Set
• ARM Cortex-M3 32-bit Instruction Set
• Unified Assembler Language
• Data Processing Instructions
• Branch Instructions
• Load and Store Instructions

Instruction format
• In assembler code, the following instruction formatting is commonly used:
• Label: opcode operand1, operand2, ...; Comments
•The label is optional. Some of the instructions might have a label in front of
them so that the address of the instructions can be determined using the label.
•Then, you will find the opcode (the instruction) followed by a number of
operands. The opcode is the instruction.
•Normally, the first operand is the destination of the operation.
• The number of operands in an instruction depends on the type of
instruction, and the syntax format of the operand can also be different.

MOV Instruction
• MOV R0, #0x12 ; Set R0 = 0x12 (hexadecimal)
• MOV R1, #34 ; R1 = 34 (decimal)
• MOV R2, #2_10010110 ; Set R2 =10010110=96h(hexadecimal)
• MOV R5, #8_33 ; Set R2 =(33)8=27(decimal)
• MOV R6, #’A’ ; Set R1 = ASCII character A
• MOV R7, #0x9999999 ; Illegal
• Note: Immediate operand data must be in the (00h to FFh)

LDR Instructions
• LDR Rd, [Rx] instruction
LDR Rd,[Rx] ;load Rd with the contents of location pointed to by Rx register.
Rx is an address between 0x00000000 to 0xFFFFFFFF

LDRB Rd, [Rx] ;
LDRH Rd, [Rx] ;
• Ex: LDRB R5,[R4] ex: LDRH
R7,[R5]
Table : compares LDRB, LDRH, and LDR.

• STR Rx, [Rd]
• STR R3,[R6] ;store R3 into locations pointed to by R6.

• STRB R1,[R5]
STRH R3,[R6]
Table: Comparison between STRB, STRH, and STR.

Assembler Language: Use of Suffixes

Conditional Branch Instructions

Assembler Language: Unified Assembler Language
• UAL was developed to allow selection of 16-bit and 32-bit instructions and to make it easier to port
applications between ARM code and Thumb code by using the same syntax for both.
• ADD R0, R1 ; R0 = R0 + R1, using Traditional Thumb syntax
• ADD R0, R0, R1 ; Equivalent instruction using UAL syntax
•One thing you need to be careful with reusing traditional Thumb is that some instructions change the flags
in APSR, even if the S suffix is not used. However, when the UAL syntax is used, whether the instruction
changes the flag depends on the S suffix. For example,
• AND R0, R1 ; Traditional Thumb syntax
• ANDS R0, R0, R1 ; Equivalent UAL syntax (S suffix is added)
•With UAL, you can specify which instruction you want by adding suffixes:
• ADDS R0, #1 ; Use 16-bit Thumb instruction by default for smaller size
• ADDS.N R0, #1 ; Use 16-bit Thumb instruction (N=Narrow)
• ADDS.W R0, #1 ; Use 32-bit Thumb-2 instruction (W=wide)
The .W (wide) suffix specifies a 32-bit instruction. If no suffix is given, the assembler tool can choose either
instruction but usually defaults to 16-bit Thumb code to get a smaller size. Depending on tool support, you
may also use the .N (narrow) suffix to specify a 16-bit Thumb instruction.

•In most cases, applications will be coded in C, and the C compilers will use 16-bit instructions if
possible due to smaller code size. However, when the immediate data exceed a certain range or
when the operation can be better handled with a 32-bit Thumb-2 instruction, the 32-bit instruction
will be used.
•The 32-bit Thumb-2 instructions can be half word aligned. For example, you can have a 32-bit
instruction located in a half word location.
• 0x1000 : LDR r0,[r1] ;a 16-bit instructions (occupy 0x1000-0x1001)
• 0x1002 : RBIT.W r0 ;a 32-bit Thumb-2 instruction (occupy 0x1002-0x1005)
• Most of the 16-bit instructions can only access registers R0–R7.
• 32-bit Thumb-2 instructions do not have this limitation.
• However, use of PC (R15) might not be allowed in some of the instructions.

Cortex_M3 Instruction SetCortex_M3 Instruction SetCortex_M3 Instruction Set.pptx

16- bit Load and Store Instructions

32- bit Data Processing Instructions

Assembler Language: Processing Data

Examples of Arithmetic Instructions

Assembler Language: CALL and
Unconditional Branch

Assembler Language: Decisions and
conditional Branches

Conditional Branches

Conditional Branches (contd.)

Cortex-M3 useful Instructions
• MRS and MSR Instructions

Cortex-M3 useful Instructions
• MRS and MSR Instructions for special purpose registers (contd.)

16 bit Data processing Instructions

INSTRUCTION DESCRIPTIONS
• Assembler Language: Moving Data
• . In the Cortex-M3, data transfers can be of one of the following types:
• Moving data between register and register
• Moving data between memory and register
• Moving data between special register and register
• Moving an immediate data value into a register

• In the Cortex-M3, data transfers can be of one of the following types:
• Moving data between register and register
• The command to move data between registers is MOV (move). For example,
moving data from register R3 to register R8 looks like this:
• MOV R8, R3
• Another instruction can generate the negative value of the original data; it is
called MVN (move negative).
• MVN R9, R5; R9= ~R5

• . In the Cortex-M3, data transfers can be of one of the following types:
• Moving data between memory and register
•ARM processors also support memory accesses with pre-indexing and post-indexing. For pre-indexing, the
register holding the memory address is adjusted. The memory transfer then takes place with the updated
address. For example,
• LDR.W R0,[R1, #offset]!; Read memory[R1+offset],
• with R1 update to R1+offset

•Multiple Load and Store operations can be combined into single instructions called LDM (Load Multiple) and
STM (Store Multiple), as outlined in Table 4.15.
•The exclamation mark (!) in the instruction specifies whether the register Rd should be updated after the
instruction is completed. For example, if R8 equals 0x8000:
• STMIA.W R8!, {R0-R3} ; R8 changed to 0x8010 after store
; (increment by 4 words)
STMIA.W R8 , {R0-R3} ; R8 unchanged after store

• The use of the “!” indicates the update of base register R1. The “!” is optional; without it, the instruction would
be just a normal memory transfer with offset from a base address. The preindexing memory access instructions
include load and store instructions of various transfer sizes (see Table 4.16).

•Post indexing memory access instructions carry out the memory transfer using the base address specified by
the register and then update the address register afterward. For example,
• LDR.W R0,[R1], #offset ; Read memory[R1], with R1
• ; updated to R1+offset
•When a post indexing instruction is used, there is no need to use the “!” sign, because all post-indexing
instructions update the base address register, whereas in pre-indexing you might choose whether to update the
base address register or not.

LDRD, STRD Instructions
•The two instructions LDRD and STRD transfer two words of data from or into two registers. The syntax of
the instructions is as follows:
• LDRD.W <Rxf>, <Rxf2>, [Rn, #+/−offset]{!} ; Pre-indexed
• LDRD.W <Rxf>, <Rxf2>, [Rn], #+/−offset ; Post-indexed
• STRD.W <Rxf>, <Rxf2>, [Rn, #+/−offset]{!} ; Pre-indexed
• STRD.W <Rxf>, <Rxf2>, [Rn], #+/−offset ; Post-indexed
• where <Rxf> is the first destination/source register and <Rxf2> is the second destination/source register.
Avoid using same register for <Rn> and <Rxf> when using LDRD because of an erratum in Cortex- M3
revision 0 to 2.
•For example, the following code reads a 64-bit value located in memory address 0x1000 into R0 and R1:
• LDR R2,=0x1000
• LDRD.W R0, R1, [R2] ; This will gives R0 = memory[0x1000], ; R1 = memory[0x1004]
• Similarly, we can use STRD to store a 64-bit value in memory. In the following example, preindexed
addressing mode is used:
• LDR R2,=0x1000 ; Base address
• STRD.W R0, R1, [R2, #0x20] ; This will gives memory[0x1020] = R0, ; memory[0x1024] = R1

• Assembler Language: PUSH, POP
• PUSH {R0, R4-R7, R9} ; Push R0, R4, R5, R6, R7, R9 into stack memory
• POP {R2,R3} ; Pop R2 and R3 from stack
• Usually a PUSH instruction will have a corresponding POP with the same register list, but this is not
always necessary. For example, a common exception is when POP is used as a function return:
• PUSH {R0-R3, LR} ; Save register contents at beginning of
; subroutine
.... ; Processing
• POP {R0-R3, PC} ; restore registers and return
• In this case, instead of popping the LR register back and then branching to the address in LR, we
POP the address value directly in the program counter.

• Assembler Language: MRS, MSR
•The Cortex-M3 has a number of special registers. To access these registers, we use the
instructions MRS and MSR. For example,
• MRS R0, PSR ; Read Processor status word into R0
• MSR CONTROL, R1 ; Write value of R1 into control register
• Unless you’re accessing the APSR, you can use MSR or MRS to access other special registers only in
privileged mode.

• Assembler Language: Immediate data
•Moving immediate data into a register is a common thing to do. For example, you might want to
access a peripheral register, so you need to put the address value into a register beforehand. For
small values (8 bits or less), you can use MOVS (move). For example,
• MOVS R0, #0x12 ; Set R0 to 0x12
• For a larger value (over 8 bits), you might need to use a Thumb-2 move instruction. For example,
• MOVW.W R0, #0x789A ; Set R0 to 0x789A
• Or if the value is 32-bit, you can use two instructions to set the upper and lower halves:
• MOVW.W R0,#0x789A ; Set R0 lower half to 0x789A
• MOVT.W R0,#0x3456 ; Set R0 upper half to 0x3456. Now
• ; R0=0x3456789A

• Assembler Language: LDR , ADR Pseudo Instructions
•Both LDR and ADR pseudo-instructions can be used to set registers to a program address value. They have
different syntaxes and behaviors. For LDR, if the address is a program address value, the assembler will
automatically set the LSB to 1. For example,
• LDR R0, =address1 ; R0 set to 0x4001
• ...
• address1 ; address here is 0x4000
• MOV R0, R1 ; address1 contains program code
• ...
•You will find that the LDR instruction will put 0x4001 into R1; the LSB is set to 1 to indicate that it is Thumb
code. If address1 is a data address, LSB will not be changed. For example,
• LDR R0, =address1 ; R0 set to 0x4000
• ...
• address1 ; address here is 0x4000
DCD 0x0 ; address1 contains data
• ...

• Assembler Language: ADR Pseudo Instructions
•For ADR, you can load the address value of a program code into a register without setting the LSB
automatically. For example,
• ADR R0, address1
• ...
• address1 ; (address here is 0x4000)
• MOV R0, R1 ; address1 contains program code
• ...
• You will get 0x4000 in the ADR instruction. Note that there is no equal sign (=) in the ADR statement.
•LDR obtains the immediate data by putting the data in the program code and uses a PC relative load to get
the data into the register. ADR tries to generate the immediate value by adding or subtracting instructions (for
example, based on the current PC value). As a result, it is not possible to create all immediate values using
ADR, and the target address label must be in a close range. However, using ADR can generate smaller code
sizes compared with LDR.
•The 16-bit version of ADR requires that the target address must be word aligned (address value is a multiple of
4). If the target address is not word aligned, you can use the 32-bit version of ADR instruction “ADR.W.” If the
target address is more than ± 4095 bytes of current PC, you can use “ADRL” pseudo-instruction,
which gives ±1 MB range.

• The Cortex-M3 provides many different instructions for data processing. A few basic ones
are introduced here. Many data operation instructions can have multiple instruction
formats. For example, an ADD instruction can operate between two registers or between
one register and an immediate data value:
• ADD R0, R0, R1 ; R0 = R0 + R1
• ADDS R0, R0, #0x12 ; R0 = R0 + 0x12
• ADD.W R0, R1, R2 ; R0 = R1 + R2
• These are all ADD instructions, but they have different
syntaxes and binary coding.

In UAL syntax, the rotate and shift operations can also update the carry flag if the S suffix is used (and
always update the carry flag if the 16-bit Thumb code is used).
If the shift or rotate operation shifts the register position by multiple bits, the value of the carry flag
C will be the last bit that shifts out of the register.

Byte or half word to Word Extension Instructions
SXTB, SXTH, UXTB, and UXTH
• The four instructions SXTB, SXTH, UXTB, and UXTH are used to extend a byte or half word data
into a word. The syntax of the instructions is as follows:
SXTB <Rd>, <Rn>
SXTH <Rd>, <Rn>
UXTB <Rd>, <Rn>
UXTH <Rd>, <Rn>
•For SXTB/SXTH, the data are sign extended using bit[7]/bit[15] of Rn.
•With UXTB and UXTH, the value is zero extended to 32-bit. For example, if R0 is 0x55AA8765:
• SXTB R1, R0 ; R1 = 0x00000065
• SXTH R1, R0 ; R1 = 0xFFFF8765
• UXTB R1, R0 ; R1 = 0x00000065
• UXTH R1, R0 ; R1 = 0x00008765

For conversion of signed data from byte or half word to word, the Cortex-M3 provides the two
instructions shown in Table 4.22. Both 16-bit and 32-bit versions are available. The 16-bit version can
only access low registers.
Data processing instructions is used for reversing data bytes in a register (see Table 4.23). These
instructions are usually used for conversion between little endian and big endian data. The 16-bit
version can only access low registers.

• The last group of data processing instructions is for bit field processing. They
include the instructions shown in Table 4.24.

• REV reverses the byte order in a data word, and REVH reverses the byte order inside a half word.
For example, if R0 is 0x12345678, in executing the following:
• REV R1, R0
REVH R2, R0
• R1 will become 0x78563412, and R2 will be 0x34127856.
REV and REVH are particularly useful for converting data
between big endian and little endian.
REVSH is similar to REVH except that it only processes the
lower half word, and then it sign extends the result.
For example, if R0 is 0x33448899, running:
• REVSH R1, R0
• R1 will become 0xFFFF9988
• The RBIT instruction reverses the bit order in a data word. The
syntax is as follows:
• RBIT.W <Rd>, <Rn>

Assembler Language: Call and Unconditional Branch
The most basic branch instructions are as follows:
B label ; Branch to a labeled address
BX reg ; Branch to an address specified by a register
In BX instructions, the LSB of the value contained in the register determines the next state (Thumb/ ARM)
of the processor. In the Cortex-M3, because it is always in Thumb state, this bit should be set to 1. If it is
zero, the program will cause a usage fault exception because it is trying to switch the processor into ARM
state.
To call a function, the branch and link instructions should be used.
BL label ; Branch to a labeled address and save return
; address in LR
BLX reg ; Branch to an address specified by a register and
; save return address in LR.
With these instructions, the return address will be stored in the link register (LR) and the function can
be terminated using BX LR, which causes program control to return to the calling process. However, when
using BLX, make sure that the LSB of the register is 1. Otherwise the processor will produce a fault
exception because it is an attempt to switch to the ARM state.

• You can also carry out a branch operation using MOV instructions and LDR instructions. For example,
• MOV R15, R0; Branch to an address inside R0
• LDR R15, [R0] ; Branch to an address in memory location specified by R0
• POP {R15} ; Do a stack pop operation, and change the program counter value to the result value.
•When using these methods to carry out branches, you also need to make sure that the LSB of the new
program counter value is 0x1. Otherwise, a usage fault exception will be generated because it will try to
switch the processor to ARM mode, which is not allowed in the Cortex-M3 redundancy.

•SAVE THE LR IF YOU NEED TO CALL A SUBROUTINE
•The BL instruction will destroy the current content of your LR. So, if your program code needs the LR later, you should save
your LR before you use BL. The common method is to push the LR to stack in the beginning of your subroutine. For example,
• main
• ...
• BL functionA
• ...
• functionA
• PUSH {LR} ; Save LR content to stack
• ...
• BL functionB
• ...
•POP {PC} ; Use stacked LR content to return to main functionB
• PUSH {LR}
• ...
• POP {PC} ; Use stacked LR content to return to functionA
•In addition, if the subroutine you call is a C function, you might also need to save the contents in R0–R3 and R12 if these
values will be needed at a later stage. According to AAPCS [Ref. 5], the contents in these registers could be changed by a C
function.

Assembler Language: Decisions and Conditional Branches
Using these conditions, branch instructions can be written as, for example,
BEQ label ; Branch to address 'label' if Z flag is set
You can also use the Thumb-2 version if your branch target is further away. For example,
BEQ.W label ; Branch to address 'label' if Z flag is set

compare
•The compare (CMP) instruction subtracts two values and updates the flags (just like SUBS),
but the result is not stored in any registers. CMP can have the following formats:
• CMP R0, R1; Calculate R0 – R1 and update flag
• CMP R0, #0x12 ; Calculate R0 – 0x12 and update flag
•A similar instruction is the CMN (compare negative). It compares one value to the negative
(two’s complement) of a second value; the flags are updated, but the result is not stored in any
registers:
• CMN R0, R1; Calculate R0 – (-R1) and update flag
• CMN R0, #0x12 ; Calculate R0 – (-0x12) and update flag
•The TST (test) instruction is more like the AND instruction. It ANDs two values and updates
the flags. However, the result is not stored in any register. Similarly to CMP, it has two input
formats:
•TST R0, R1 ; Calculate R0 AND R1 and update flag
•TST R0, #0x12 ; Calculate R0 AND 0x12 and update flag

Assembler Language: Combined Compare and
Conditional Branch(CBZ)
• The compare and branch instructions only support forward branches.
For example,
i = 5;
while (i != 0 ){
func1(); ; call a function
i−−;
}
MOV R0, #5 ; Set loop counter
loop1 CBZ R0,loop1exit ; if loop counter = 0 then exit the loop
BL func1 ; call a function
SUB R0, #1 ; loop counter decrement
B loop1 ; next loop
Loop1 exit

Assembler Language: Combined Compare and
Conditional Branch(CBNZ)
•The usage of CBNZ is similar to CBZ, apart from the fact that the branch is taken if the Z flag is not set
(result is not zero). For example,
• status = strchr(email_address, '@');
if (status == 0){//status is 0 if @ is not in email_address
show_error_message();
exit(1);
}
• This can be compiled into the following:
• ...
BL strchr
CBNZ R0, email_looks_okay ; Branch if result is not zero
BL show_error_message
BL exit email_looks_okay
...
• The APSR value is not affected by the CBZ and CBNZ
instructions.

Assembler Language: Conditional Execution
Using IT Instructions
• The IT (IF-THEN) block is very useful for handling small conditional code. It avoids branch penalties because
there is no change to program flow. It can provide a maximum of four conditionally executed instructions.
• In IT instruction blocks, the first line must be the IT instruction, detailing the choice of execution, followed by
the condition it checks. The first statement after the IT command must be
TRUE-THEN-EXECUTE, which is always written as IT xyz, where T means THEN and E means ELSE. The second
through fourth statements can be either THEN (true) or ELSE (false):
• IT<x><y><z> <cond> ; IT instruction (<x>, <y>,
; <z> can be T or E)
• instr1<cond> <operands> ; 1st instruction (<cond>
; must be same as IT)
instr2<cond or not cond> <operands> ; 2nd instruction (can be
; <cond> or <!cond>
instr3<cond or not cond> <operands> ; 3rd instruction (can be
; <cond> or <!cond>
instr4<cond or not cond> <operands> ; 4th instruction (can be
; <cond> or <!cond>

IF-THEN-ELSE structures.
• CMP R0, R1 ; Compare R0 and R1
• ITTEE GT ; If R0 > R1 Then
• ; if true, first 2 statements execute,
• ; if false, other 2 statements execute
• MOVGT R2, R0 ; R2 = R0
• MOVGT R3, R1 ; R3 = R1
• MOVLE R2, R0 ; Else R2 = R1
• MOVLE R3, R1 ; R3 = R0
•APSR flags can be affected by the following:
• Most of the 16-bit ALU instructions
• 32-bit (Thumb-2) ALU instructions with the S suffix; for example,
ADDS.W
• Compare (e.g., CMP) and Test (e.g., TST, TEQ)
• Write to APSR/xPSR directly

Assembler Language: Conditional Execution Using
IT Instructions
•If a statement is to be executed when <cond> is false, the suffix for the instruction must be the opposite of
the condition. For example, the opposite of EQ is NE, the opposite of GT is LE, and so on. The following code
shows an example of a simple conditional execution:
• if (R1<R2) then
R2=R2−R1
R2=R2/2
else
R1=R1−R2
R1=R1/2
• You can have fewer than four conditionally executed
instructions. The minimum is 1. You need to make sure the
number of T and E occurrences in the IT instruction matches
the number of conditionally executed instructions after the IT.
CMP R1, R2 ; If R1 < R2 (less then)
ITTEE LT ; then execute instruction 1 and 2
; (indicated by T)
; else execute instruction 3 and 4;
(indicated by E)
SUBLT.W R2,R1 ; 1st
instruction
LSRLT.W R2,#1 ; 2nd
instruction
SUBGE.W R1,R2 ; 3rd instruction (notice the GE is
; opposite of LT)
LSRGE.W R1,#1;4th
instruction

• If an exception occurs during the IT instruction block, the execution status of the block will
be stored in the stacked PSR (in the IT/Interrupt-Continuable Instruction [ICI] bit field). So,
when the exception handler completes and the IT block resumes, the rest of the instructions
in the block can continue the execution correctly.
• In the case of using multicycle instructions (for example, multiple load and store) inside an
IT block, if an exception takes place during the execution, the whole instruction is
abandoned and restarted after the interrupt process is completed.

IT Instructions
The <cond> part uses the same condition symbols as conditional branch. If “AL” is used as <cond>,
then you cannot use “E” in the condition control as it implies the instruction should never get
executed. Each of <x>, <y>, and <z> can be either T (THEN) or E (ELSE), which refers to the base
condition
<cond>, whereas <cond> uses traditional syntax such as EQ, NE, GT, or the like.

• Here is an example of IT use:
•if (R0 equal R1) then { R3 = R4 + R5
R3 = R3/2
}
else {
R3 = R6 + R7
R3 = R3/2
}
•This can be written as follows:
CMP R0, R1 ; Compare R0 and R1
ITTEE EQ ; If R0 equal R1, Then-Then-Else-Else
ADDEQ R3, R4, R5 ; Add if equal
ASREQ R3, R3, #1 ; Arithmetic shift right if equal
ADDNE R3, R6, R7 ; Add if not equal
ASRNE R3, R3, #1 ; Arithmetic shift right if not equal

Assembly Language: Saturation Operations
• The Cortex-M3 supports two instructions that provide signed and unsigned saturation operations:
SSAT and USAT (for signed data type and unsigned data type, respectively).
• Saturation is commonly used in signal processing—for example, in signal amplification. When an input
signal is amplified, there is a chance that the output will be larger than the allowed output range. If
the value is adjusted simply by removing the unused MSB, an overflowed result will cause the signal
waveform to be completely deformed .
• The saturation operation does not prevent the distortion of the signal, but at least the amount of
distortion is greatly reduced in the signal waveform.
Fig: Signed Saturation Operation

Assembly Language: Saturation Operations
Ex: SSAT.W R1, #16, R0
USAT.W R1, #16, R0
Fig: Unsigned Saturation Operation

MRS & MSR Instructions
• These two instructions provide access to the special registers in the
Cortex-M3. Here is the syntax of these instructions:
• MRS <Rn>, <SReg> ; Move from Special Register
• MSR <SReg>, <Rn> ; Write to Special Register
• where <SReg> could be one of the options shown in Table 4.31.
• For example, the following code can be used to set up the process stack
pointer(PSP):
• LDR R0,=0x20008000 ; new value for Process Stack Pointer
• MSR PSP, R0
• Unless accessing the APSR, the MRS and MSR instructions can be used in
privileged mode only. Otherwise the operation will be ignored, and the
returned read data (if MRS is used) will be zero.
• After updating the value of the CONTROL register using MSR instruction,
it is recommended to add an ISB instruction to ensure that the effect of
the update takes place immediately. On the Cortex-M3 processor this is
not strictly required, but for software portability (if the software code is
to be used on other ARM processor) this is needed.

Table Branch Byte and Table Branch Halfword
• Table Branch Byte (TBB) and Table Branch Halfword (TBH) are for implementing branch tables. The TBB
instruction uses a branch table of byte size offset, and TBH uses a branch table of half word offset. Since
the bit 0 of a program counter is always zero, the value in the branch table is multiplied by two before it’s
added to PC. Furthermore, because the PC value is the current instruction address plus four, the branch
range for TBB is (2 × 255) + 4 = 514, and the branch range for TBH is (2 × 65535) + 4 = 131074. Both TBB
and TBH support forward branch only.
• TBB has this general syntax:
• TBB.W [Rn, Rm]
• where Rn is the base memory offset and Rm is the branch table index. The branch table item for TBB is
located at Rn + Rm. Assuming we used PC for Rn, we can see the operation as shown in Figure 4.5.
FIGURE 4.5: TBB Operation
TBB Operation.

Table Branch Halfword
For TBH instruction, the process is similar except the memory location of the branch table item is
located at Rn + 2 x Rm and the maximum branch offset is higher. Again, we assume that Rn is set to PC,
as shown in Figure 4.6.

TBB
• TBB.W [Rn, Rm] ; the branch range for TBB is (2 × 255) + 4 = 514
• where Rn is the base memory offset and Rm is the branch table index. The branch table item for TBB is located at Rn + Rm. If Rn in
the table branch instruction is set to R15, the value used for Rn will be PC + 4 because of the pipeline in the processor. These two
instructions are more likely to be used by a C compiler to generate code for switch (case) statements. Because the values in the branch
table are relative to the current program counter, it is not easy to code the branch table content manually in assembler as the address
offset value might not be able to be determined during assembly/compile stage, especially if the branch target is in a separate program
code file. The coding syntax for calculating TBB/TBH branch table content could be dependent on the development tool. In ARM
assembler (armasm), the TBB branch table can be created in the following way:
• TBB.W [pc, r0] ; when executing this instruction, PC equal; branchtable
• branchtable
• DCB ((dest0 − branchtable)/2) ; Note that DCB is used because ; the value is 8-bit
• DCB ((dest1 − branchtable)/2)
• dest0
•... ; Execute if r0 = 0
dest1
dest2
dest3
• ... ; Execute if r0 = 3

• AREA section name, attribute, attribute, …
• AREA MY_ASM_PROG1, CODE, READONLY
• Among widely used attributes are CODE, DATA, READONLY,
READWRITE, COMMON, and ALIGN.
• AREA OUR_VARIABLES, DATA, READWRITE
• AREA OUR_CONSTS, DATA, READONLY

ADR Pseudo Instruction
• ADR:
• To load registers with the addresses of memory locations we can also use the ADR pseudo-
instruction which has a better performance.
• ADR has the following syntax: ADR Rn, label
• For example, in Program 2-3A we can load R2 with the address of OUR_FIXED_DATA using
the following pseudo-instruction:
• ADR R2, OUR_FIXED_DATA ;Point to OUR_FIXED_DATA .
• point to OUR_FIXED_DATA ALIGN This is used to make sure data is aligned in 32-bit word or
16-bit half word memory address.
• The following uses ALIGN to make the data 32-bit word aligned: ALIGN 4 ;the next
instruction is word (4 bytes) aligned …
• ALIGN 2 ;the next instruction is half-word (2 bytes) aligned … Example 2-7 shows the result
of using the ALIGN directive.

Use DCB and DCD to define byte-size and word-size
variables
• LDR R3, =MY_NUMBER ; Get the memory code 0x in R4...
• LDR R0,=HELLO_TXT address value of MY_NUMBER
• LDR R4, [R3] ; Get the value ; Get the starting memory address of HELLO_TXT
• BL PrintText ; Call a function called PrintText to display string MY_NUMBER
• DCD 0xHELLO_TXTDCB “Hellon”,0 ; null terminated string

With UAL, you can explicitly specify whether
a Thumb or a Thumb-2 instruction you want
by adding suffixes
• ADDS R0, #1 ; Use 16-bit Thumb instruction by default for smaller
size
• ADDS.N R0, #1 ; Use 16-bit Thumb instruction (N=Narrow)
• ADDS.W R0, #1 ; Use 32-bit Thumb-2 instruction (W=wide)
• Note: In most cases, applications will be coded in C, and the C
compilers will use 16-bit instructions if possible due to smaller code
size

32-bit Thumb-2 instructions can be half
word aligned
• 0x1000 : LDR r0,[r1] ; a 16-bit instructions (occupy 0x1000-0x1001)
• 0x1002 : RBIT.W r0 ; a 32-bit Thumb-2 instruction (occupy 0x ;
0x1005)
• Most of the 16-bit instructions can only access registers R0 to R7
• 32-bit Thumb-2 instructions do not have this limitation

ARM Cortex-M3 Memory System
• UNIT – V:
• ARM Cortex-M3 Instruction Set and Memory System
• Instruction Sets: ARM Cortex-M3 16-bit and 32-bit Instruction Set, Unified
Assembler Language, Data Processing Instructions, Branch Instructions, Load and
Store Instructions
• Memory System: Memory Maps, Memory Access Attributes, Default Memory
Access Permissions, Bit-Band Operations, Unaligned Transfers, Exclusive accesses,
Pipeline

ARM Cortex-M3 Memory System
• Memory Maps
• Memory Access Attributes
• Default Memory Access Permissions
• Bit-Band Operations
• Unaligned Transfers
• Exclusive accesses
• Pipeline

ARM Cortex-M3 MEMORY SYSTEM FEATURES
• The Cortex™-M3 processor has a predefined memory map that specifies which bus
interface is to be used when a memory location is accessed. This feature also allows
the processor design to optimize the access behavior when different devices are
accessed.
•Another feature of the memory system is the bit-band support. This provides
atomic operations to bit data in memory or peripherals. The bit-band operations are
supported only in special memory regions.
•The Cortex-M3 memory system also supports unaligned transfers and exclusive
accesses.
•The Cortex-M3 supports both little endian and big endian memory configuration.
•

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