![Immediate Offset Addressing
Base Register: Specify a register which contains the memory
address
❖ In case of the load instruction (LDR) this is the memory
address of the data that we want to retrieve from memory
❖ In case of the store instruction (STR), this is the memory
address where we want to write the value which is currently
in a register
Example: [r0]
specifies the memory address pointed to by the value in r0
The ARM data transfer instructions are all based around
register-indirect addressing, register being referenced is
called Base register
5 Engr.Sharif Kakar](https://image.slidesharecdn.com/ch6-200129022637/85/Memory-Access-Instructions-5-320.jpg)
![Illustration of LDR instruction Data Transfer
8
LDR 𝑅0 , [𝑅1] ;
load R0 with data from memory pointed by 𝑅1
Execution of the instruction LDR R0, [R1] will result in the
transfer of the 32-bit value pointed to by 𝑅1 in the destination
register 𝑅0.
In 1st step LDR instruction is fetched from code memory
region addressed by PC
This instruction is then decoded by the processor. After
decoding the instruction, the execution phase starts.
The first sub-step in the execution phase is to use the
contents of register 𝑅1 as an address, which is sent on the
data bus address lines to read the contents from the data
memory shown as 3 in fig. 6.2
Engr.Sharif Kakar](https://image.slidesharecdn.com/ch6-200129022637/85/Memory-Access-Instructions-8-320.jpg)
![Pre-indexed immediate offset addressing:
13
The presence of ‘!’ after the closing or right square
bracket ‘]’ indicates that the contents of the register
containing the base address are permanently updated and
distinguishes the pre-indexed addressing mode from the
immediate addressing mode.
Engr.Sharif Kakar](https://image.slidesharecdn.com/ch6-200129022637/85/Memory-Access-Instructions-13-320.jpg)
![LDR with PC- Relative Addressing Mode
21
In PC-Relative addressing mode, memory address is
generated using an offset from current value of PC
A label is used for representing an instruction address or
literal data in code memory region
LDR {type}{cond} 𝑅𝑡, Label
It is required that the label must be within an address
offset of ±4095 from the current instruction address.
Otherwise, the assembler generates an error
The assembler may also permit us to directly write the
label as [PC, #number]. The expression [PC, #number]
generates the label address by adding or subtracting an
offset equal to #number to the current value of PC.
Engr.Sharif Kakar](https://image.slidesharecdn.com/ch6-200129022637/85/Memory-Access-Instructions-21-320.jpg)
Memory Access Instructions
- 1. Memory Access Instructions Chapter 6 1 Engr.Sharif Kakar
- 2. Memory Access Instruction Topics Covered: ARM is a Load Store Architecture, all data processing instructions are executed in registers ❖ Does not support memory to memory data processing operations. ❖ Must move data values into registers before using them LDR / Memory to register or LOAD from memory to register STR / Register to memory or STORE from register to memory 3 sets of memory access instruction Single register data transfer(LDR/STR) Block data transfer(LDM/STM) Single data swap (SWP) 2 Engr.Sharif Kakar
- 3. Assembly Operands: Memory Memory: Think of as single one-dimensional array where each cell stores a byte size value Is referred to by a 32 bit address e.g. value at 0x4000 is 0x0a Data is stored in memory as: variables, arrays, structures In LDR instruction we studied Zero Extension Sign Extension 3 Engr.Sharif Kakar
- 4. Addressing Modes 4 There are many ways in ARM to specify the address; these are called addressing modes. Two modes associated with memory access instructions are 1. Immediate offset addressing 2. Register offset addressing The basic load and store instructions are: Load and Store Word or Byte or Half word ❖ LDR / STR / LDRB / STRB / LDRH / STRH Engr.Sharif Kakar
- 5. Immediate Offset Addressing Base Register: Specify a register which contains the memory address ❖ In case of the load instruction (LDR) this is the memory address of the data that we want to retrieve from memory ❖ In case of the store instruction (STR), this is the memory address where we want to write the value which is currently in a register Example: [r0] specifies the memory address pointed to by the value in r0 The ARM data transfer instructions are all based around register-indirect addressing, register being referenced is called Base register 5 Engr.Sharif Kakar
- 6. Immediate Offset Addressing 6 When the offset is an immediate value from the base address stored in a register, the resulting addressing mode is called immediate offset addressing. General syntax In immediate offset addressing mode contents of register 𝑅 𝑛 remain unchanged. Immediate value can be in between -255 to 255 in 16-bit encoding or -4095 to 4095 in 32-bit encoding Engr.Sharif Kakar
- 7. Data Types for LDR/STR Instruction Transfer data from memory to processor and vice versa, The data item may be a byte, 16-bit half-word, a 32-bit word Data types available and their range given in table 6.2 When type field is not specified transfer of 32-bit take place 7 Engr.Sharif Kakar
- 8. Illustration of LDR instruction Data Transfer 8 LDR 𝑅0 , [𝑅1] ; load R0 with data from memory pointed by 𝑅1 Execution of the instruction LDR R0, [R1] will result in the transfer of the 32-bit value pointed to by 𝑅1 in the destination register 𝑅0. In 1st step LDR instruction is fetched from code memory region addressed by PC This instruction is then decoded by the processor. After decoding the instruction, the execution phase starts. The first sub-step in the execution phase is to use the contents of register 𝑅1 as an address, which is sent on the data bus address lines to read the contents from the data memory shown as 3 in fig. 6.2 Engr.Sharif Kakar
- 9. LDR Instruction 9 Engr.Sharif Kakar
- 10. LDR Instruction 10 4th step: For the LDR instruction, a read signal is sent on the control bus to the data memory and as a result 32 bits are copied by the memory (from the corresponding address) on the data lines of the data bus 5th step: Finally, the data from the data bus is copied to the register 𝑹𝟎 and this phase completes the execution of the instruction. During the execution of this instruction, the contents of register 𝑅1 are not changed Engr.Sharif Kakar
- 11. Web link https://www.youtube.com/watch?v=07ATOG5wXPE 11 Engr.Sharif Kakar
- 12. Immediate Offset Addressing 12 Immediate Addressing mode can be divided into 1. Pre-indexed immediate offset addressing 2. Post-indexed immediate offset addressing Pre-indexed immediate offset addressing: In pre- indexed offset addressing the base address is updated first. This updated address is used by STR/LDR instruction during execution. General Syntax Engr.Sharif Kakar
- 13. Pre-indexed immediate offset addressing: 13 The presence of ‘!’ after the closing or right square bracket ‘]’ indicates that the contents of the register containing the base address are permanently updated and distinguishes the pre-indexed addressing mode from the immediate addressing mode. Engr.Sharif Kakar
- 14. Post-index offset addressing 14 If the base address contained in the address register is updated after the load or store operation has been performed, then this addressing mode is called the post- index offset addressing mode. Example: Engr.Sharif Kakar
- 15. Example 6.5 15 (Copying single data at a time with post-indexing.). Assume Src to be an array of numbers in the memory section with READONLY attribute while Dst is an array in the READWRITE memory section.We want to copy the elements of Src to Dst using post-indexing. Engr.Sharif Kakar
- 16. Register Offset Addressing 16 In this addressing mode, the base address is contained in a register while the offset value is also in a register.This is unlike immediate offset addressing mode, where the offset is an immediate value. Rn contains the base address to or from which an offset contained in Rm is added or subtracted.The offset n is a optional value and can be shifted by 0 to 3bits with left shift logical operation. Engr.Sharif Kakar
- 17. Aligned and unaligned memory access 17 A 32-bit word object will result in an aligned word access if the first two bits of its starting address are zero or if it is divisible by 4. Otherwise, the 32-bit data access is unaligned. Similarly, if the starting address of a 16-bit half word object is divisible by 2 or its LSB is zero, we say the 16-bit object is half-word aligned. Otherwise, its access will be unaligned. Memory accesses of size 1 byte are, however always aligned. Example 6.7 see exercise also Engr.Sharif Kakar
- 18. 6.6 Stack 18 Covered on board, kindly see lecture notes Engr.Sharif Kakar
- 19. 6.2.4: Unprivileged Load and Store instructions 19 Cortex-M processor can access the memory either in privileged or unprivileged mode Load and store instructions with unprivileged access can be used to mandate the applications running on top of the operating system to have only unprivileged access thus allow a restricted memory access to the application program. General Syntax: They perform same operation as LDR/STR with immediate offset value but have unprivileged access Engr.Sharif Kakar
- 21. LDR with PC- Relative Addressing Mode 21 In PC-Relative addressing mode, memory address is generated using an offset from current value of PC A label is used for representing an instruction address or literal data in code memory region LDR {type}{cond} 𝑅𝑡, Label It is required that the label must be within an address offset of ±4095 from the current instruction address. Otherwise, the assembler generates an error The assembler may also permit us to directly write the label as [PC, #number]. The expression [PC, #number] generates the label address by adding or subtracting an offset equal to #number to the current value of PC. Engr.Sharif Kakar
- 23. ADR instruction 23 ADR can be used to generate PC-relative addresses, it is used to load addresses to registers General Syntax: ADR { cond } Rd, label Here Rd is destination register, label is used for representing an instruction address. Example: ADR R2, TxtMsg Engr.Sharif Kakar
- 24. Double and Multiple Word Memory Access 24 In case memory data access becomes larger than word then there are 2 solutions 1. One of them is to use the existing word size memory access instruction repeatedly. 2. Cortex-M3 instruction allows either double or multiple load and store operations to be performed in single memory access instruction DoubleWord Memory Access General Syntax Engr.Sharif Kakar
- 25. Example 25 The first instruction in Example 6.18 loads register R1 with a word at an address obtained by adding an offset of 32 bytes to the value in register R2, and loads a word to R0 from an offset of 36 bytes. The second instruction stores R3 to an address in R7, and the register R4 to an address equal to R7 + 4 and then decrements R7 by 16 Engr.Sharif Kakar
- 26. Multiple Word Load and Store Instructions 26 Multiple registers can be loaded and stored using LDM (load multiple) and STM (Store Multiple) instructions addrmode can be Increament After (IA) and Decreament Before (DB), cond field is an optional field, 𝑹 𝒅 holds the base memory address from which multiple registers are loaded and stored. Reglist is the list of registers to be loaded or stored. {!} exclamation mark is an optional field and specifies whether Rd should be updated after instruction execution or not. Engr.Sharif Kakar
- 27. Multiple word load and Store instructions 27 Engr.Sharif Kakar
- 28. Multiple word Load and Store instructions 28 In the above examples, R0 is the first register to be copied to the memory, then R1 and in the end R3 is stored in the memory. The LDM instructions work in the opposite manner as compared to their STM counterparts.We may also encounter instructions such as LDMFD and STMFD.The LDM and LDMFD instructions are synonyms for LDMIA while STMFD is a synonym for STMDB. For LDM, LDMIA, LDMFD, STM, and STMIA, the accesses occur in order of increasing register numbers, with the lowest numbered register using the lowest memory address and the highest numbered register using the highest memory address. Engr.Sharif Kakar
- 29. Multiple Word Load and Store instruction 29 For LDMDB, LDMEA, STMDB, and STMFD, the accesses occur in order of decreasing register numbers, with the highest numbered register using the highest memory address and the lowest number register using the lowest memory address. Assignment : example 6.21 + exercise problems for paper Engr.Sharif Kakar