Embedded system and arm with different module

MODULE-5
Introduction to the ARM Instruction set

Contents
◦ Data processing Instructions
◦ Move Instructions
◦ Barrel Shifter
◦ Arithmetic Instructions
◦ Using the Barrel Shifter with Arithmetic Instructions
◦ Logical Instructions
◦ Comparison Instructions
◦ Multiply Instructions
◦ Branch Instructions
◦ Load-Store Instructions
◦ Software Interrupt Instructions
◦ Program Status Register Instructions
◦ Conditional Execution

Key points about ARM
ARM is a RISC machine.
There are 16 registers and all registers are 32bit in size.
ARM instructions process data held in registers but do not process
data stored in memory.
ARM instructions only access memory with load and store
instructions.
ARM instructions commonly take two or three operands.
In ARM instructions, 1st
operand is destination operand and remaining
operands are source operands.
ADD r3, r1,r2

We illustrate the processor operations using examples with pre and
post conditions, describing registers and memory before and after the
instruction or instructions are executed.
PRE < pre-conditions >
< instruction/s >
POST < post-conditions>
PRE r5=5
r7=8
MOV r7, r5
POST r5=5
r7=5

We will represent hexadecimal numbers with the prefix 0x and
binary numbers with the prefix 0b.
Constants are preceded by #
Example : MOV r1, #15
Memory is denoted as
Example: mem32[1024]
Rd is any Destination Register
Rs is any Source Register
Rn or Rm are any register from R0 to R15

Data Processing Instructions
• The data processing instructions manipulate data within
registers. They are
-move instructions
-arithmetic instructions
-logical instructions
-comparison instructions
-multiply instructions.
• Most data processing instructions can process one of their
operands using the barrel shifter.

• If you use the S suffix ona data processing
instruction, then it updates the flags in the cpsr.
• Move and logical operations update the carry flag
C, negative flag N, and zero flag Z.
• The carry flag is set from the result of thebarrel shift
as the last bit shifted out.
• The N flag is set to bit 31 of the result.
• The Z flag is set if the result is zero.

•Barrel Shifter
•A MOV instruction where N is a simple register.
•But N can be more than just a register or immediate
value; it can also be a register Rm that has been
preprocessed by the barrel shifter prior to being used
by a data processing instruction.
•Data processing instructions are processed within
the arithmetic logic unit (ALU). A unique and
powerful feature of the ARM processor is the ability
to shift the 32-bit binary pattern in one of the source
registers left or right by a specific number of
positions before it enters the ALU.

•This shift increases the power and flexibility of
many data processing operations.
•There are data processing instructions that do
not use the barrel shift, for example, the MUL
(multiply), CLZ (count leading zeros), and
QADD (signed saturated 32-bit add)
instructions.

Example: We apply a logical shift left (LSL) to register Rm before
moving it to the destination register. This is the same as applying the
standard C language shift operator to the register. The MOV
instruction copies the shift operator result N into register Rd. N
represents the result of the LSL operation.

Embedded system and arm with different module

1) Move Instructions
• Move is the simplest ARM instruction.
• It copies N into a destination register Rd, where N is a
register or immediate value.
• This instruction is useful for setting initial values and
transferring data between registers.

Example 1
Example 2
PRE r5= 0xA3 or r5= 0x000000A3 or 163
r7 =8
MVN r7, r5 ; let r7=~r5
POST r5=0xA3
r7=0xFFFFFF5C

Example-1
Subtract instruction subtracts a value stored in register r2 from
a value stored in register r1. The result is stored in register r0.

Example-2
Reverse Subtract Instruction (RSB) subtracts r1 from the
constant value #0, writing the result to r0. You can use this
instruction to negate numbers.

Example-3
SUBS instruction is useful for decrementing loop counters. In
this example we subtract the immediate value one from the
value one stored in register r1. The result value zero is written
to register r1. The cpsr is updated with the Z flag being set.

3) Logical Instructions
Logical instructions perform bitwise logical operations on
the two source registers.

Example-1
Logical OR operation between registers r1 and r2.
r0 holds the result.

Example-2
Logical bit clear (BIC)

4) Comparison Instructions
❑ The comparison instructions are used to compare or test a register with
a 32-bit value.
❑ They update the cpsr flag bits according to the result, but do not affect
other registers.
❑ After the bits have been set, the information can then be used to change
program flow by using conditional execution.

CMN Instruction
The CMN instruction adds thevalue of N to the value in Rn.
This is thesame as an ADDS instruction, except that the result is
discarded.
The conditional flags are updated accordingly.
RO=50
R1=10
CMN RO, R1

TEQ Instruction
❑ The Test Equivalence instruction performs a bitwise Exclusive OR
operation on the value in Rn and the value of N. The result is
discarded.
❑ Use the TEQ instruction to test if two values are equal, without
affecting the V or C flags (as CMP does). It affects the N and Z flags.

TST Instruction
❑ This instruction tests the value in a register against N. It updates the
condition flags on the result, but does not place the result in any register.
❑ The TST instruction performs a bitwise AND operation on the value in Rn
and the value of N.
❑ This is the same as an ANDS instruction, except that the result is
discarded.

5) Multiply Instructions (32-bit
product)
The multiply instructions multiply the contents of a
pair of registers.

Multiply Instruction (64-bit product)

Barrel Shifter
• In MOV instruction N is a simple register / immediate value.
• It can also be a register Rm that has been preprocessed by the barrel
shifter prior to being used by a data processing instruction.
• Majority of the data processing instructions are processed within the ALU.
• A unique and powerful feature of the ARM processor is the ability to shift
the 32-bit binary pattern in one of the source registers left or right by a
specific number of positions before it enters the ALU.
• This shift increases the power and flexibility of many data processing
operations.
• There are data processing instructions that do not use the barrel shift, for
example,
-- MUL (multiply),
-- CLZ (count leading zeros)
-- QADD (signed saturated 32-bit add)

Barrel Shifter operation syntax for data processing instructions
Immediate : Rm
, shift #x
Register : Rm
, shift Rs

Using the Barrel Shifter with Arithmetic Instructions

Branch Instructions
• A branch instruction changes the flow of execution or
is used to call a routine.
• This type of instruction allows programs to have
subroutines, if-then-else structures and loops.
• The change of execution flow forces the program
counter pc to point to a new address.

The ARM v5E instruction set includes 4 different branch instructions:
•The label is the address stored in the instruction as a signed pc-relative offset and must be within
approximately 32 MB of the branch instruction.
•T refers to the Thumb bit in the cpsr.
•When instructions set T, the ARM switches to Thumb state.

Forward and Backward Branch
• These loops are address specific, we do not include the pre and
post-conditions.
• In the following example the forward branch skips three instructions. The
backward branch creates an infinite loop.

BL (Branch with Link Instruction)
• BL instruction is similar to the B instruction but overwrites the link register lr
with a return address. It performs a subroutine call.
• Example

BX(Branch Exchange), BLX(Branch Exchange with Link)
The BX instruction uses an absolute address stored in register Rm.
• It is used to branch to and from Thumb code.
• The T bit in the cpsr is updated by the Least Significant Bit of the branch register pc=Rm&0xfffffffe, T = Rm
& 1.
• Similarly the BLX instruction updates the T bit of the cpsr with the Least Significant Bit and
additionally sets the link register with the return address.
•pc = label, T = 1
•pc = Rm & 0xfffffffe, T = Rm & 1
•lr = address of the next instruction after the BLX

BL and BLX instructions can copy the address of the next
instruction to Link Register (r14).
BX and BLX instructions can change the state of the
processor from ARM to Thumb or from Thumb to ARM.
BLX Label always changes the state of the processor in any
case.

Load-Store Instructions
▪Load-store instructions transfer data between memory and processor
registers.
▪There are three types of load-store instructions:
1) single-register transfer
2) multiple-register transfer and
3) swap

1) Single-Register Transfer
These instructions are used for moving a single data item in and out
of a register.
The datatypes supported are signed and unsigned words (32-bit),
halfwords (16-bit), and bytes.

Example 3.15
This example shows a load from a memory address contained in
register r1, followed by a store back to the same address in memory.

▪Single-Register Load-Store Addressing Modes
▪The ARM instruction set provides different modes for addressing
memory.
▪These modes incorporate one of the indexing methods:
▪pre index with write back
▪Pre index
▪Post index

Multiple-Register Transfer
Load-store multiple instructions can transfer multiple registers between
memory and the processor in a single instruction. The transfer occurs
from a base address register Rn pointing into memory.
Load-store multiple instructions can increase interrupt latency. ARM
implementations do not usually interrupt instructions while they are
executing. For example, on an ARM7 a load multiple instruction takes
2+Nt cycles, where N is the number of registers to load and t is the
number of cycles required for each sequential access to memory.

Software Interrupt Instruction
• A software interrupt instruction - (SWI)
• This causes a software interrupt exception
• Provides a mechanism for applications to call operating system
routines.

When the processor executes an SWI
instruction, it sets the program counter pc to the
offset 0x8 in the vector table.
The processor mode changes to SVC, which
allows an operating system routine to be called
in a privileged mode.
Each SWI instruction has an associated SWI
number, which is used to represent a particular
function call or feature.

Program Status Register Instructions
• The ARM instruction set provides two instructions to directly
control a program status register (psr).
• The MRS instruction transfers the contents of either the cpsr or
spsr into a register; in the reverse direction
• The MSR instruction transfers the contents of a register into the
cpsr or spsr.
• Together these instructions are used to read and write the cpsr and

MRS, MSR Syntax
In the syntax you can see a label called fields. This can be any
combination of Control(c), Extension (x) , Status (s) and Flags(f).

Example
•The MSR first copies the cpsr into register r1.
•The BIC instruction clears bit 7 of r1.
•Register r1 is then copied back into the cpsr, which enables IRQ interrupts.
•This code preserves all the other settings in the cpsr and only modifies the I bit in
the control field.
•This example is in SVC mode. In user mode you can read all cpsr bits, but you can
only update the condition flag field f.

Coprocessor Instructions
• Coprocessor instructions are used to extend the instruction set.
• A coprocessor provides
✔ Additional computation capability
✔ Used to control the memory subsystem including caches & memory management
• The coprocessor instructions include
-data processing
-register transfer
-memory transfer instructions
Note that these instructions are only used by cores with a coprocessor

Coprocessor Instruction Syntax
•The cp field represents the coprocessor number between p0 and p15.
•The opcode fields describe the operation to take place on the coprocessor.
•The Cn, Cm and Cd fields describe registers within the coprocessor.
•Coprocessor 15 (CP15) is reserved for systemcontrol purposes, such as memory
management, write buffer control, cache control and identification registers.

Example
This example shows a CP15 register being copied into a general
–purpose register.
• Here CP15 register-0 contains the processor identification
number. This register is copied into the general-purpose register
r10.

Coprocessor 15 Instruction Syntax
CP15 is called the “ System Control Processor”.
Both MRC and MCR instructions are used to read and write to CP15, where register Rd is the core destination
register, Cn is the primary register, Cm is the secondary register (extended register) and opcode 2 is a secondary
register modifier.
Here is the instruction to move the contents of CP15 control register C1 into register r1 of the processor core:
MRC p15, 0, r1, c1. c0, 0
The reference notation uses the following format:
CP15:cX:cY:Z where X-Primary(0-15) , Y-Secondary register(0-15), last term is opcode2 instruction
modifier (0-7)
CP15:w:cX:cY:Z where w- non zero value of opcode 1

Single–Register Load-Store Addressing Modes

Stack Operations
• The ARM architecture uses the load-store multiple instructions to carry
out stack operations.
---The pop operation (removing data from a stack) uses a load
multiple instruction
----The push operation (placing data onto the stack) uses a store
multiple instruction
• We have to decide whether the stack will grow up or down in memory. A
stack is either
-- Ascending (A) or
-- Descending (D)
Ascending stack grows towards higher memory addresses
Descending stack grows towards lower memory addresses

• In full stack (F), the stack pointer sp points to an address that is the last used
or full location (i.e., sp points to the last item on the stack).
• In an empty stack (E) the sp points to an address that is the first
unused or empty location (i.e., it points after the last item on the stack).

Example-STMFD
• The STMFD instruction pushes registers onto the stack, updating the sp.
Below example push onto a full descending stack.
• When the stack grows the stack pointer (sp) points to the last full entry in the
stack. Hence it is called as full and descending because address decreases.

Example-STMED
The STMED instruction pushes the registers onto the stack but updates register
sp to point to the next empty location downward.

Checking Stack Overflow
• In handling the stack there are three attributes that need to be preserved:
– The stack base
– The stack pointer and
– The stack limit
• The stack base is the starting address of the stack in memory.
• The stack pointer initially points to the stack base; as data is pushed onto
the stack, the stack pointer descends memory and continuously points to
the top of stack.
• If the stack pointer passesthe stack limit, then a stack overflow
occurs

Embedded system and arm with different module

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