Dac, adc architecture
- 1. DAC, ADC architecture Resource CMOS Circuit Design, Layout and Simulation R. Jacob Baker SIES GRADUATE SCHOOL OF TECHNOLOGY
- 3. Resistor String DAC • The most basic DAC is seen in fig. Comprised of a simple resistor string of 2 𝑁 identical resistors and switches, the analog output is simply the voltage division of the resistors at the selected tap. • Note that a N: 2 𝑁 decoder is required to provide the 2 𝑁 signals controlling the switches. This architecture typically results in good accuracy, provided that no output current is required and that the values of the resistors are within the specified error tolerance of the converter. • One big advantage of a resistor string is that the output is always guaranteed to be monotonic. • One problem with this converter is that the converter output is always connected to 2 𝑁 - 1 switches that are off and one switch that is on. For larger resolutions, a large parasitic capacitance appears at the output node, resulting in slower conversion speeds
- 4. • A better alternative for the resistor-string DAC is seen in Fig. near. Here, a binary switch array ensures that the output is connected to at most N switches that are on and N switches that are off, thus increasing conversion speed. • The input to this switch array is a binary word since the decoding is inherent in the binary tree arrangement of the switches. • Another problem with the resistor-string DAC is the balance between area and power dissipation. An integrated version of this converter leads to a large chip area for higher bit resolutions because of the large number of passive components needed. • Active resistors such as the n-well resistor can be used for low-resolution applications. However, as the resolution increases, the relative accuracy of the resistors becomes an important factor. • Although the value of R could always be made small to minimize the chip area required, power dissipation would then become the critical issue as current flows through the resistor string at all times
- 5. • Example
- 6. Mismatch Errors Related to the Resistor-String DAC • The accuracy of the resistor string is obviously related to matching between the resistors, • which ultimately determines the INL and DNL for the entire DAC. • Suppose that the 𝑖 𝑡ℎ resistor, 𝑅𝑖, has a mismatch error associated with it so that 𝑅𝑖 = 𝑅 + Δ𝑅𝑖 where R is the ideal value of the resistor and Δ𝑅𝑖 is the mismatch error • Also suppose that the mismatches were symmetrical about the string so that the sum of all the mismatch terms were zero, i.e 𝑖=1 2 𝑁 Δ𝑅𝑖 = 0 • The value of the voltage at the tap associated with the 𝑖 𝑡ℎ resistor should ideally be (When all resistors are identical) 𝑉𝑖, 𝑖𝑑𝑒𝑎𝑙 = 𝑖 𝑉𝑟𝑒𝑓 2 𝑁 𝑓𝑜𝑟 𝑖 = 0,1,2, … . . , 2 𝑁 − 1 • However, including the mismatch, the actual value of the 𝑖 𝑡ℎ voltage is the sum of all of the resistances up to and including resistor i, divided by the sum of all of the resistances in the string. This can be represented by
- 7. finally, the value of the voltage at the i-th tap is • Integral Nonlinearity of the Resistor-String DAC – Integral nonlinearity (INL) is defined as the difference between the actual and ideal switching points i.e. 𝐼𝑁𝐿 = 𝑉𝑖 − 𝑉𝑖, 𝑖𝑑𝑒𝑎𝑙 – Thus from previous equations we get
- 8. • condition that will ensure a worst-case scenario is to consider the lower half resistors at their maximum positive mismatch value and the upper half resistors at their maximum negative mismatch value, or vice versa Where 𝐿𝑆𝐵 = 𝑉 𝑟𝑒𝑓 2 𝑁 and % 𝑚𝑎𝑡𝑐ℎ𝑖𝑛𝑔 = Δ𝑅 𝑅
- 9. • Differential Nonlinearity of the Worst-Case Resistor-String DAC – DNL is simply the actual height of the stair-step in the DAC transfer curve minus the ideal step height, – The actual difference between step heights is This can be simplified as The DNL can then be determined by subtracting the ideal step height
- 10. An R-2R digital-to-analog converter. • Figure illustrates an N-bit R-2R ladder. • Starting at the right end of the network, notice that the resistance looking to the right of any node to ground is 2R. • The digital input determines whether each resistor is switched to ground (non inverting input) or to the inverting input of the op-amp. • The total current flowing from 𝑉𝑟𝑒𝑓 is constant, since the potential at the bottom of each switched resistor is always zero volts (either ground or virtual ground). Therefore, the node voltages remain constant for any value of the digital input. • The output voltage, 𝑉𝑜𝑢𝑡 , depends on currents flowing through the feedback resistor, 𝑅 𝐹, such that 𝑉𝑜𝑢𝑡 = −𝑖 𝑡𝑜𝑡𝑎𝑙 𝑅 𝐹 Where 𝑖 𝑡𝑜𝑡𝑎𝑙 is the sum of the currents selected by the digital input by
- 11. • Example
- 12. Current Steering DAC • In the R-2R DAC section, a voltage was converted into a current, which then generated a voltage at the output. Another DAC method uses current throughout the conversion. Known as current steering, this type of DAC requires precision current sources that are summed in various fashions • Above Figure illustrates a generic current-steering DAC. This configuration requires a set of current sources, each having a unit value of current, 𝐼. Since there are no current sources generating 𝐼 𝑜𝑢𝑡when all the digital inputs are zero, the MSB, 𝐷2𝑁−2 , is offset by two index positions instead of one. For example, for a 3-bit converter, seven current sources will be needed, labeled from 𝐷0 to 𝐷6. The binary signal controls whether or not the current sources are connected to either 𝐼 𝑜𝑢𝑡 or some other summing node (in this case ground). The output current, 𝐼 𝑜𝑢𝑡, has the range of 0 ≤ 𝐼 𝑜𝑢𝑡 ≤ 2 𝑁 − 1 𝐼
- 13. • Another current-steering architecture is seen in below. This architecture uses binary-weighted current sources, thus requiring only N current sources of various sizes versus 2 𝑁 − 1 sources in the previous example. • Since the current sources are binary weighted, the input code can be a simple binary number with no thermometer encoder needed.
- 14. • One advantage of the current-steering DACs is the high- current drive inherent in the system. Since no output buffers are necessary to drive resistive loads, these DACs are typically used in high-speed applications • Mismatch Errors Related to Current-Steering DACs – Analysis of the mismatch associated with the current sources is similar to the resistor string analysis Assume that 𝐼𝑖 = 𝐼 + Δ𝐼𝑖 𝑓𝑜𝑟 𝑖 = 0,1,2, … . . , 2 𝑁 − 1 • where 𝐼 is the ideal value of the current and Δ𝐼𝑖 is the error due to mismatch. • If it is again assumed that the Δ𝐼𝑖 terms sum to zero and that one-half of the current sources contain the maximum positive mismatch, Δ𝐼𝑖,𝑚𝑎𝑥 , and the other half contains the maximum negative mismatch, -Δ𝐼𝑖,𝑚𝑎𝑥. • Since the INL is simply the actual output current minus the ideal, the worst-case INL is
- 15. • The DNL is easily obtained since the step eight in the transfer curve is equivalent to the value of the ideal current source,𝐼. The maximum difference between any two adjacent values of output current will simply be the value of the single source, 𝐼 𝑘, • Thus maximum DNL is given by
- 16. Charge-Scaling DACs • A very popular DAC architecture used in CMOS technology is the charge-scaling DAC. • As Shown in Fig. above, a parallel array of binary-weighted capacitors, totaling 2 𝑁 𝐶, is connected to an op-amp. The value, C, is a unit capacitance of any value. After initially being discharged, the digital signal switches each capacitor to either 𝑉𝑟𝑒𝑓or ground, causing the output voltage, 𝑉𝑜𝑢𝑡, to be a function of the voltage division between the capacitors. • The capacitor array totals 2 𝑁 𝐶. Therefore, if the MSB is high and the remaining bits are low, then a voltage divider occurs between the MSB capacitor and the rest of the array. The analog output voltage, 𝑉𝑜𝑢𝑡, becomes In general 𝑉𝑜𝑢𝑡 is given by
- 18. Example
- 19. Cyclic DAC
- 20. • The cyclic DAC uses only a couple of simple Components to perform the conversion. As seen in Fig. in previous slide, a summer adds 𝑉𝑟𝑒𝑓or ground to the feedback signal depending on the input bits. • An amplifier with a gain of 0.5 feeds the output voltage back to the summer such that the output at the end of each cycle depends on the value of the output during thecycle before. • Notice that the input bits must be read in a serial fashion. Therefore, the conversion is performed one bit at a time, resulting in N cycles required for each conversion. • The voltage output at the end of the M 𝑡ℎ cycle of the conversion can be written as
- 21. • The accuracy of this converter is dependent on several factors. – The gain of the 0.5 amplifier needs to be highly accurate (to within the accuracy of the DAC) and is usually generated with passive capacitors. – Similarly, the summer and the sample-and-hold also need to be N-bit accurate • Example – For Input bits 𝐷5 𝐷4 𝐷3 𝐷2 𝐷1 𝐷0=110101 and 𝑉𝑟𝑒𝑓 = 5 𝑉
- 22. Pipeline DAC • The cyclic converter presented in the last section takes N clock cycles per N-bit conversion. Instead of recycling the output back to the input each time, we could extend the cyclic converter to N stages, where each stage performs one bit of the conversion. • This extension of the cyclic converter is called a pipeline DAC and is seen in Fig. above. • Here, the signal is passed down the "pipeline," and as each stage works on one conversion, the previous stage can begin processing another. Therefore, an initial N clock cycle delay is experienced as the signal makes its way down the pipeline the very first time. After the N clock cycle delay, a conversion takes place at every clock cycle. • Besides the N clock cycle delay, this architecture can be very fast • However, the amplifier gains must be very accurate to produce high resolutions • Also, this architecture uses N times more circuitry than that of the cyclic, so there is a trade-off between speed and chip area. • The output voltage of the «-th stage in the converter can be written as
- 23. • The operation of each stage in the pipeline can be summarized as follows – if the input bit is a 1, add 𝑉𝑟𝑒𝑓to the output of the previous stage, divide by two, and pass the value to the next stage. – If the input bit is a 0, simply divide the output of the previous stage by two and pass along the resulting value.
- 25. Flash ADC • Flash or parallel converters have the highest speed of any type of ADC. As seen in Fig, they use one comparator per quantization level (2 𝑁 - 1) and 2 𝑁 resistors (a resistor-string DAC). • The reference voltage is divided into 2N values, each of which is fed into a comparator. • The input voltage is compared with each reference value and results in a thermometer code at the output of the comparators. • A thermometer code exhibits all zeros for each resistor level if the value of 𝑣 𝑚 is less than the value on the resistor string, and ones if 𝑣𝐼𝑁 is greater than or equal to voltage on the resistor string. • A simple 2 𝑁 − 1: 𝑁 digital thermometer decoder circuit converts the compared data into an N-bit digital word.
- 27. • The obvious advantage of this converter is the speed with which one conversion can take place. Each clock pulse generates an output digital word. • The advantage of having high speed, however, is counterbalanced by the doubling of area with each bit of increased resolution. For example, an 8-bit converter requires 255 comparators, but a 9-bit ADC requires 511! • Flash converters have traditionally been limited to 8-bit resolution with conversion speeds of 10-40 Ms/s using CMOS technology. • The disadvantages of the Flash ADC are the area and power requirements of the 2 𝑁 - 1 comparators. • The speed is limited by the switching of the comparators and the digital logic.
- 28. • Accuracy Issues for the Flash ADC – Accuracy depends on the matching of the resistor string and the input offset voltage of the comparators – an ideal comparator should switch at the point at which the two inputs, 𝑣+ and 𝑣− , are the same potential. However, the offset voltage, 𝑉𝑜𝑠, prohibits this from occurring as the comparator output switches states as follows: 𝑉0 = 1 𝑤ℎ𝑒𝑛 𝑉+ ≥ 𝑉− + 𝑉𝑜𝑠 𝑉0 = 0 𝑤ℎ𝑒𝑛 𝑉+ < 𝑉− + 𝑉𝑜𝑠
- 29. • We know from N bit resistor string DAC the value of the voltage at the 𝑖 𝑡ℎ tap is Where 𝑉𝑖,𝑖𝑑𝑒𝑎𝑙= voltage at the 𝑖 𝑡ℎ tap if all the resistors had an ideal value of R, Δ𝑅 𝑘 is value of resistance error due to mismatch, • Then switching point of 𝑖 𝑡ℎ comparator becomes 𝑉𝑠𝑤,𝑖 = 𝑉𝑖 + 𝑉𝑜𝑠,𝑖 Where 𝑉𝑜𝑠,𝑖 is input offset voltage of 𝑖 𝑡ℎ comparator • Then INL is given by • The worst-case INL will occur at the middle of the string (i = 2 𝑁−1), as described for R-2R DAC. Including the offset voltage, the maximum INL will be
- 30. • DNL – Using the definition of DNL, But 𝑉𝑠𝑤,𝑖 = 𝑉𝑖 + 𝑉𝑜𝑠 ,𝑖 thus Which can be written as • The maximum DNL will occur, assuming Δ𝑅𝑖 is at its maximum, and 𝑉𝑜𝑠,𝑖 at its maximum positive value, and 𝑉𝑜𝑠,𝑖 is at its maximum negative voltage Thus
- 31. A two-step Flash ADC. • Another type of Flash converter is called the two-step Flash converter or the parallel, feed-forward ADC. • The basic block diagram of a two-step converter is seen in Fig. above. • The converter is separated into two complete Flash ADCs with feed-forward circuitry. • The first converter generates a rough estimate of the value of the input, and the second converter performs a fine conversion.
- 32. • The advantages of this architecture are that the number of comparators is greatly reduced from that of the Flash converter from 2 𝑁 − 1 comparators to 2(2 𝑁/2 − 1) comparators. For example, an 8-bit Flash converter requires 255 comparators, while the two-step Flash requires only 30. • The trade-off is that the conversion process takes two steps instead of one, with the speed limited by the bandwidth and settling time required by the residue amplifier and the summer. • Conversion process is as follows : 1. After the input is sampled, the most significant bits (MSBs) are converted by the first Flash ADC. 2. The result is then converted back to an analog voltage with the DAC and subtracted with the original input. 3. The result of the subtraction, known as the residue, is then multiplied by 2 𝑁/2 and input into the second ADC. The multiplication not only allows the two ADCs to be identical, but also increases the quantum level of the signal input into the second ADC. 4. The second ADC produces the least significant bits through a Flash conversion. • Figure below illustrates the two-step nature of the converter. The first conversion identifies the segment in which the analog voltage resides. This is also known as a coarse conversion of the MSBs. • The results of the coarse conversion are then multiplied by 2 𝑁/2 so that the segment within which 𝑉𝐼𝑁 resides will be scaled to the same reference as the first conversion. The second conversion is known as the fine conversion and will generate the final LSBs using the same Flash approach.
- 33. The Pipeline ADC • The pipeline ADC is an N-step converter, with 1 bit being converted per stage. • It is able to achieve high resolution (10-13 bits) at relatively fast speeds, • the pipeline ADC consists of N stages connected in series. • Each stage contains a 1-bit ADC (a comparator), a sample-and-hold, a summer, and a gain of two amplifier. Each stage of the converter performs the following operation: 1. After the input signal has been sampled, compare it to 𝑉 𝑟𝑒𝑓 2 . The output of each comparator is the bit conversion for that stage. 2. If 𝑣𝑖𝑛 > 𝑉 𝑟𝑒𝑓 2 (comparator output is 1), 𝑉 𝑟𝑒𝑓 2 is subtracted from the held signal and pass the result to the amplifier. If 𝑣𝑖𝑛 < 𝑉 𝑟𝑒𝑓 2 (comparator output is 0), then pass the original input signal to the amplifier. The output of each stage in the converter is referred to as the residue. 3. Multiply the result of the summation by 2 and pass the result to the sample and hold of the next stage.
- 34. Integrating ADCs Another type of ADC performs the conversion by integrating the input signal and correlating the integration time with a digital counter. Known as single- and dual-slope ADCs, these types of converters are used in high-resolution applications but have relatively slow conversions. However, they are very inexpensive to produce and are commonly found in slow-speed, cost-conscious applications.
- 35. • Figure in previous slide illustrates the single-slope converter in block level form. • A counter determines the number of clock pulses that are required before the integrated value of a reference voltage is equal to the sampled input signal. • The number of clock pulses is proportional to the actual value of the input, and the output of the counter is the actual digital representation of the analog voltage. • Since the reference is a DC voltage, the output of the integrator should start at zero and linearly increase with a slope that depends on the gain of the integrator. • Notice that the reference voltage is defined as negative so that the output of the inverting integrator is positive. • At the time when the output of the integrator surpasses the value of the S/H output, the comparator switches states, thus triggering the control logic to latch the value of the counter. • The control logic also resets the system for the next sample. • Figure near illustrates the behavior of the integrator output and the clock.
- 36. • Note that if the input voltage is very small, the conversion time is very short, as the counter has to increment only a few times before the comparator latches the data. • However, if the input voltage is at its full-scale value, the counter must increment to its maximum value of 2N clock cycles. Thus, the clock frequency must be many times faster than the bandwidth of the input signal. The conversion time, 𝑡 𝑐, depends on the value of the input signal and can be described as 𝑡 𝑐 = 𝑉𝑖𝑛 𝑉𝑟𝑒𝑓 2N Tclk • Where Tclk is the period of the clock. The sampling rate is inversely proportional to the conversion time and can be written as 𝑓𝑠𝑎𝑚𝑝𝑙𝑒 = 𝑉𝑟𝑒𝑓 𝑉𝑖𝑛2 𝑁 𝑓𝑐𝑙𝑘 • Accuracy Issues Related to the Single-Slope ADC – At the end of the conversion, the voltage across the integrating capacitor, 𝑉𝑐, Assuming no initial conditions is given by 𝑉𝑐 = 1 𝐶 0 𝑡 𝑐 𝑉𝑟𝑒𝑓 𝑅 𝑑𝑡 = 𝑉𝑟𝑒𝑓. 𝑡 𝑐 𝑅𝐶 where 𝑡 𝑐 is the conversion time. Thus we can write
- 37. • Above equation is a revealing one in that the final voltage on the integrator output depends not only on the value of the input voltage, which is to be expected, but also on the value of R, C, and 𝑓𝑠𝑎𝑚𝑝𝑙𝑒 . Therefore, any non ideal effects affecting these values will have an influence on the accuracy of the integrator output from sample to sample. • For example, if an integrated diffused-resistor is used, then the voltage coefficient of the resistor could limit the accuracy, since the resistor will be effectively nonlinear. Similarly, the capacitor may have charge leakage or aging effects associated with it. Also, any jitter in the clock will affect the overall accuracy. The integrator must have a linear slope to within the accuracy of the converter, which depends on the specifications of the op- amp (open- loop gain, settling time, offset, etc.) and must be considered accordingly. • Offset voltages on the comparator, the S/H, or the integrator result in additional or fewer clock pulses, depending on the polarity of the offset. A delay also exists from the time that the inputs to the comparator are equal and the time that the output of the counter is actually latched. The reference voltage must also stay constant to within the accuracy of the converter.
- 38. Dual slope ADC A slightly more sophisticated design known as the dual-slope, integrating ADC eliminates most of the problems encountered when using the single-slope converter. Here, two integrations are performed, one on the input signal and one on 𝑉𝑟𝑒𝑓 The input voltage in this case is assumed to be negative, so that the output of the inverting integrator results in a positive slope during the first integration.
- 39. • Above Figure illustrates the behavior for two separate samples. • The first integration is of fixed length, dictated by the counter, in which the sample-and-held signal is integrated, resulting in the first slope. • After the counter overflows and is reset, the reference voltage is connected to the input of the integrator. Since 𝑉𝑖𝑛 was negative and the reference voltage is positive, the inverting integrator output begins discharging back down to zero at a constant slope. • A counter again measures the amount of time for the integrator to discharge, thus generating the digital output. • Notice that the first slope varies according to the value of the input signal, while the second slope, dependent only on 𝑉𝑟𝑒𝑓, is constant. Similarly, the time required to generate the first slope is constant, since it is limited by the size of the counter. • However, the discharging period is variable and results in the digital representation of the input voltage.
- 40. • Accuracy Issues Related to the Dual-Slope ADC – The first integration period requires a full 2 𝑁 clock cycle and cannot be decreased, because the second integration might require the full 2 𝑁 clock cycles to discharge if the maximum value of 𝑉𝑖𝑛 is being converted. – However, the dual slope is the preferred architecture because the same integrator and clock are used to produce both slopes. – Therefore, any non idealities will essentially be canceled. For example, assuming that the S/H is ideal, the gain of the integrator at the end of the first integration period, 𝑇1 becomes – The output at the end of 𝑇1 is positive since the input voltage is considered to be negative and the integrator is inverting. After the clock has been reset, the discharging commences, with the initial condition defined by the value of the integrator output at the end of the charging period,
- 41. – Once the value of the integrator output, Vc, reaches zero volts – i.e. – At the end of the conversion, the dependencies on R and C have canceled out. Since we also know that the counter increments 2 𝑁 times at time, 𝑇1and the counter increments D times at time, 𝑇2, Eq. can be rewritten as where D is the counter output that is actually the digital representation of the input voltage. Thus, it can be written that the ratio of the input voltage and the reference voltage is proportional to the ratio of the binary value of the digital word, D, and 2 𝑁 . Therefore, since the same clock pulse is responsible for the charging and discharging times, any irregularities will also cancel out.
- 42. The Successive Approximation ADC The successive approximation converter performs basically a binary search through all possible quantization levels before converging on the final digital answer. The block diagram is seen above. An N-bit register controls the timing of the conversion where N is the resolution of the ADC. 𝑉𝐼𝑁 is sampled and compared to the output of the DAC. The comparator output controls the direction of the binary search, and the output of the successive approximation register (SAR) is the actual digital conversion.
- 43. • The successive approximation algorithm is as follows. 1. A 1 is applied to the input of the shift register. For each bit converted, the 1 is shifted to the right 1-bit position. 𝐵 𝑁−1 = 1 and 𝐵 𝑁−2 through 𝐵0= 0. 2. The MSB of the SAR, 𝐷 𝑁−1, is initially set to 1, while the remaining bits, 𝐷 𝑁−2through 𝐷0, are set to 0. 3. Since the SAR output controls the DAC and the SAR output is 100...0, the DAC output will be set to 𝑉 𝑟𝑒𝑓 2 . 4. Next, 𝑉𝑖𝑛 is compared to 𝑉 𝑟𝑒𝑓 2 . If 𝑉 𝑟𝑒𝑓 2 is greater than 𝑉𝑖𝑛, then the comparator output is a 0 and the comparator resets 𝐷 𝑁−1 to 0. If 𝑉 𝑟𝑒𝑓 2 is less than 𝑉𝑖𝑛, then the comparator output is a 1 and the 𝐷 𝑁−1 remains a 1. 𝐷 𝑁−1 is the actual MSB of the final digital output code. 5. The 1 applied to the shift register is then shifted by one position so that 𝐵 𝑁−2 while the remaining bits are all 0. 6. 𝐷 𝑁−2 is set to a 1, 𝐷 𝑁−3 through 𝐷0 remain 0, while 𝐷 𝑁−1 remains the value from the MSB conversion. The output of the DAC will now either equal 𝑉 𝑟𝑒𝑓 4 (if 𝐷 𝑁−1=0) or 3𝑉 𝑟𝑒𝑓 4 (if 𝐷 𝑁−1=1) 7. Next, 𝑉𝑖𝑛 is compared to the output of the DAC. If the DAC output is greater than 𝑉𝑖𝑛 then the comparator output drives 𝐷 𝑁−2 to 0. If the DAC output is less than 𝑉𝑖𝑛 then 𝐷 𝑁−2 remains a 1. 8. The process repeats until the output of the DAC converges to the value of 𝑉𝑖𝑛 within the resolution of the converter.