Day2 Open

The document outlines the topics to be covered on Day 2 of training which includes a review of electronic design and Boolean logic, an introduction to FPGA/CPLD devices, a Verilog HDL tutorial and running ModelSim, tools installation, and a Q&A session on using FPGA/CPLD. The day will also cover logic circuits, Verilog HDL basics for combinational logic, and a hands-on lab using ModelSim that is over 50% of the time. Resources on logic design from Altera and a note page from GFEC in traditional Chinese are also listed.