Day2 Logic Circuits

This document discusses logic circuits and their characteristics. It covers TTL and CMOS voltage levels, noise margins, propagation delays, fan-out, open collector/drain interfaces, Schmitt trigger inputs, and details about the MAX II FPGA such as its IO banks, power supplies, and IOE characteristics. Key topics include the voltage levels that define logic 1 and 0 for TTL and CMOS, noise margins that provide voltage tolerances, and timing specifications like propagation delays. Interface types like open drain and considerations for driving loads are also addressed.