Design and analysis of inexact floating point adders
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This document presents an inexact floating-point adder design aimed at reducing power consumption in nanoscale integrated circuits for error-tolerant applications. The proposed adder achieves significant improvements in power and power-delay product, with reductions of 29.98% and 39.60%, respectively, when tested on high dynamic range images. An upper bound error analysis is included to guide the design, indicating its dependence on the application data range.
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Design and analysis of inexact floating point adders
- 1. DESIGN AND ANALYSIS OF INEXACT FLOATING-POINT ADDERS ABSTRACT: Power has become a key constraint in nanoscale inte-grated circuit design due to the increasing demands for mobile computing and higher integration density. As an emerging compu-tational paradigm, an inexact circuit offers a promising approach to significantly reduce both dynamic and static power dissipation for error-tolerant applications. In this paper, an inexact floating-point adder is proposed by approximately designing an exponent sub-tractor and mantissa adder. Related operations such as normaliza-tion and rounding are also dealt with in terms of inexact computing. An upper bound error analysis for the average case is presented to guide the inexact design; it shows that the inexact floating-point adder design is dependent on the application data range. High dynamic range images are then processed using the proposed inexact floating-point adders to show the validity of the inexact design; comparison results show that the proposed inexact floating-point adders can improve the power consumption and power- delay product by 29.98% and 39.60%, respectively.