Design and analysis of inexact floating point adders
- 1. Design and Analysis of Inexact Floating-Point Adders ABSTRACT: Power has become a key constraint in nanoscale inte-grated circuit design due to the increasing demands for mobile computing and higher integration density. As an emerging compu-tational paradigm, an inexact circuit offers a promising approach to significantly reduce both dynamic and static power dissipation for error-tolerant applications. In this paper, an inexact floating-point adder is proposed by approximately designing an exponent sub-tractor and mantissa adder. Related operations such as normaliza-tion and rounding are also dealt with in terms of inexact computing. An upper bound error analysis for the average case is presented to guide the inexact design; it shows that the inexact floating-point adder design is dependent on the application data range. High dynamic range images are then processed using the proposed inexact floating-point adders to show the validity of the inexact design; comparison results show that the proposed inexact floating- point adders can improve the power consumption and power-delay product by 29.98% and 39.60%, respectively.
- 2. EXISTING SYSTEM: With advancement and development of innovative digital integrated circuits, power consumption has dramatically increased; power has become a key design constraint due to the high demand for mobile computing and higher integration density. Traditional designs ap-ply fully accurate computing to all types of applications; however, error-tolerant applications involving human intervention (such as image processing) do not require full accuracy. So, it is possible to perform computation with inexact circuits; in these cases, inexact computing *1+ is an attractive approach to save power and area, while achieving improved performance compared to accurate designs. The arithmetic unit is the core of a processor, and its power largely determines the power of the whole pro-cessor. Recent research on inexact fixed-point adders has shown that inexact processing hardware with a relative error of 7.58% can be nearly 15 times more efficient in terms of speed, area and energy product than an accu- rate chip *2+. Inexact chips are smaller, faster and con-sume less energy. Although fixed-point arithmetic cir-cuits have been studied in terms of inexact computing *2-8+, floating-point (FP) arithmetic circuits are signifi-cantly
- 3. more power hungry and they have not been fully considered for inexact computing. The FP format offers a high dynamic range for computationally intensive appli- cations; FP adders and multipliers are commonly used in DSP systems. However, its application to embedded DSP systems is limited due to the high power consump-tion. A low power design of an FP multiplier was investi-gated by Tong et al. *9+; this design involves the trunca-tion of hardware and a reduction of the bit width repre-sentation of the FP data. A probabilistic FP multiplier was proposed by Gupta et al. *10+ mostly as an energy efficient design. A lightweight FP design flow using bit-width optimization was proposed for low power signal processing applications *11+. Low precision FP numbers have also been used for MP3 decoding to reduce memory utilization and power consumption *12+. However, to the best of the authors' knowledge, there has been no research to date on an inexact FP adder design. PROPOSED SYSTEM: In this paper, adder designs are studied as a starting point for inexact FP arithmetic; several inexact adder designs are proposed and assessed for application to high dynamic range images. The upper bound error due to the inexact design is analyzed for the average case to guide the design of inexact FP adders. A
- 4. subjective visu-al difference predictor metric is used to measure the re-sults of image addition; moreover, a procedure is intro-duced for designing inexact FP arithmetic circuits. This paper is an extension of previous research by the authors in *13+; it improves on *13+ as follows: (1) The design of the inexact FP adder is discussed in more de-tail. (2) An upper bound error analysis is conducted for the average case to guide the inexact design of the FP adders and the error from each inexact part is analyzed. (3) The validity of the case studies is further illustrated based on the error analysis. (4) Detailed HDR-VDP met-rics (including both overall visibility and quality) are used to further illustrate the design results.
- 5. SOFTWARE IMPLEMENTATION: Modelsim 6.0 Xilinx 14.2 HARDWARE IMPLEMENTATION: SPARTAN-III, SPARTAN-VI