Truncated booth multiplier design of hdl
- 1. TRUNCATED BOOTH MULTIPLIER DESIGN OF APPROXIMATE COMPRESSORS USING VERILOG HDL
- 2. CONTENTS Abstract Introduction Literature review Existing Method Existing method simulation results Drawbacks Proposed method Advantages Hardware and Software Requirements
- 3. ABSTRACT In this work, In order to avoid the creation on hard multiples, the approximate radix-256 Booth encoding will be suggesting in this short. Partial product pairings are created using a partial encoding method and are simply acquired by shifting and complementing. The sum of each pair of matching partial products consequently takes the role of the precise encoding values. For performance testing, a 16/16-bit multiplier with the suggested radix-256 Booth encoding have been constructed The proposing method is coded in Verilog High Description Language (HDL), synthesized for Artix 7 Field-Programmable Gate Array (FPGA) board and simulated using Xilinx Vivado Design Suite.
- 4. INTRODUCTION We are aware that multipliers are used in all fundamental circuits. Today, multipliers are the foundation of every ALU system. The entire logical portion of complete arithmetic is predicated on a multiplier, and if the multiplier is taking too long, the entire product that is based on the multiplier will fail since the multiplier failed. A multiplier will operate slowly if its speed is low. Regarding this, if our function takes two seconds to complete, there will be a delay. The output then has a delay of at least two seconds. That delay could be longer than the standard performance delay.
- 5. In VLSI, power consumption, area, and latency all affect an IC's speed. When a circuit is complicated, there will be an increase in power consumption and latency. Another important power element is power usage. If we lower an IC's power factor, it indicates that the battery life of our device is good. Everyone uses computers and calculators today. Every manufacturer strives to develop low power consumption circuits in order to supply batteries with longer lives than their competitors
- 6. Literature review paper-1 Title : An area efficient high speed optimized FFT algorithm Authors :B. R. Manuel, E. Konguvel and M. Kannan Outcome : The main objective of this design is to reduce the power consumption by minimizing the number of multipliers required for FFT computation. This is achieved by rearranging and swapping the input terms, which leads to a reduced number of multipliers used in the computation process. The reduction in multipliers significantly contributes to lowering power consumption.
- 7. Literature review paper-2 Title : Design and Analysis of Approximate Multipliers for Error-Tolerant Applications Authors : Pandey, M. Reddy Karri, P. Yadav, N. K. Y.B. and V. M.H. Outcome : The paper focuses on the significance of approximate circuits in applications like image and video processing, where small errors in the output are imperceptible to human eyes. Approximate circuits enable the development of low-power and high-speed designs while maintaining acceptable output error levels
- 9. EXISTING METHOD Due to their straightforward and consistent compressor, topologies designs had been primarily employed to create practical multipliers. Following the first PPs being created by bit-wise ANDing multiplicand A and multiplier X. The precise p-q compressor uses aided carry-in/out values to decrease the number of PPs from p to q. In the instance of the 4-2 compressor, which was frequently employed in actual multiple-stage multipliers, two PPs are produced across two columns (yi and yi+1) by 4 PPs along the same i-th bit position, designated as ai, bi, ci, and di. More Power and Complex Design are disadvantages of the current system.
- 10. start End Count=0? A 0 M Divisor Q Dividend Count n Shift LEFT A,Q A A - M Count count-1 Q○ 0 A A+M Q○ 1 A<0? Booth Multiplier :
- 11. Existing method:
- 12. Existing method Simulation Results:
- 13. Simulation results: Area : Delay :
- 14. DISADVANTAGES Delay was created due to booth encoding, partial product generators and the compressors which are used in this method. In this booth multiplier area and power consumed more for multiplication process.
- 15. PROPOSED METHOD An around radix-256 Booth encoding is suggesting using a partial encoding strategy that makes use of carefully chosen partial product pairings to tackle challenging multiple difficulties and achieve a low error distance. The proposing Booth encoding-based multiplier design displays an improved performance-accuracy tradeoff. Simulation Outcome for Partial Product Generation on Radix 256 Booth Encoding & approximate Summation Unit, Design of the Booth Multiplier using Verilog HDL and Analysis of Area, time, and power using Xilinx. RTL Schematic View of Booth Multiplier seen in a Xilinx tool in this work booth multiplier is compared to the traditional booth multiplier and its decrease of the area in terms of slices, gates, and LUT. Gate and path delays are being reduced. It decreases in both static and dynamic power.
- 16. BLOCK DIAGRAM Partial product generator Adder Final product Encoder Multiplier B Multiplicant A Product A′B
- 17. ADVANTAGES •Performance of the circuit is minimized •Area and power consumption of the circuit is optimized.
- 18. HARDWARE AND SOFTWARE REQUIREMENTS Software: Xilinx vivado2018.3 HDL: Verilog