![Fast detectors
Moving charges:
i = n q v / d
Rise-time di/dt= q [ n dv/dt + dn/dt v]
collection multiplication
Maximize
n primary ionization, detector thickness
dv/dt qE/m electric field
- Electron multiplication
- High electric fields, segmented electrodes
- Reduce collection distance d
- Detector capacitance (signal/noise)
- Landau amplitude distribution (rise time spreads)
Bias
J-F Genat, LLN, Jan 16th 2008
d
transimpedance](https://image.slidesharecdn.com/lln6jfg-241012144726-4306dff1/85/design-and-simulation-and-implementation-17-320.jpg)
design and simulation and implementation
- 1. Strips and Pixels Detectors Associated Electronics Jean-François Genat LPNHE Paris Louvain la Neuve, Jan 16th 2008 J-F Genat, LLN Jan 2008
- 2. Outline J-F Genat, LLN, Jan 16th 2008 Solid-state vs Gaseous, basics Strips Timing Pixels Monolithic DEPFETs SOI Hybrids 3D detectors Readout electronics Perspectives
- 3. Solid state detectors vs Gaseous Gaseous Silicon Ionization energy 20 eV 3.6 eV Primary ionization 3e-/mm 60k e-/mm Amplification 100k No Exceptions: DEPFETs (APDs, Silicon PMTs) Carriers velocity 50 m/ns 500 m/ns (electrons) Signal processing No Yes integration Radiation hardness Yes No, if not designed for J-F Genat, LLN, Jan 16th 2008
- 4. Basic mechanisms Primary ionization Low electron-hole pair generation energy: 3.6 eV (Silicon) High loss/length: 1 MIP = 60k e-/mm Small range rays, high position resolution using thin detectors Collection - Drift under depletion field: reverse biased PN junction Voltage needed depends upon resistivity : high resistivity Silicon (1e4 /cm) to deplete at low voltages (100V) Drift velocity saturates: v = E, 1/ = Nq - Diffusion Total collected charge = primary ionization Unless reduced by : - recombination with impurities - radiation damage Current signal as large as: - number of moving carriers, - electric field (as high as closer to small electrodes) J-F Genat, LLN, Jan 16th 2008
- 5. Noises Sources of noise Parallel Detector leakage current Biasing resistor Series Electrode resistance input transistor (thermal, 1/f) « System » noise All other noises ! Reduce detector capacitance (segmentation helps) Use high good quality material (leakage current) Use appropriate shaping times Parallel 1/f Series f Input noise J-F Genat, LLN, Jan 16th 2008 H. Spieler http://www-physics.lbl.gov/~spieler/Heidelberg_Notes/pdf Charge amplifier
- 6. Outline J-F Genat, LLN, Jan 16th 2008 Solid-state vs Gaseous, basics Strips Timing Pixels Monolithic DEPFETs SOI Hybrids Semi-3D, 3D detectors Readout electronics Perspective
- 7. Silicon strips DC coupled Single sided Double sided DC or AC coupled n+ al al P+ n +V Amplifier bias voltage Single sided DC coupled DC leakage current flowing through amplifier may saturate particularly under irradiation J-F Genat, LLN, Jan 16th 2008 Fully depleted PN junction G. Lutz Semiconductor Radiation Detectors. Springer Verlag 2001
- 8. AC coupled strips AC coupled No DC flowing through insulated amplifiers Need for biasing resistors n+ al al P+ n +V 0V SiO2 20% more expensive ’’pinholes’’ through oxide J-F Genat, LLN, Jan 16th 2008
- 9. Silicon strips parameters Size 100 x 100 mm2 (6-8’’ wafers) DC or AC coupled Pitch 20-200m Substrate resistivity 2-10k/cm Capacitance to substrate 100fF/cm Interstrip capacitance 1pf/cm Full depletion voltage 60-100V Thickness 50-300 m Leakage current 50nA/cm2 at 100V bias Junction breakdown >200V Interstrip resistance > 2 G Edgeless < 10 m Defective strips <1% J-F Genat, LLN, Jan 16th 2008
- 10. Silicon strips space resolution Digital readout (ATLAS, CERN ABCD chips): m m Analog readout (CMS, RAL APV25 chips): Several adjacent strips collect the signal: Centroids Improved space resolution: = <10 m J-F Genat, LLN, Jan 16th 2008 12 ATLAS Unno et al. NIM A453 pp109-120 CMS K. Klein. IECHEP 2005, Lisboa
- 11. Magnetic field effect J-F Genat, LLN, Jan 16th 2008 (S. Cucciarelli) Degrades space resolution
- 12. Silicon strips modules J-F Genat, LLN, Jan 16th 2008 CMS (K. Klein) Radiation hardness is a big issue, as close to the beam
- 13. Outline J-F Genat, LLN, Jan 16th 2008 Solid-state vs Gaseous, basics Strips Timing Pixels Monolithic DEPFETs SOI Hybrids 3D detectors Readout electronics Perspective
- 14. Timing J-F Genat, LLN, Jan 16th 2008 The faster detector and front-end electronics, The better the timing Obvious, but still to keep in mind…
- 15. Rise time and noise A Threshold 1 Slope 1/ A t . A t A . A t noise Effects of noise t Time spread proportional to rise-time and noise J-F Genat, LLN, Jan 16th 2008
- 16. Amplitude, rise-time Amplitude and/or Rise-time spectra translate into time spread J-F Genat, LLN, Jan 16th 2008
- 17. Fast detectors Moving charges: i = n q v / d Rise-time di/dt= q [ n dv/dt + dn/dt v] collection multiplication Maximize n primary ionization, detector thickness dv/dt qE/m electric field - Electron multiplication - High electric fields, segmented electrodes - Reduce collection distance d - Detector capacitance (signal/noise) - Landau amplitude distribution (rise time spreads) Bias J-F Genat, LLN, Jan 16th 2008 d transimpedance
- 18. Gaseous vs Silicon Signals (e-) Rise-time Time resolution Gaseous • MWPCs 106 3ns 500ps • RPCs 107 1ns 100ps Silicon • Strips 104 5 ns 2 ns • 3D Silicon 104 1ns ? • Silicon PMs 107 1 ns 100 ps J-F Genat, LLN, Jan 16th 2008
- 19. Time picking techniques J-F Genat, LLN, Jan 16th 2008 Time picking: Leading edge Zero crossing Constant fraction Multiple thresholds Sampling Leading edge vs CFD
- 20. Sampling vs CFD MATLAB Simulation with Silicon signals Better compared to CFD by a factor of two depending on noise properties and signal waveform statistics - MATLAB simulation package J-F Genat, LLN, Jan 16th 2008
- 21. Expected time resolution with Silicon Simulated time resolution using sampling - S/N =25 - 16 samples - 40 ns shaping 1 ns time resolution J-F Genat, LLN, Jan 16th 2008
- 22. Timing using Silicon strips M. Friedl et al NIM 572 pp 385-387 Using sampling at 25ns rate, digitization and signal processing, a time resolution of 2ns id obtained (CMS detectors + APV25 chip) using a deconvolution algorithm J-F Genat, LLN, Jan 16th 2008
- 23. Coordinate along the strip 15 ns LC V / 1 V = c/4.7 L =50nH R =5 Ci=500 fF Cs= 100 fF 120cm V = c/3.7 8 cm /ns SPICE J-F Genat, LLN, Jan 16th 2008
- 24. Measured Pulse Velocity 4.5 ns/cm Measured moving a laser diode along 24 cm Moving a laser diode along the Silicon strip detector Threshold V = 4.5cm/ns J-F Genat, LLN, Jan 16th 2008
- 25. Outline J-F Genat, LLN, Jan 16th 2008 Solid-state vs Gaseous, basics Strips Timing Pixels Monolithic DEPFETs SOI Hybrids 3D detectors Readout electronics Perspective
- 26. Monolithic Active Pixels Sensors (MAPS) Integrate pixel detector and readout electronics using a single standard opto CMOS process (cheap) Matrices of 25 x 25 microns pixels Built-in 2D device Detector segmentation highly improves Signal/noise Opto-CMOS allows pixel signal processing Slow collection (diffusion) Slow readout (unless on-pixel sparsifier implemented) Power needed by amplifiers (can be cycled) n+ n well p epi P sub J-F Genat, LLN, Jan 16th 2008 Dulinski et al. Trans Nucl Sci V49 N2 p601
- 27. DEPFETS One MOSFET on top of a fully depleted PN junction: MOSFET current is modulated by the deposited charges stored in the bulk under the channel: amplification . Multiple readout possible (reduced noise) using two ping-pong DEPFETs. Thickness down to 50 m 4000 e-/MIP Noise down to ¼ electrons ! Wolfel et al. NIMA253, 356-377 n+ p+ p p+ n+ n+ n+ p Source Gate Drain Clear Bulk Internal gate p+ 50 MIP --- +++ n- 1 G. Lutz Semiconductor Radiation Detectors. Springer Verlag 2001 J-F Genat, LLN, Jan 16th 2008 Gain: 500pA/e-
- 28. DEPFETS Readout J-F Genat, LLN, Jan 16th 2008 Readout chip • Current based • 3-fold sampling • Noise 45 nA (<100 e- equivalent) • Signal/noise = 40 • Mixed signal FIFO • Analog pedestal subtraction • Zero-suppression up to 110 MHz • 4.5 x 4.5 mm2 250nm CMOS M. Trimpl et al. NIMA 511 p257
- 29. Silicon on Insulator (SOI) Superimpose: - CMOS process on low resistivity Silicon - Oxide (100-200nm) - High resistivity Silicon (detector) - Allow connections through oxide PMOS n well p NMOS oxide n detector al p+ +HV gnd p+ gnd J-F Genat, LLN, Jan 16th 2008
- 30. SOI features Full thickness of fast collection detector High performance CMOS electronics available Availability of SOI wafers from industry (SOITEC) Processes available: Japan OKI 150nm, US ASI 180nm. 100% fill factor Not so radiation hard (oxide) Not so cheap J-F Genat, LLN, Jan 16th 2008
- 31. SOI pixels Fermilab pixel design: 64 x 64 matrix of 26 x 26 m counting pixels (12bit, max 1MHz) 350 m detector thickness Pixel includes: Amplifier 150 mV/1k e- CR-RC shaper150ns peaking time Discriminator 12bit counter ASI US OKI Japan (Numbers from Ray Yarema, FNAL) J-F Genat, LLN, Jan 16th 2008 Y.Arai et al. NSS 2007 N20-2 pp 1040
- 32. Hybrid pixels Flexibility for detector/electronics process choice Readout chips available (CERN), but fixed pixel size Radiation hard (as far as detector and electronics are, but the choice is more open) Pixel level bump bonding connexions J-F Genat, LLN, Jan 16th 2008 Mature technology
- 33. Hybrid pixels at LHC Detector and electronics as two independent Silicon structures ATLAS Vertex detector: - Detector: ATLAS rad-tol: Partially depleted n+ on_inverted_n on Fz-oxygenated Silicon after irradiation - Electronics: FE-I3 chip IBM 250nm (LBL Bonn CPPM) - Bump-bonding (Bonn – IZM) CMS Detector: Cz-oxygenated Electronics: IBM 250nm (PSI) J-F Genat, LLN, Jan 16th 2008 L. Cremaldi et al. NIM 511-1, pp64-67
- 34. FE-I3 chip (LBNL, Marseille, Bonn) • 18 x 160 pixels columns, active area 8 x 7.2mm2 • Time over threshold (7 bits) • Level 1 buffering: 3.2s. Max rate: 0.15 hit/BC/column pair=1.35 hit/BCO/chip. • Trigger output as a single fast OR bit of all (selectable) pixels. 50 m 7.4 mm 8 mm 10 m I/O pads 1100 mm 400 m 7.2mm 100 m Output data format: | Header 1 | BC Id 4 | row 8 |column 5 | Parity 1 | ToT 7 | J-F Genat, LLN, Jan 16th 2008
- 35. ATLAS pixel module • Pixel module (50,000 pixels) J-F Genat, LLN, Jan 16th 2008
- 36. Outline J-F Genat, LLN, Jan 16th 2008 Silicon detectors Solid-state vs Gaseous, basics Strips Timing Pixels Monolithic DEPFETs SOI Hybrids 3D detectors Readout electronics Perspective
- 37. 3D Silicon J-F Genat, LLN, Jan 16th 2008
- 38. 3D Silicon detectors Full 3D: Charges move parallel to the detector plane instead transverse, the field created using vertical electrodes through the detector (MEMS technology). Built-in pixels. Semi-3D: The backplane is still an electrode. Electrons are collected by vertical electrodes, holes by backplane. J-F Genat, LLN, Jan 16th 2008
- 39. 3D Active edges Silicon Full 3D: Both type of carriers collected by electrodes of two types Active edges allow sensitivity to 5 microns from the cut, Abutt detectors without dead zones. J-F Genat, LLN, Jan 16th 2008
- 40. 3D Silicon Collection distance reduced by 10: - Faster (1-2ns rise-time) - Position resolution down to 10-15 mm in the two dimensions. - Same collected charge (24k electrons/300 mm) - More radiation tolerant detectors (1015 n/cm2 ). - Depletion voltage reduced to a few Volts. Any connexions between electrodes are possible (as long as the total capacitance remains small, if not noise increases) - Active edges (conducting): edgeless capability down to 10 mm. - Readout using CMOS chips available at CERN (ATLAS pixels) - Moderate passive cooling. J-F Genat, LLN, Jan 16th 2008
- 41. Available 3D detectors Active area 50 m 7.4 mm 8 mm 10 m I/O pads 1100 mm 400 m 7.2mm 100 m 7.4 x 8mm2 detectors bump-bonded to FE13 chips (CERN) 400 x 50 m2 pixels Plans to reduce pixel size to 50 x 50 m2 J-F Genat, LLN, Jan 16th 2008
- 42. 220m Roman Pots at ATLAS IP 220m 8m One horizontal pot and two vertical pots at 216 and 224 m on each arm with detectors as close as possible to the beam: 10 = 1mm 3cm Silicon detectors One Horizontal pot Two Vertical pots J-F Genat, LLN, Jan 16th 2008
- 43. 3D Silicon detectors for RP 220 J-F Genat, LLN, Jan 16th 2008
- 44. Roman Pot Layout MCP-PMT Light Guide Radiator 8 x 8 Pixels Read Out ASIC 64 Ch. P. Le Dû X X 2,54 x 2,54 cm Beam 4,5 cm FE ASIC (PA,SH,Pipeline) Plus FAST OR Read out and Trigger LOGIC (FPGA) Power and Clock distribution Slow control Cooling To Alco ve Edgeless Silicon J-F Genat, LLN, Jan 16th 2008
- 45. Acceptance for diffracted protons Acceptance for diffracted p[rotons at 220m Simulation J-F Genat, LLN, Jan 16th 2008
- 46. 3D Silicon layout J-F Genat, LLN, Jan 16th 2008
- 47. Silicon Manufacturers Hamamatsu Japan Canberra Belgium SINTEF Norway 3D Micron UK CSEM Switzerland VTT Finland 3D CiS Germany IST Italy STM France J-F Genat, LLN, Jan 16th 2008
- 48. Outline J-F Genat, LLN, Jan 16th 2008 Solid-state vs Gaseous, basics Strips Timing Pixels Monolithic DEPFETs SOI Hybrids 3D detectors Readout electronics Perspective
- 49. Digital sampler chip for Silicon strips J-F Genat, LLN, Jan 16th 2008 Technology CMOS 130nm
- 50. Digital sampler architecture Storage Waveforms Technologies: Deep Sub-Micron CMOS 180-130nm Deep Sub-Micron CMOS LPNHE Paris Counter Wilkinson ADC ‘trigger’ Ch # Charge 1-40 MIP, S/N~ 15-20, Time resolution: BC tagging, fine: ~ 2ns Calibration Control Analog samplers, slow, fast iVi > th Sparsifier Channel n+1 Channel n-1 Time tag Preamp + Shapers Strip reset reset J-F Genat, LLN, Jan 16th 2008
- 51. Digital sampler prototype chip layout J-F Genat, LLN, Jan 16th 2008 Technology CMOS 130nm
- 52. Prototype Sampler chip beam tests J-F Genat, LLN, Jan 16th 2008 120 GeV pions beam tests S/N= 18 Detectors+ 130nm chip
- 53. Issues Inter-layers vias through oxide (etching) Wafer thinning to facilitate through wafer vias Alignment (< 1m) Present: 6’’ wafer thinned to 6 m, mounted on 75 m Kapton ! J-F Genat, LLN, Jan 16th 2008
- 54. Outline J-F Genat, LLN, Jan 16th 2008 Solid-state vs Gaseous, basics Strips Timing Pixels Monolithic DEPFETs SOI Hybrids 3D detectors Readout electronics Perspectives
- 55. MAPS Faster collection time by drift in a depleted PN junction Integrate pixel discriminators: Sparse readout to fasten the readout Improve fill factor Integrate pixel DAC for threshold match Storage 350nm standard HighVoltage CMOS process (used for I/Os) Mannheim Germany I. Peric IEEE NSS 2007 N20-1 pp1033-1039 J-F Genat, LLN, Jan 16th 2008
- 56. 3D Silicon Merge pixels and strips Pixels top Strips underneath Readout with bump-bonded pixel chip, wire bonded to strip readout chip Improved space resolution, trigger capabilities with the strips. C. Da Via’ 2005 J-F Genat, LLN, Jan 16th 2008
- 57. Silicon at low T J-F Genat, LLN, Jan 16th 2008 Electron and hole mobilities in Silicon vs dopants densities at various temperatures
- 58. Front-ends NA60 AFP chip (CERN) Cryogenic Silicon beam tracker for high intensity proton beam and heavy ions hodoscopes • 32 channels 0.25m CMOST=80-300K • Transimpedance amplifier optimized for 4pF input • CMOS 250nm • Gain: 10mV/MIP • Noise: 350 e- (@ 300K) • Fall time: 3ns @ 300K, 1.5ns @ 130K • Radiation hard to 1015 p/cm2 Designed for 20 m pitch Silicon strips detectors Rencently tested with 3D detectors G. Anelli et al A high speed low-noise transimpedance… NIMA 512 1-2 pp117-120 J-F Genat, LLN, Jan 16th 2008
- 59. Silicon readout J-F Genat, LLN, Jan 16th 2008 Merge low-noise amplification and sampling Increase number of channels up to 1k Implement low level Digital Signal Processing Calibrations, centroids, fits Flip-chip 3D interconnect Equip on-detector Silicon strips readout 3D interconnect to pixels (3D or others)
- 60. Signal processing • Fast samplers in CMOS technology • Saclay (France) 2 GHz 12 bits • Germany 5 GHz 12 bits • Hawaii 6 GHz 10 bits Push sampling speed up to higher frequencies: Get Charge and Time with ultimate precision J-F Genat, LLN, Jan 16th 2008
- 61. Vertical integration As device feature size cost increases, vertical integration allows stacking any processes: DEPFET + CMOS/SOI CCD + CMOS/SOI MAPS + CMOS/SOI Solves the 2D interconnection bottleneck: - Reduces I/O pads, crosstalk, power, increases speed for same functionnality Ray Yarema, FNAL Lincoln Labs IZM Germany Digital Analogue Sensor J-F Genat, LLN, Jan 16th 2008
- 62. Vertical integration references Ray Yarema Fermilab Marcel Demarteau ’’ R. Yarema, 3D Integrated Circuits for HEP, 6th Front-End Electronics Workshop Perugia 2006 C.Bower et al, High Density Vertical Interconnects 56th Electronics Components TC Conference May 30th -June 2 2006 San Diego A. Klump, ‘’3D System integration’’, FEE Perugia 2006 B. Aull et al. Laser Radar Image based on 3D APDs IEEE SSCC 2006, p26 J-F Genat, LLN, Jan 16th 2008
- 63. The end… Lots of ideas Technology exploding So much to do… Thanks !