Design and Testing Challenges for Chiplet Based Design: Assembly and Test View
0 likes771 views
The document outlines the design and testing challenges inherent in chiplet-based design, including assembly and testing processes utilizing Zglue's chiplet technology. It emphasizes the importance of interoperability, the responsibilities of designers and integrators for testing and quality, and the need for comprehensive methodologies and standardization. A call to action encourages collaboration among stakeholders to address these challenges and improve chiplet deployment.
Design and Testing Challenges for Chiplet Based Design: Assembly and Test View
- 1. Design and Testing Challenges for Chiplet Based Design: Assembly and Test View Jawad Nasrullah Co-founder and CTO zGlue Inc 1/29/2018
- 2. • Intro & Interest zGlue wants to support and contribute to Open initiatives • Assembly and Test Options for Chiplet-Based Design • Call to Action • Questions & General Discussion Outline 2
- 3. zGlue Smart fabric, a programmable silicon chip, designed to be the base for chip stacking. Developer uses zGlue ChipBuilder online software to choose chiplets, stack chiplets and build a system on chip with it. zGlue ChipBuilder was launched commercially at CES this year. (www.zglue.com/ChipBuilder) Step 1: Select a zGlue Smart Fabric base (Programmable silicon base for stacking. ‘Glue’ chiplets in z direction.) Step 2: Develop, Code and Order (Select Chiplets, place, design capture, route, test, download API and SDK, order devkits, order volume.) Step 3: Manufacture (Start with a Shuttle Run then Ramp up volume. Hardening option available for HVM.) SolutionzGlue–a Chiplet Based Design Company 3
- 5. Chiplet Availability and Interoperability (Architecture, Electrical, Mechanical) Chiplet Marketplace and Business Framework Chiplet IO compatibility Design Collateral Availability Many Assembly Design Choices Design Tools are being retrofitted • Thermal and Mechanical simulations requires complex multi-physics tools (no PDK) • Low Power Technology is the enabler of Chip Stacking Testability • How to Debug system level issues • Who owns the system level yield loss 6 Challenges for Chiplet Based Design
- 7. C1 C2 C3 C4 Substrate Si Interposer C1 C2 C3 C4 Substrate C2+C4+Interposer C1 C3 Active Silicon Substrate Chiplets on Organic Substrate (POC I) Chiplets on 2.5D Si Interposer Chiplets on Active Silicon 8
- 8. C1 C2 C3 C4 Substrate Chiplets on Organic Substrate (POC I) Innovative FE (arch), Mature BE (assembly), Novel Business Model Unit BoM Cost (MCM) ∝ {t1 x Area_C1 + t2 x Area_C2 + t3 x Area_C3 + t4 x Area_C4} + {t5 x Area_Substrate} TESTING FLOW (assuming no Radio Chiplets):- DFT & Verification: - Need ESL (transaction level) and IBIS Models for all Chiplets - Need Mechanical Models for all Chiplets for Thermal/Mech Simulations - Simple JTAG in each Chiplet (can skip for PoC) Incoming Material: - Visual Inspection (at best, cannot afford retest of each component) - Quality of Chiplet to be guaranteed by the Vendor - E-test for substrate After Assembly: - Inspection (Xray etc) - System level testing to verify assembly process (JTAG needed) Q&R: Responsibility of the designer, the integrator, and the application 9
- 9. Chiplets on 2.5D Si Interposer Innovative FE (arch), Innovative BE (Design & assembly) Unit BoM Cost ∝ {t1 x Area_C1 + t2 x Area_C2 + t3 x Area_C3 + t4 x Area_C4} + {t5 x Area_Substrate} + t6*Area_Si_Interposer TESTING FLOW (assuming no Radio Chiplets):- DFT & Verification: - Need ESL (transaction level) and IBIS Models for all Chiplets - Need Mechanical Models for all Chiplets for Thermal/Mech Simulations - Simple JTAG in each Chiplet (can skip for PoC) Incoming Material: - Visual Inspection (at best, cannot afford retest of each component) - Quality of Chiplet to be guaranteed by the Vendor - E-test for substrate - CP test for Si Interposer After Assembly: - Inspection (Xray etc) - System level testing to verify assembly process (JTAG needed) Q&R: Responsibility of the designer, the integrator, and the application 10 Si Interposer C1 C2 C3 C4 Substrate
- 10. Chiplets on Active Silicon Innovative FE (arch), Innovative BE (Design & assembly) Unit BoM Cost ∝ {t1 x Area_C1 + t3 x Area_C3} + {t5 x Area_Substrate} + t6*Area_C3+C4+Si_Interposer TESTING FLOW (assuming no Radio Chiplets):- DFT & Verifciation: - Need ESL (transaction level) and IBIS Models for all Chiplets - Need Mechanical Models for all Chiplets for Thermal/Mech Simulations - Simple JTAG in each Chiplet (can skip for PoC) Incoming Material: - Visual Inspection (at best, cannot afford retest of each component) - Quality of Chiplet to be guaranteed by the Vendor - E-test for substrate - CP test for Si Interposer After Assembly: - Inspection (Xray etc) - System level testing to verify assembly process (JTAG needed) Q&R: Responsibility of the designer, the integrator, and the application 11 C2+C4+ Si Interposer C1 C3 Active Silicon Substrate
- 11. Limitations: Chiplets being used are pre-existing hence the assembly and test flow needs to be retrofitted. Assembly: BGA MCM. Flipchip on substrate and wire-bond on substrate Testing of Individual Chiplets: N/A for PoC System Test and Bring-up: To be architected. Highspeed interfaces are critical to test. IEEE 1149.1 and 1149.6 JTAG should be leveraged. A test architecture with daisy chained JTAG may work but a detailed design will be needed. 12 Assembly & Test Considerations for PoC I
- 12. 1- Agreement needed on a Testing Methodology that leverages existing technology such as JTAG. 2- Chiplet Providers should commit to providing detailed Data Sheets, ESL and IBIS Models for DFT and Verification, and FEM Models for Mechanical Simulations. 3- Chiplets need to be tested to the identical (or better) screening standard that a regular chip sale entails. Test escapes in the chiplet lot, otherwise, will cause a yield issue that will effect other assembled BoM. 4- Need to come up with a simple standard (PDK) for assembly design and simulation. 13 Call to Action and Discussion