Developing for polar fire soc
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The document discusses developing applications for the PolarFire® System on Chip (SoC) field programmable gate array (FPGA). It notes that developing for the PolarFire SoC is less complicated than it seems. It covers the functionality of the application and monitor cores, how to develop bare metal applications using SoftConsole IDE, and how to develop FPGA applications using the Libero SoC Design Suite. Examples of driver code and build systems are also provided to simplify the development process for the PolarFire SoC.
Developing for polar fire soc
- 1. Information Classification: General CONTRIBUTE. COLLABORATE. COMMERCIALIZE. December 8-10 | Virtual Event
- 2. Information Classification: General December 8-10 | Virtual Event Developing for PolarFire® SoC Hugh Breslin Design Engineer Microchip #RISCVSUMMIT
- 3. Information Classification: General Developing for PolarFire® SoC Less complicated than it seems! In this session we’ll be discussing the world’s first RISC-V® based SoC FPGA. With the PolarFire® SoC, we have been able to create a multi core RISC-V based SoC FPGA that brings more functionality than any of our previous product families. An SoC FPGA is like a blank canvas, which means you must develop your HDL design, generate, program the part and test before you can get started. In this presentation we will discuss: • Functionality of the application and monitor cores • How to develop for bare metal • How to develop for an FPGA My hope is that at the end of the presentation, developing with PolarFire SoC will seem less complicated!
- 4. Information Classification: General Developing for PolarFire® SoC • Worlds first RISC-V based SoC FPGA • FPGAs = Complicated? Nope! • PolarFire SoC = Dynamic • RISC-V = Invisible FPGA SoC
- 5. Information Classification: General Developing for PolarFire® SoC • MSS • 5 Cores • 1 Monitor core • 4 Application cores • Peripherals • Universal Asynchronous Receiver Transmitter (UART), Universal Serial Bus (USB), Controller Area Network (CAN), General-Purpose Input/Output (GPIO), Ethernet, Double data rate (DDR), MMC, etc. • FPGA • PolarFire FPGA • Programable logic, Serializer/Deserializer (SerDes), PCI, MATH blocks, Static random-access memory (SRAM), etc. • MSS + FPGA = freedom and flexibility
- 6. Information Classification: General The Application Cores • U54 Application cores • 1 core / 2 core / 3 cores / 4 cores • 1 + 3 • 2 + 2 • 2 + 1 + 1 • 1 + 1 + 1 + 1 • Bare metal: SoftConsole IDE • Linux®: Buildroot / Yocto #ifndef MPFS_HAL_FIRST_HART #define MPFS_HAL_FIRST_HART 0 #endif #ifndef MPFS_HAL_LAST_HART #define MPFS_HAL_LAST_HART 4 #endif void u54_1(void) {} __attribute__((weak)) void u54_1(void) { /* Put hart in safe infinite WFI loop. */ park_hart(); }
- 7. Information Classification: General The Monitor Core • E51 Monitor core • Hart Software Services (HSS) • System Services • Message Sharing • Boot U54_1 U54_2 U54_3 U54_4 Cache Cache Cache Cache System Bus Memory Linux I/O E51 Cache HSS Communication Layer RTOS
- 8. Information Classification: General Bare Metal Development • Bare metal: SoftConsole IDE • Example projects: • Each peripheral driver • How to use the functions provided • SoftConsole: build, debug and emulate • Examples are all pre-configured
- 9. Information Classification: General mss_init_mutex((uint64_t)&uart_lock); MSS_UART_init( &g_mss_uart0_lo, MSS_UART_115200_BAUD, MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); /* Receive interrupt is enabled now. Please see uart0_rx_handler() for * more details */ MSS_UART_set_rx_handler(&g_mss_uart0_lo, uart0_rx_handler, MSS_UART_FIFO_SINGLE_BYTE); MSS_UART_enable_local_irq(&g_mss_uart1_lo); /* Demonstrating polled MMUART transmission */ uart_tx_with_mutex(&g_mss_uart0_lo, (uint64_t)&uart_lock, g_message1, sizeof(g_message1)); mss_take_mutex((uint64_t)&uart_lock); /* Demonstrating interrupt method of transmission */ MSS_UART_irq_tx(&g_mss_uart0_lo, g_message2, sizeof(g_message2)); /* Makes sure that the previous interrupt based transmission is completed * Alternatively, you could register TX complete handler using * MSS_UART_set_tx_handler() */ while (0u == MSS_UART_tx_complete(&g_mss_uart0_lo)) { ; } Driver Example: MMUART
- 10. Information Classification: General Customizing Builds: Development History
- 11. Information Classification: General FPGA Development • FPGA development • Libero® SoC Design Suite v12.5+ • Build on top of the out of the box design
- 12. Information Classification: General Summary • PolarFire® SoC • Easy to develop for • Highly configurable • How are we transparent? • Smart use of defines in code • Providing: • Build systems with platform support and commit history • Examples for all drivers • Pre-built images - users need: FPGA, HSS and payload • FPGA + HSS • Payload
- 13. Information Classification: General December 8-10 | Virtual Event Thank you for joining us. Contribute to the RISC-V conversation on social! #RISCVSUMMIT @risc_v