Differential Amplifiers ( Amplifies the Difference Between Two Inputs) .pdf

Differential Amplifiers
(Amplifies the difference between two input voltages)
(P.N. Kondekar)
1
** P.N. Kondekar **

Contents
1. Differential Amplifier Basics
2. Single-ended signal and Differential signal
3. Differential Pair
3.1. Qualitative Analysis
3.2. Quantitative Analysis
4. Common-Mode Response
5. Differential Pair with MOS Load
6. Gilbert Cell
2
** P.N. Kondekar **

Differential Amplifier Basics
• What is Differential Amplifier ?
A differential amplifier is the combination of inverting and non inverting amplifier that
amplifies difference between two input voltages but suppresses any voltage common
to the two input.
• Why Differential Amplifier ?
As it suppress common signal, so higher immunity to “environmental” noise.
(noise is common to both input).
Mathematically, Common Gain ‘AC’= 0 (ideal)
CMRR = Differential Gain (Ad) / Common Gain (AC) = ∞
So it “rejects” common-mode noise.
• What is problem with Common-Source or other single input amplifiers ?
In Single Input, Vout = gain x Vin (Vin → Vin + Vnoise), i.e. amplify noise
In Differential, ΔVout = gain x ΔVin [ΔVin = (Vin1 – Vin2)]
So ΔVout = gain x (Vin1 +Vnoise – Vin2 – Vnoise) = gain x (Vin1 – Vin2) i.e. cancel noise
But one disadvantage is gain of Differential amplifier is relatively low than Common-
Source amplifier. (we will see this later) 3
** P.N. Kondekar **

Single-ended signal and Differential signal
Single-ended signal is defined as one that is measured with respect to fixed potential
usually ground.
Differential signal is defined as one that is measured between two nodes that have
equal & opposite signal, excursion around a fixed potential (one node have non-inverting
while other have inverting signal). Both nodes signal are with respect to same potential.
To get same signal from two different nodes, the nodes must exhibit equal impedance to
that potential.
The “centre” potential in
differential signaling is called
Common-Mode Level
For example, if we take two different transistor and apply same input signal, we will
get different output because they have different impedance to that same potential.
4
** P.N. Kondekar **

Advantage of Differential Signaling
As we have seen that differential operation is highly immune to environmental
noise over single-ended signaling.
Consider an example
Single Line
Two adjacent lines, one carry small sensitive
signal and other carry large clock waveform
Due to capacitive coupling, transitions on line L2 corrupt the signal on L1.
Differential Line
Now consider, if the sensitive signal is distributed
as two equal and opposite phase and clock is
placed midway between the two.
The transitions in clock disturb the differential
phase by equal amount, cause differential o/p is
not corrupted. This arrangement rejects Common-Mode noise. 5
** P.N. Kondekar **

Another Example
Single-ended → VDD varies by ΔV (due to noise) then Vout changes approximately
the same amount i.e. output is quite susceptible to noise on VDD.
Differential → VDD varies by ΔV, VX and VY affects same but VX – VY = Vout. Thus
circuit is more robust to supply noise.
One more advantage of differential signaling is increase in maximum voltage swing.
In Single-ended circuit : Max achievable voltage swing is VDD – (VGS – VTH).
In Differential circuit : Max achievable voltage swing is 2[VDD – (VGS – VTH)].
Disadvantage: Differential circuit occupy twice as much area as single-ended.
6
** P.N. Kondekar **

Differential Pair
• Two identical single-ended signal paths to process the two phase.
• Output is taken as differential signal (Vout1 – Vout2).
• Advantage: High rejection of supply noise, Higher output swing.
Problems to be studied:
• What happens if we change input common-mode dc level or simply don’t have a
well defined common-mode dc level ?
• Modification in circuit to solve the above problem.
• Qualitative Analysis of Modified circuit.
• Quantitative or Mathematical Analysis using different methods. 7
** P.N. Kondekar **

What happens if we don’t have a well-defined common-mode dc level??
Change in input CM level (Vin,CM) causes changes in:
• Bias currents of M1 (ID1) and M2 (ID1) and output CM level too.
• Transconductance
• Small-signal gain |AV| = gm.RD
As output CM level changes (from its ideal value)→ maximum allowable output swing
value will also be lowered.
For example :
If the input CM level is excessively low, M1 and M2 may turn off
for minimum value of Vin1 and Vin2 leading to clipping at output
(max. swing reduces).
Result: We need to bias currents of device so it have minimal
dependence on input CM level.
8
D
ox
n
m (W/L)I
C
2μ
g =
** P.N. Kondekar **

Modification in circuit (Constant Current source added)
We had studied that if input common-mode level changes it will change bias current
which will cause change in gain. So basically we don’t want our current to change
with change in input common-mode level (due to noise or disturbance).
Adding a current source can solve this problem, so we modified the circuit by adding
a constant current source.
Addition of Constant Current Source
Iss = ID1 + ID2
If Vin1 = Vin2 → ID1 = ID2 = ISS/2
Now if input Vin,CM changes still Vin1 = Vin2
Again ID1 = ID2 = ISS/2 (bias current is equal)
Gain remain constant
Output CM level is VDD – RD.ISS/2
Note: If we don’t add constant current source then change in Vin,CM will changes current and
change in current will cause change in gain. 9
)
(W/L)I
C
2μ
(g D
ox
n
m =
** P.N. Kondekar **

Qualitative Analysis
• Input-Output characteristics of a differential pair
a) Change in output w.r.t. differential input
b) Change in differential output w.r.t. differential input
• Common-Mode behavior of circuit
a) Different circuit parameters variation w.r.t. Input CM level
b) Limits of input CM level (Vin,CM)
c) Effect of CM level on maximum output swing
• Trade Off between Vin,CM and Differential Gain
10
** P.N. Kondekar **

1) Input-Output characteristics
a) Plotting (Vout) v/s (Vin1 – Vin2)
–∞ < Vin1 – Vin2 < ∞
Case 1: Vin1 – Vin2 << 0 → Vin1 << Vin2 M1 OFF, M2 ON
ID2 = ISS → Vout1 = VDD and Vout2 = VDD – RD.ISS
Case 2: Vin1 – Vin2 >> 0 → Vin2 << Vin1 M1 ON, M2 OFF
Case 3: Vin1 < Vin2 (Vin1 is brought closer to Vin2)
M1 gradually turns ON, draw a fraction of ISS
hence lowering Vout1 from VDD to Vout1 = VDD – RD.ID1
Vout2 = VDD – RD.ID2 (ID1 < ID2 → Vout1 > Vout2)
Same for Vin2 < Vin1 (Vin2 is brought closer to Vin1)
11
** P.N. Kondekar **

b) Plotting (Vout1 – Vout2) v/s (Vin1 – Vin2)
Case 1: Vin1 – Vin2 << 0 → Vin1 << Vin2 M1 OFF, M2 ON
Vout1 – Vout2 = RD.ISS
Case 2: Vin1 – Vin2 >> 0 → Vin2 << Vin1 M1 ON, M2 OFF
Vout1 – Vout2 = –RD.ISS
Case 3: Vin1 – Vin2 = 0 → Vin1 = Vin2 M1 ON, M2 ON
ID1 = ID2 = ISS/2 → Vout1 = Vout2 = VDD – RD.ISS/2
Vout1 – Vout2 = 0
12
** P.N. Kondekar **

Observation:
1) Maximum and Minimum output levels are well defined (VDD and VDD – RD.ISS)
and independent of input CM level because we had plotted output w.r.t. i/p
difference signal (Vin1 – Vin2) i.e. i/p CM noise cancels out.
2) Small-signal gain (slope of Vout1 – Vout2 versus Vin1 – Vin2)
is max. at Vin1 – Vin2 = 0 i.e. Vin1 = Vin2, gradually falling
to zero as |Vin1 – Vin2| increases.
We can also see in graph that circuit is approx. linear near
Vin1–Vin2 = 0 and become non-linear as |Vin1–Vin2| increases
i.e. circuit become non-linear as input voltage swing increases.
2) Common-Mode behavior of circuit
Role of tail current is to suppress the effect of input CM level variation on operation
of M1 and M2 and output level.
So can we assume any arbitrarily low or high values of Vin,CM ??
To answer this, we will fix Vin1 = Vin2 = Vin,CM and plot some variables of circuit with
respect to Vin,CM. 13
** P.N. Kondekar **

For Vin,CM = 0
M1 and M2 Off,
ID1 = ID2 = 0,
Vb is high so M3 is in deep triode
Vout1 = Vout2 = VDD
a) Circuit parameters variation with respect to input CM level
Vin,CM ≤ VTH → M1 and M2 Off, ID1 = ID2 = 0, VP = 0 and Vout1 = Vout2 = VDD
Vin,CM > VTH → M1 and M2 starts to turn ON, ID1 & ID2 starts to increases, VP also rises and
Vout1 decreases from VDD to VDD – RD.ID1
Vin,CM >> 0 → For sufficiently high Vin,CM, VP also become high and force M3 into saturation.
M3 is in saturation, it work as a constant current source, so ID1 = ID2 = ISS/2,
VP is force to track to Vin,CM and Vout1 = VDD – RD.ISS/2
14
** P.N. Kondekar **

b) Limits of Input CM level
We have to find the limits of input CM level for which our circuit work properly
Minimum value of Vin,CM
We previously see, for small Vin,CM M3 is in triode but we want it in saturation so there
must be some min. value of Vin,CM to operate M3 in saturation
For M3 in saturation
VP ≥ Vb – VTH → Adding Vin,CM on both side
Vin,CM + VP ≥ Vin,CM + Vb – VTH
Vin,CM ≥ Vin,CM – VP + Vb – VTH
Vin,CM ≥ VGS1 + (VGS3 – VTH)
Maximum value of Vin,CM
Now Vin,CM is increased continuously, M3 is in saturation so current in M1 and M2 is
constant and Vout1 and Vout2 will be constant too.
Vin,CM↑ so VP↑ too but Vout1 is constant i.e. VGS1 – VTH > VDS1 → M1,M2 enters triode.
For M1 and M2 in saturation
VGS1 – VTH ≤ VDS1 → Vin,CM ≤ Vout1 + VTH = VDD – RD.ISS/2 + VTH → Vin,CM ≤ VDD – RD.ISS/2 + VTH
15
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
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in,
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GS1 V
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(V
V
** P.N. Kondekar **

From previous understanding of Vin,CM limits, we can plot AV vs Vin,CM
Vin,CM ≤ VTH → gain = 0
Vin,CM > VTH → gain starts to increase
Vin,CM ≥ V1 → M3 enters in saturation and
gain become constant
Vin,CM ≥ V2 → M1 and M2 enters triode and gain begins to decrease
Note: Increasing Vin,CM after V1, gain does not increase due to constant current in M1 & M2
c) Effect of CM level on Maximum Output Swing
How large can output voltage swings of a differential pair be??
For M1 and M2 to be in saturated,
Highest output value of M1 = VDD
Lowest output value of M1 = VGS1 – VTH + VP
= Vin,CM – VTH
Observation: Higher the Vin,CM, smaller the output swing,
it is desirable to choose low Vin,CM 16
** P.N. Kondekar **

3) Trade Off between Vin,CM and Differential Gain
Differential gain is function of Gm and Gm is function of Iss (constant current of M3)
|AV| = Gm.RD
So to increase gain, ISS should be
increased, but increasing ISS will
cause high drop across RD.
Vout1↓ = VDD – (ISS↑).RD/2
Lowering of Vout1 can force M1 into triode and to make M1 remain in saturation we
need to low input Vin,CM (Vin,CM↓ ≥ Vout1↓ + VTH).
Vin,CM should remain close to ground potential so to make M1 remain in saturation.
Result: So the trade off here is to increase gain we need to decrease Vin,CM.
17
SS
ox
n
m (W/L)I
C
μ
G =
** P.N. Kondekar **

Quantitative Analysis
• Transconductance and Gain calculation
• Examine the change in different parameters while changing the ∆Vin
a) Transconductance ‘Gm’
b) Differential Current ‘∆ID’
• Limit of ∆Vin (∆Vin up to which both transistors are ON)
• Small-Signal behavior of Differential Pair
a) Method 1: Using Superposition
b) Method 2: Using Half-Circuit concept
18
** P.N. Kondekar **

Quantitative Analysis
We now understand working of Differential Amplifier using mathematic and calculate
some important parameters (for ex. Resultant transconductance, Overall Gain etc).
Transconductance ‘Gm’ and Gain ‘AV’ calculation
We have to calculate (ID1 – ID2) in terms of (Vin1 – Vin2)
Assumptions: M1 and M2 in saturation and λ = 0, circuit
is symmetric.
Voltage at P = Vin1 – VGS1 = Vin2 – VGS2 → Vin1 – Vin2 = VGS1 – VGS2
Acc. to square law
)
V
V
(
)
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19
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−
** P.N. Kondekar **

(differential input voltage)
Our objective is to calculate differential output current (ID1 – ID2) as a function of
differential input voltage (Vin1 – Vin2)
Squaring above eqn and using ID1 + ID2 = ISS →
Squaring again and noting 4ID1.ID2 = (ID1 + ID2)2 – (ID1 – ID2)2 = I2
SS – (ID1 – ID2)2
Thus relation between, (ID1 – ID2) and (Vin1 – Vin2) is
20
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in1
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D2
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D1
GS2
GS1 V
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V −
=
−
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L
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2
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(V
L
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in2
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4
in2
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2
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V
(V
L
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(V
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1
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I
(I −
+
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
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
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−
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−
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in2
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ox
n
SS
in2
in1
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D2
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V
(V
L
W
C
μ
4I
)
V
(V
L
W
C
μ
2
1
I
I −
−
−
=
−
** P.N. Kondekar **

Transconductance
Differentiating both side with respect to (Vin1 – Vin2) for equivalent Gm of the circuit
For ∆Vin = 0,
Gain
Vout1 – Vout2 = VDD – RD.ID1 – (VDD – RD.ID2) = –RD.(ID1 – ID2) → ∆Vout = –RD. ∆ID
Differentiating both side w.r.t. ∆Vin
(d∆Vout/d∆Vin) = –RD.(d∆ID/d∆Vin) → |AV| = RD.Gm
)
V
V
(
)
V
V
(
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V
A
in2
in1
out2
out1
in
out
V
−

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
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21
2
in
ox
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SS
2
in
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D
m
ΔV
(W/L)
C
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4I
V
2
(W/L)
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μ
4I
L
W
C
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ΔV
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−

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G =
D
SS
ox
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(W/L)I
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μ
A =
** P.N. Kondekar **

Change in different parameter w.r.t. ∆Vin
a) Examine the relation between (GM) and (Vin1 – Vin2)
By observing above equation,
*Gm falls to zero for and maximum for ∆Vin = 0
As Gm is maximum at ∆Vin = 0, therefore to get max. and constant gain, we will superimpose
only small-signal (because small-signal will not disturb Gm)
b) Examine the relation between (ID1 – ID2) and (Vin1 – Vin2)
For (ID1 – ID2) = 0, i.e. ID1 = ID2 we get two different values of (Vin1 – Vin2)
But if we go previously, this was not predicted in plot of (ID1 – ID2) vs (Vin1 – Vin2)
22
2
in
ox
n
SS
2
in
ox
n
SS
ox
n
in
D
m
ΔV
(W/L)
C
μ
4I
V
2
(W/L)
C
μ
4I
L
W
C
μ
2
1
ΔV
ΔI
G
−

−
=

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[W/L])
C
/(μ
2I
ΔV ox
n
SS
in =
2
in2
in1
ox
n
SS
)
V
(V
(W/L)
C
μ
4I
−
−
−
=
− )
V
(V
L
W
C
μ
2
1
I
I in2
in1
ox
n
D2
D1
W/L)
C
/(μ
4I
ΔV
2)
and
0
V
V
ΔV
1) ox
n
SS
in
in2
in1
in =
=
−
=
** P.N. Kondekar **

The (ID2 – ID1) vs (Vin1 – Vin2) is same as (Vout1 – Vout2) vs (Vin1 – Vin2) and we had already
studied this plot in qualitative analysis.
According to this plot,
∆ID crosses zero only at one value of ∆Vin i.e. (ID2 – ID1) = 0 for (Vin1 – Vin2) = 0
But Mathematical analysis show ∆ID = 0 for two different values of ∆Vin, How ???
Recall the relation derived between (ID1 – ID2) and (Vin1 – Vin2), we have assumed that
M1 and M2 are saturated and they both are ON but in reality if ∆Vin exceeds a limit,
one transistor carries the entire ISS while turning off the other.
23
** P.N. Kondekar **

Limit of ∆Vin (∆Vin up to which both transistors are ON)
Let ∆Vin exceeds the limit for which M2 will turn off and all current flows in M1
∆Vin = ∆Vin1 (Minimum ∆Vin for which M2 will off)
ID1 = ISS and ID2 = 0 (as all current flow in M1)
∆Vin = Vin1 – Vin2 = VGS1 – VGS2 = ∆Vin1 and
(2nd value of ∆Vin for which ∆ID = 0)
Observation: ∆Vin1 is less than i.e. M2 will get OFF before the 2nd
value of ∆Vin which we have calculated assuming that M1 and M2 both are ON.
∆Vin > ∆Vin1, M2 OFF and derived relation between (ID1–ID2) and (Vin1–Vin2) does not
hold hence is invalid.
24
L
W
C
μ
2I
ΔV
ox
n
SS
in1 =
L
W
C
μ
2I
L
W
C
μ
2I
V
V
ox
n
D2
ox
n
D1
GS2
GS1 −
=
−
[W/L])
C
/(μ
4I
ΔV ox
n
SS
in1 
[W/L])
C
/(μ
4I
ΔV ox
n
SS
in1 =
[W/L])
C
/(μ
4I ox
n
SS
** P.N. Kondekar **

From previous study, we conclude that ∆Vin (Vin1 – Vin2) has a limit ‘∆Vin1’, after that
limit, one of the transistor turns-off and there will be no gain and this is also shown
in overall transconductance Gm vs ∆Vin plot.
In other words, ∆Vin1 is maximum differential input
that circuit can handle.
What if we want to increase ∆Vin1 ??? (↑∆Vin1 will increase circuit input capability)
a) (∆Vin1)↑ by ↑(ISS) or b) (∆Vin1)↑ by ↓(W/L)
↑(ISS) → (Input Range)↑ ↑(W/L) → (Input Range)↓
(output current swing )↑ (gain)↑
25
L
W
C
μ
2I
ΔV
ox
n
SS
in1 =
** P.N. Kondekar **

Tradeoff cause by increasing ∆Vin1
Increasing ∆Vin1 so to make circuit linear, we have to ↑ISS or ↓W/L
But ↑ISS or ↓W/L can effect other parameters like increase in overdrive voltage of
M1 and M2
Overdrive Voltage of M1, M2
For zero differential input
ID1 = ID2 = ISS/2
Hence overdrive voltage increase
Disadvantage:
Increasing ∆Vin1 increases overdrive-voltage which cause decrease in output-swing.
For given ISS, ∆Vin1 is increased by ↓W/L only, which reduces transconductance.
26
L
W
C
μ
2I
ΔV
ox
n
SS
in1 =
L
W
C
μ
I
)
V
(V
ox
n
SS
1,2
TH
GS =
−
** P.N. Kondekar **

Small-Signal behavior of Differential pair
We apply small signal Vin1 and Vin2 and assume M1 and M2 are saturated and calculate
differential gain of circuit.
Gain Calculation
We had already calculated differential gain (overall gain) which is equal to
As both transistor carries approximately equal current
i.e. ID1 ≈ ID2 ≈ ISS/2 (RD1 = RD2 = RD)
Therefore gm of M1 and M2 is
Gain of M1 & M2 is |AV M1,M2| = gm1,2.RD
Observation: Gain of single M1 or M2 is equal to Gain of Differential Amplifier
Now to arrive at same result by small-signal analysis, we employ two different
method, each provide insight into circuit’s operation 27
D
SS
ox
n
V R
I
L
W
C
μ
A =
SS
D1,2 I
I (W/L)
C
μ
(W/L)
C
2μ
g ox
n
ox
n
m1,2 =
=
D
ox
n R
(W/L)
C
μ SS
I
=
** P.N. Kondekar **

Method 1: Small-Signal analysis using SUPERPOSITION
In Superposition, first see the effect of Vin1 on Vout1 & Vout2 while grounding the Vin2
and then the effect of Vin2 on Vout1 & Vout2 while grounding the Vin1.
• Set Vin2 to 0 and finding the effect of Vin1 at X and Y
A) To obtain effect of Vin1 at X (Vout1)
M1 forms a common-source stage
with a degeneration resistance RS
equal to impedance seen looking
into source of M2.
28
** P.N. Kondekar **

Calculating degeneration Resistance ‘RS’
(Neglecting channel-length modulation and body effect)
IX = – gm2.V1
V1 = –VX → IX = gm2.VX
VX/ IX = RS = 1/gm2
Finding (VX/Vin1)
Equivalent Small-Signal
Circuit Circuit
Vin1 = V1 + (gm1V1).RS ……………………… (1)
VX = – (gm1V1).RD1 → V1 = –VX/(gm1.RD1) …………… put in eqn (1) 29
** P.N. Kondekar **

we have RS = 1/gm2
B) To obtain effect of Vin1 at Y (Vout2)
M1 drives M2 as a source follower
Replace Vin1 and M1 by Thevenin
equivalent VT and RT
Calculating Thevenin Resistance ‘RT’
Shorting Vin1 and VDD to find RT RT = 1/gm1
30
m2
m1
D1
in1
X
g
1
g
1
R
V
V
+
−
=
** P.N. Kondekar **

Calculating Thevenin Voltage ‘VT’
Voltage at source of M1 must be equal to Vin1 because
in given circuit no current will flow i.e. ID = 0 so to make
ID = 0 Gate and Source voltage of M1 must be same.
That’s why
VT = Vin1
Note: In previous case we did not calculate voltage with degeneration resistance RS
because there is no input voltage applied at Gate of M2 that’s why resultant VT = 0
Finding (VY/Vin1)
Small-Signal Circuit
M2 as a Source Follower 31
** P.N. Kondekar **

VY = – (gm2V1).RD2 ……………………..(1)
V1 + (gm2/gm1) V1 + Vin1 = 0
V1 = – Vin1/(1 + [gm2/gm1]) …………… put in eqn (1)
Let RD1 = RD2 = RD
Overall voltage gain for Vin1
For gm1 = gm2 = gm, (VX – VY) reduces to
32
m1
m2
D2
in1
Y
g
1
g
1
R
V
V
+
=
m1
m2
D
in1
Y
m2
m1
D
in1
X
g
1
g
1
R
V
V
and
g
1
g
1
R
V
V
+
=
+
−
=
in1
m2
m1
D
V
to
Due
Y
X V
g
1
g
1
2R
)
V
(V
in1
+
−
=
−
in1
D
m
V
to
Due
Y
X V
R
g
)
V
(V
in1
−
=
−
** P.N. Kondekar **

Overall voltage gain for Vin2
By virtue of symmetry, the effect of Vin2 at X and Y is
identical to that of Vin1 except for change in polarities
Adding the two sides to perform Superposition,
we get differential gain
Observation:
1) Magnitude of overall voltage gain for Vin1, Vin2 [input is applied to only one side]
and overall differential gain for (Vin1 – Vin2) [input is difference b/w two sources]
is same as gm.RD i.e. regardless of how inputs are applied, gain will be same.
33
in2
D
m
V
to
Due
Y
X V
R
g
)
V
(V
in2
=
−
D
m
in2
in1
tot
Y
X
R
g
V
V
)
V
(V
−
=
−
−
** P.N. Kondekar **

2) Single ended output gain (Vout1/Vin1), if input is
applied on one side only is
where gm1 = gm2 = gm
(Vout1/Vin1) = – (gm.RD)/2
i.e. If output is single ended (sensed b/w X and ground) then gain is halved.
Example: In the circuit M2 is twice wide as M1. Calculate the Small-signal gain if the
bias values of Vin1 and Vin2 are equal.
Solution: Vin1 = Vin2 (Gates of M1 and M2 at same potential)
ID2 = 2ID1 = 2Iss/3 [because M1 → (W/L) & M2 → (2W/L)
and VGS1 = VGS2]
i.e. gm2 = 2gm1. Therefore
Note: For given ISS, this gain is lower than the gain of symmetric differential pair
(with 2W/L for each device) because gm1 is smaller. 34
m2
m1
D
in1
X
g
1
g
1
R
V
V
+
−
=
/3
(2W/L)2I
C
2μ
g
and
/3
(W/L)I
C
2μ
g SS
ox
n
m2
SS
ox
n
m1 =
=
D
m1
m1
m1
D
V R
g
3
4
2g
1
g
1
2R
A =
+
=
** P.N. Kondekar **

Gain comparison between Common-Source Stage and Differential Pair
For a given total bias current ISS ,we will calculate gm of both Common-Source and
Differential Pair
Differential Pair
For ΔVin = 0, ID1 = ID2 = ISS/2
|AV| = (Vout1 – Vout2)/(Vin1 – Vin2) = Gm.RD
Common-Source Stage
|AV| = ∂Vout/∂Vin = gm.RD
Observation: Gm = gm/√2 (Gm of Differential pair is smaller than gm of Common-Source).
Thus total gain of Differential pair is proportionally less.
A Differential pair achieves the same gain as CS stage at cost of twice bias current ISS.
35
SS
ox
n
m (W/L)I
C
μ
G =
SS
ox
n
m I
L
W
C
2μ
g =
** P.N. Kondekar **

Method 2: Small-Signal analysis using HALF-CIRCUIT concept
If we prove that changes in differential input does not affect the source voltage (VP)
i.e. VP seems constant for small-signal differential input.
Then our circuit will greatly simplify Small-Signal Analysis because VP can be taken
as “ac-ground” and circuit can be decompose into separate halves.
Hence ‘Half-Circuit’ concept
*Condition: Circuit must be fully-symmetric differential pair and sense differential
inputs (i.e. the two inputs change by equal and opposite amount from
equilibrium condition)
36
** P.N. Kondekar **

Lemma: Consider the symmetric circuit where D1 and D2 represent any 3-terminal
active device.
Vin1 changes from (V0) to (V0 + ΔVin) and Vin2 changes from (V0) to (V0 – ΔVin).
Then, if circuit remains linear, VP does not change. [Assume λ = 0]
Proof:
When Vin1 and Vin2 is in equilibrium at ‘V0’, V1 and V2 (gate to source voltage) must
also be at constant value let Va.
Changes in Vin1 and Vin2 will also change V1 and V2 from its equilibrium value (Va) to
(Va + ΔV1) and (Va) to (Va – ΔV2)
37
** P.N. Kondekar **

i.e. VGS1 (V1) = Va and VGS2 (V2) = Va
(when Vin1 and Vin2 is at V0)
VGS1 (V1) = Va + ΔV1 and VGS2 (V2) = Va – ΔV2
(when Vin1 and Vin2 changes by ΔVin in equal and
opposite amount)
*We know IT = I1 + I2, then any amount of increase or decrease in I1 will cause same
amount of decrease or increase in I2.
i.e. ΔI1 + ΔI2 = 0 ……………(1)
Change in output current I1 and I2
ΔI1 = gm.ΔVGS1 [where ΔVGS1 = Va + ΔV1 – (Va)]
ΔI2 = gm.ΔVGS2 [where ΔVGS2 = Va – ΔV2 – (Va)]
Putting in eqn. (1)
ΔV1 = ΔV2 ………….(2) (change in gate to source voltage must be equal)
Source voltage of both device must be equal i.e. VS1 =VS2 = VP
Vin1 – VGS1 = Vin2 – VGS2 = VP
V0 + ΔVin – (Va + ΔV1) = V0 – ΔVin – (Va + ΔV1) → 2ΔVin = ΔV1 + ΔV2 → 2ΔVin = 2ΔV1
38
** P.N. Kondekar **

ΔVin = ΔV1 (The amount of input change will cause the same amount to change in
gate to source voltage)
VP = Vin1 – V1 → ΔVP = ΔVin1 – ΔV1 = 0
Result: ΔVP = 0 i.e. No change in Source voltage ‘VP’ while changing input
(remember this result is only valid if previous two condition are valid)
The proof of the foregoing lemma can also be invoked from symmetry. As long as
the operation remains linear so that the difference between the bias currents of
D1 and D2 is negligible, the circuit is symmetric. Thus, VP cannot “favor” the change
at one input and “ignore” the other.
From yet another point of view, the effect of D1 and D2
at node P can be represented by Thevenin equivalents.
If VT1 and VT2 change by equal and opposite amounts
and RT1 and RT2 are equal then VP remains constant. We
emphasize that this is valid if the changes are small such
that we can assume RT1 = RT2 39
** P.N. Kondekar **

Gain calculation using half circuit concept (λ = 0)
As VP is not changing with differential input therefore it can considered as ground.
This greatly simplifies the circuit and circuit can be decomposed into two separate
half circuits.
Now both circuits can be considered as Common-Source circuit and their gain can
be calculated using direct formula.
VX/Vin1 = – gm.RD and VY/(–Vin1) = – gm.RD
(If Vin1 = Vin1 then Vin2 = –Vin1 because this concept is valid for differential input)
Thus,
(VX – VY)/(2Vin1) = – gm.RD
40
** P.N. Kondekar **

Gain calculation using half circuit concept (λ ≠ 0)
Small-Signal Model (to calculate gain)
Applying half circuit concept, both circuit can be treated as separate circuit
VX/Vin1 = –gm.(RDǁro1) and VY/(–Vin1) = –gm.(RDǁro2)
Where as ro1 = ro2 = ro
Note: Lengthy calculation needed to get same result from Method 1
)
r
R
(
g
)
(2V
)
V
(V
A o
D
m
in1
Y
X
V −
=
−
=
41
** P.N. Kondekar **

What happens if Input is not Differential??
Can we still use the concept of Half-Circuit to calculate Gain??
We will calculate Gain when Vin1 ≠ –Vin2 and λ ≠ 0 (using half-circuit concept)
i.e. we can convert Non-Differential input signal
into sum of Differential and Common-Mode Signal 42
2
V
V
2
V
V
V
2
V
V
2
V
V
V
in2
in1
in1
in2
in2
in2
in1
in2
in1
in1
+
+
−
=
+
+
−
=
** P.N. Kondekar **

Using Superposition, we can analyze both Differential and Common-Mode
1) Differential Signal (using Half-circuit)
That is,
VX – VY = –gm.(RDǁro)(Vin1 – Vin2)
2) Common-Mode Signal
If circuit is fully symmetric and ISS is ideal current source,
the current drawn by M1 and M2 from RD1 and RD2 is
exactly equal to ISS /2 and independent of Vin,CM.
Thus, VX and VY experience no changes as Vin,CM varies.
Common Mode Gain = 0
Note: The circuit only amplify the difference b/w VX and VY
while eliminating the effect of Vin,CM
43
2
V
V
)
r
R
(
g
V in2
in1
o1
D
m
X
−
−
=
2
V
V
)
r
R
(
g
V in1
in2
o2
D
m
Y
−
−
=
** P.N. Kondekar **

Common-Mode Response
An ideal Differential-Pair has ability to suppress the effect of common-mode
perturbation i.e. Common-Mode Gain ‘Av,CM’= 0
• What if Differential-Pair is not ideal (in reality circuit cannot be fabricated fully
symmetric) and also current source don’t exhibit infinite output impedance.
• This difference in circuit parameter (not fully symmetric circuit) and non infinite
impedance current source will result a variation in input CM appears at output.
Which parameters can cause Common-Mode gain?
1. Finite Resistance Current Source
2. Mismatching in Drain Resistance (RD1 and RD2)
3. Mismatching in M1 and M2 (gm changes)
In previous cases, we calculate common-mode
gain assuming the circuit is symmetric which give
zero common-mode gain.
Now we consider the effect of each parameter on Common-Mode Gain. 44
** P.N. Kondekar **

Common-Mode Gain due to Finite Resistance Current Source
In previous circuits, current-source is ideal i.e. having infinite impedance but now
we will replace infinite impedance to finite impedance RSS.
This finite impedance will result variation in
output CM level with change in Input CM level.
We had previously studied VP variation w.r.t. Vin,CM in Qualitative
Analysis (for ideal current source). We observe that as Vin,CM
increases, VP also track Vin,CM.
● Vin,CM increases, VP also increases i.e. current across RSS also increases.
● Increase in current across RSS increases total current (ID1 + ID2) i.e. drain current
of M1 and M2 increases by increasing Vin,CM.
● Increase in drain currents will decrease the both Vou1 and Vout2. 45
** P.N. Kondekar **

Observation:
Ideal Current Source: Increase in Vin,CM will not increase drain current of M1 & M2
i.e. no effect of Vin,CM on drain currents
That’s why Common Mode Gain = 0
Non-Ideal Current Source: Increase in Vin,CM will increase drain current of M1 & M2.
that is due to that finite current-source impedance RSS.
Vin,CM effects the drain currents and output voltages.
That’s why Common Mode Gain ≠ 0
Common-Mode Gain Calculation
46
** P.N. Kondekar **

Due to symmetry VX = VY. Therefore M1 & M2 are now “in parallel” i.e. they share all
of their respective terminal.
Note: The compound device transconductance is twice the transconductance of
single device i.e.
In Parallel, Resultant Width W(M1+M2) = W1 + W2 = 2W
Resultant Current I(M1+M2) = I1 + I2 = 2I
Therefore, Resultant Transconductance gm(M1+M2) = (2μnCox[2W/L]{2I})1/2
= 2(2μnCox[W/L]{I})1/2 = 2gm
The circuit reduced to a single mosfet C-S stage with source degeneration.
47
** P.N. Kondekar **

As gm(M1+M2) = 2gm
Vin,CM = V1 + 2gmV1.RSS …………….(1)
Vout = –2gmV1.(RD/2)
V1 = –Vout/(gm.RD) …………. Put in eqn (1)
Therefore the Common-Mode Gain of circuit is
Observation: Input CM (Vin,CM) variations disturb the output bias points (i.e. varies
output CM level) and also alter the small-signal gain.
• Vin,CM changes → Drain current changes (due to finite impedance current source).
Differential gain |AV| = gm.RD and gm = (2μnCox[W/L]{ID})1/2.
Therefore (|AV|∝ {ID}1/2) i.e. Small signal gain is proportional to drain current that’s
why change in Vin,CM changes small-signal gain.
• Also change in gain will possibly limit the output voltage swing.
• Vin,CM changes → Drain current changes → Output Voltage changes too
Change in o/p voltage will cause change in output bias point i.e. output CM level
varies with input CM level. 48
SS
m
D
in,CM
out
V,CM
R
)
1/(2g
/2
R
V
V
A
+
−
=
=
** P.N. Kondekar **

Example: The circuit uses a resistor rather than a current source to define a tail current
of 1mA.
Assume (W/L)1,2 = 25/0.5, μnCox = 50 μA/V2, VTH = 0.6 V,
λ = ɣ = 0, and VDD = 3 V.
(a) What is the required input CM for which RSS sustains
0.5 V?
(b) Calculate RD for a differential gain of 5.
(c) What happens at the output if the input CM level is
50 mV higher than the value calculated in (a)?
Solution: (a) ID1 = ID2 = ISS/2 = 0.5 mA and RSS = 500 Ω
and →
Thus Vin,CM = VGS1 + 0.5 V = 1.73 V.
(b) |AV| = gmRD → . Therefore RD = 3.16 k Ω
Note that Vout1 = VDD – ID1RD = 1.42 V and for device in saturation VGS1 – VTH ≤ VDS1
i.e. Vin,CM – VTH ≤ Vout1. Therefore Vin,CM ≤ 1.42 + 0.6 = 2.02 V.
The transistor M1 and M1 is 290 mV (2.02 – 1.73) away from triode region.
2
TH
GS1
ox
n
D1 )
V
(V
L
W
C
μ
2
1
I −
= V
1.23
V
(W/L)
C
μ
2I
V
V TH
ox
n
D1
GS2
GS1 =
+
=
=
49
Ω)
1/(632
(W/L)I
C
2μ
g D1
ox
n
m =
=
** P.N. Kondekar **

(c) Vin,CM increases by 50 mV i.e. ΔVin,CM = 50 mV
and now Vin,CM = 1.78 V
Vout decreases from 1.42 V to 1.323 V (1.42 – 0.0968)
Saturation condition Vin,CM ≤ 1.323 + 0.6 = 1.923 V.
Therefore transistor M1 and M1 is now 143 mV (1.923 – 1.78) away from triode region.
Result : Increase in input CM level will decrease the output CM level i.e. our device
drain voltage decreases with increase in Vin,CM which will cause reduction in
device operating saturation region or device comes closer to triode region.
So this Common-Mode Gain can disturb the output bias point according to the
noise added in input but this CM Gain will not corrupt the Differential Output
(i.e. no common mode to differential mode conversion) as
∆Vout = ∆(VX – VY) = 0 since VX = VY for Common-Mode Input, therefore input noise
will not be amplified when differential output is considered. 50
)
(1/2g
R
/2
R
ΔV
ΔV
m
SS
D
in,CM
Y
X,
+
=
1.94
mV
50 
=
mV
96.8
=
** P.N. Kondekar **

Common-Mode Gain due to Mismatching in Drain Resistance
• Finite output impedance of tail current source results in some Common Mode
gain in symmetric differential pair. Nonetheless, this is a minor concern.
• As circuit cannot be fully symmetric i.e. two sides suffer mismatching during
manufacturing. This will cause variation in Differential Output as a result of a
change in Vin,CM.
• Let transistors (M1 and M2) are identical but drain resistance have mismatching
RD1 = RD and RD2 = RD + ΔRD (where ΔRD denotes small mismatch).
51
** P.N. Kondekar **

Common-Mode to Differential-Mode Gain (ACM-DM) Calculation
Method 1
Change in Vin,CM (∆Vin,CM) will cause change in current in M1 and M2 i.e. ∆I1 and ∆I2.
Now ∆I1 = gm.∆VGS and ∆I2 = gm.∆VGS i.e. ∆I1 = ∆I2. (M1 and M2 are identical)
Therefore current in M1 and M2 will always be same for any Common-Mode Input
(M1 and M2 must remain in saturation).
As current from M1 and M2 into RSS is same, RSS can be divided into two parallel 2RSS.
So above circuit can be treated as two separate circuits and both resolved into
Common-Source with Source degeneration circuit. 52
** P.N. Kondekar **

For Circuit 1
Vin,CM = V1 + gmV1.2RSS …………….(1)
VX = –gmV1.RD
V1 = –VX/(gm.RD) …………. Put in eqn (1)
Therefore
For Circuit 2, just replace RD → RD + ∆RD
Thus a Common Mode change at input introduce a differential component at output.
That’s why,
Circuit exhibits Common-Mode to Differential conversion which is critical problem.
53
D
SS
m
m
in,CM
X R
R
2g
1
g
V
V
+

−
=

)
R
(R
R
2g
1
g
V
V D
D
SS
m
m
in,CM
Y 
+
+

−
=

SS
m
D
m
in,CM
Y
X
DM
-
CM
R
2g
1
R
g
V
V
V
A
+

=


−

=
** P.N. Kondekar **

For Example
Let Input of differential → Differential Signal + Common Mode Noise
Because of the Mismatching in Drain Resistance (∆RD), there will be Common Mode
Differential Gain (ACM-DM)
This ACM-DM gain will convert input Common-mode Noise to Differential component
at the output.
54
** P.N. Kondekar **

Effect of High Frequency Input Common-Mode Signal (Noise)
As disturbance frequency of Vin,CM increases, VP disturbance also increases which
cause capacitance C1 will come into existence.
This C1 will shunt the tail current source introduce larger tail current variation.
Capacitance ‘C1’ arises from
a) Parasitic of current source itself
b) Source-Bulk junctions of M1 & M2
Even if output resistance of current source is high, common-mode to differential
conversion become significant at high frequencies.
55
** P.N. Kondekar **

Common-Mode Gain due to Mismatching in Transistor M1 and M2
• Mismatching in transistor can be because of
a) Change in dimension (W/L)
b) Threshold Voltage mismatch
• As transistors are not symmetric, M1 and M2 will carry slightly different current
for same Gate to Source voltage and exhibits unequal transconductance.
56
** P.N. Kondekar **

Common-Mode to Differential-Mode Gain (ACM-DM) Calculation
Method 1
VP = (I1 + I2).RSS (where I1 = gm1.VGS, I2 = gm2.VGS and I1 ≠ I2)
Also VP = I1.R1 and VP = I2.R2 (if RSS is divided into 2-parallel resistance R1 and R2)
R1 = RSS.(gm1 + gm2)/gm1 and R2 = RSS.(gm1 + gm2)/gm2
Circuit can again be divided into 2 separate circuits.
and same as
57
in,CM
D
SS
m2
m1
m1
X V
R
1
R
)
g
(g
g
V
+
+
−
=
in,CM
D
SS
m2
m1
m2
Y V
R
1
R
)
g
(g
g
V
+
+
−
=
** P.N. Kondekar **

Method 2
I1 = gm1.VGS and I2 = gm2.VGS
I1 = gm1.(Vin,CM – VP) and I2 = gm2.(Vin,CM – VP)
That is,
(gm1 + gm2)(Vin,CM – VP)RSS = VP
Therefore
Also VX = –gm1(Vin,CM – VP)RD
Putting value of VP in above equation, we get
and same
where Δgm = gm1 – gm2
There is conversion of Input Common-Mode to Output Differential-Mode
Note: This method can also be used to calculate CM Gain of ΔRD mismatching. 58
in,CM
SS
m2
m1
SS
m2
m1
P V
1
)R
g
(g
)R
g
(g
V
+
+
+
=
in,CM
D
SS
m2
m1
m1
X V
R
1
R
)
g
(g
g
V
+
+
−
= in,CM
D
SS
m2
m1
m2
Y V
R
1
R
)
g
(g
g
V
+
+
−
=
)
g
(g
R
1
R
Δg
V
V
V
A
m2
m1
SS
D
m
in,CM
Y
X
DM
-
CM
+
+
−
=
−
=
** P.N. Kondekar **

Example
Two different pairs are cascaded as shown.
M3 and M4 suffer from a gm mismatching of
∆gm, the total parasitic capacitance at node P
is CP and the circuit is otherwise symmetric.
What fraction of the supply noise appears as
differential component at the output?
(Assume λ = ɣ = 0)
Solution: Output of Pair 1 → Input of Pair 2 (neglecting capacitance b/w nodes A and B)
Supply noise appears at node A and B (or Input of Pair 2) with no attenuation.
Parasitic capacitance ‘CP’ is present with current source, so there will be conversion of
Input Common Mode to Differential Output. Taking magnitude of CM gain ‘ACM-DM’
RSS can be replaced by CP because RSS is high and CP provide
less resistance path to shunt tail current at high frequency
Note that increasing frequency ω, │ACM-DM│ increases i.e. capacitance effect become
more noticeable because it give less resistance path to shunt tail current. 59
2
Pω
2
m4
m3
D
m
DM
CM
C
1
)
g
(g
1
R
Δg
A
+
+
=
−
** P.N. Kondekar **

CMRR (Common Mode Rejection Ratio)
CMRR is ratio of Differential Mode Gain to Common Mode Gain
For meaningful comparison of differential circuits, the undesirable differential component
produced by CM variation must be normalized to get amplified differential output same
as input (excluding noise).
So Common-Mode Gain must be minimum as possible i.e. CMRR must be high for reliable
amplification.
For ideal case CM gain should be zero and CMRR should be infinite.
CMRR calculation (considering only gm mismatch)
1) Common Mode Gain
60
SS
m2
m1
D
m
DM
CM
)R
g
(g
1
R
Δg
A
+
+
=
−
DM
CM
DM
A
A
CMRR
−
=
** P.N. Kondekar **

2) Differential Mode Gain
Note: Finite impedance current source is assumed, so RSS has to be considered while
calculating differential gain.
Calculating VX/Vin1
Calculating VY/Vin1
61
)
g
(g
R
1
)g
.g
R
(1
R
R
g
1
g
1
R
V
V
m2
m1
SS
m1
m2
SS
D
SS
m2
m1
D
in1
X
+
+
+
−
=








+
−
=
)
g
(g
R
1
.g
.g
.R
R
R
g
1
R
R
g
1
g
1
R
V
V
m2
m1
SS
m1
m2
SS
D
SS
m1
SS
SS
m1
m2
D
in1
Y
+
+
=








+









+
=
** P.N. Kondekar **

Therefore,
same for Vin2,
For Differential Gain
As Vin1 = – Vin2
Therefore
where, gm denotes mean value, i.e. gm = (gm1 + gm2)/2
Note: Approximated result is only valid when gm1 ≈ gm2 (in the case of mismatching)
62
)
g
(g
R
1
.g
.g
.R
2R
.g
R
V
V
V
m2
m1
SS
m2
m1
SS
D
m1
D
in1
Y
X
+
+
−
−
=
−
)
g
(g
R
1
.g
.g
.R
2R
.g
R
V
V
V
m2
m1
SS
m2
m1
SS
D
m2
D
in2
Y
X
+
+
+
=
−
]
V
)][V
g
(g
R
[1
]
)V
.g
.g
.R
2R
.g
[(R
]
)V
.g
.g
.R
2R
.g
R
[(
V
V
V
V
A
in2
in1
m2
m1
SS
in2
m2
m1
SS
D
m2
D
in1
m2
m1
SS
D
m1
D
in2
in1
Y
X
DM
−
+
+
+
−
−
−
=
−
−
=
)]
g
(g
R
[1
)
.g
.g
4R
g
(g
2
R
2V
V
V
A
m2
m1
SS
m2
m1
SS
m2
m1
D
in1
Y
X
DM
+
+
+
+
=
−
=
)
R
2g
(1
Δg
g
2ΔΔ
)
.g
.g
4R
g
(g
A
A
CMRR SS
m
m
m
m
m2
m1
SS
m2
m1
DM
-
CM
DM
+

+
+
=
=
** P.N. Kondekar **

63
Differential Pair with MOS Loads
• Load of Differential Pair need not to be implemented using linear resistors.
• Diode-connected and Current-source loads can be used in place of linear resistors.
1) Differential Gain (diode-connected load)
Using Half circuit Concept – Current source node (VP) can be treated as ac ground
** P.N. Kondekar **

Therefore, Differential Gain of diode connected load is
2) Differential Gain (current-source load)
For current source load, we apply fixed bias at the gate of PMOS load.
Therefore simply ground the gate voltage VG3 to find RD i.e. no effect of gmP on
resistance RD = roP
Trade-Off caused by using Diode-connected Load
Diode-connected load consume voltage headroom, thus creating trade-off between
Output Swing, Voltage Gain and Input CM range.
• Increase in Voltage gain decreases Output Swing
To increase gain, (W/L)P must ↓ and overdrive
voltage of PMOS load ↑ (consume more voltage
headroom) which cause decrease in Output Swing and lowering Output CM level.
64
THN
GSN
THP
GSP
P
p
N
n
V
V
V
V
V
(W/L)
μ
(W/L)
μ
A
−
−

−

THN
GSN
THP
GSP
P
p
N
n
mP
mN
oP
oN
1
-
mP
mN
V
V
V
V
V
(W/L)
μ
(W/L)
μ
g
g
)
r
r
(g
g
A
−
−

−

−

−
=
)
oP
oN
mN
V r
(r
g
A −
=
** P.N. Kondekar **

• Increase in Voltage gain decreases Input CM range
Increase in gain will cause increase in overdrive voltage of PMOS
load i.e. |VGSP – VTHP|. High overdrive voltage can transfer Input
transistor M1 from saturation to triode region.
To compensate this, decrease in Input CM range will decrease
overdrive voltage of M1 (VGN – VTHN = Vin – VTHN) which will cause
Input transistor M1 to remain in saturation.
Improvement in circuit to alleviate the trade-off
where IN = IP (for above circuit)
To increase gain, (W/L)P have to decrease therefore |VGSP – VTHP| must increase
because to remain current constant (i.e. IN = IP) which results increase in voltage
headroom.
Now the idea is to decrease the gmP of load device by reducing the load current IP
rather than its aspect ratio (W/L)P (which is causing more voltage headroom).
65
THN
GSN
THP
GSP
P
p
N
n
mP
mN
V
V
V
V
V
(W/L)
μ
(W/L)
μ
g
g
A
−
−

−

−

P
N
I
I
** P.N. Kondekar **

*By adding extra Current Source with PMOS load will decrease it’s current load
i.e. IP decreases while IN remains constant (because left current will pass through
extra added current source).
For Example
Let current source (M5 and M6 ) carry 80%
of drain current of M1 and M2 i.e. 0.8(ISS/2)
Current through M3 and M4 will left to 0.2(ISS/2)
reduced by factor of 5.
[IN = ISS/2= 0.8(ISS/2) + 0.2(ISS/2)]
For given |VGSP – VTHP|,
IP is proportional to (W/L)P for fixed |VGSP – VTHP|
i.e. decreasing IP by factor of 5 will also lower (W/L)P by same factor.
As IP → IP/5, then (W/L)P → (W/L)P/5. Therefore gmP → gmP/5.
Thus Differential gain will approximately increase by 5 times without increasing the
overdrive voltage of PMOS load (which increase voltage headroom).
66
** P.N. Kondekar **

Differential Pair with Current Source load have relatively low small-signal gain –
in range of 10 to 20 (in submicron technologies)
To increase voltage gain → Increase Output impedance (of both PMOS & NMOS)
This can be done by Cascoding
|AV| =gm1.Rout = gm1(R1ǁR2 )
R1 = {[1 + (gm2 + gmb2)ro2]ro1 + ro2}
R2 = {[1 + (gm3 + gmb3)ro3]ro4 + ro3}
For typical values, approximate gain is
|AV| = gm1[(gm2ro2ro1)ǁ(gm3ro3ro4)]
Cascoding therefore increases the differential gain substantially but at the cost of
consuming more voltage headroom.
Note: Output CM level has to be defined for a high gain fully differential amplifier.
In Diode-connected Load – Output CM level is defined as VDD – VGSP .
In Current-source Load – Output CM level is not well defined.
67
** P.N. Kondekar **

Gilbert Cell
• A cell or block whose gain can be varied by a control voltage from positive to
negative or negative to positive value.
• A Differential pair’s gain is a function of gm and gm is a function of current. So
controlling current Iss of circuit can control the gain of Differential pair.
Variable Gain Amplifier “VGA” (using one Differential Pair)
• A Differential Pair whose gain can be varied using control voltage because
tail current is defined by control voltage and hence gain.
• |AV| = Vout/Vin can be varied from zero (if ISS = 0) to maximum value given
by voltage headroom limitations of device dimension.
68
** P.N. Kondekar **

Variable Gain Amplifier “VGA” (using two Differential Pair - A Gilbert Cell)
• An amplifier whose gain can be continuously varied from a negative value to a
positive value.
• Vout = Vout1 + Vout2 = A1.Vin + A2.Vin = (A1 + A2)Vin
(where gain A1 can vary from maximum positive value
to zero and gain A2 can vary from zero to maximum
negative value)
Also A1 and A2 is controlled by some control Voltage
Implementation of Gilbert Cell using Differential Amplifier
Consider two Differential Pairs that amplify the input by opposite gains.
69
** P.N. Kondekar **

70
1st differential amplifier’s gain A1 = Vout1/Vin = –gm.RD and
2nd differential amplifier’s gain A2 = Vout2/Vin = gm.RD
(gm denotes transconductance in equilibrium)
Vout = Vout1 + Vout2 = A1.Vin + A2.Vin (from Gilbert Cell)
Vout1 = RD.ID1 – RD.ID2 and Vout2 = RD.ID4 – RD.ID3 (from opposite gain Differential pairs)
Put in Gilbert Cell’s equation
Vout = Vout1 + Vout2 = RD(ID1 + ID4) – RD(ID2 + ID3)
So actual implementation is quite simple, rather adding Vout1 and Vout2, simply short
the corresponding drain terminals to sum the currents.
If I1 = 0, then Vout = + gmRDVin and
If I2 = 0, then Vout = – gmRDVin and
If I1 = I2, then Vout = 0 i.e. gain drops to zero
In Gilbert Cell, gain must change monotonically
(with same rate).
Therefore I1 and I2 must vary in opposite direction
such that gain changes monotonically.
** P.N. Kondekar **

If I1 and I2 vary in opposite direction (i.e. if I1↑ then I2↓ by same rate), then overall
gain changes from positive to negative or negative to positive with same rate.
What circuit is added so that current I1 and I2 can vary in opposite direction?
A differential Pair provides such characteristics.
In Gilbert Cell
• For a large │Vcont1 – Vcont2│, all of the tail current steered to one of the top
differential pairs and gain goes to its most positive or most negative value.
• M1, M2, M3 and M4 are identical while M5 and M6 are identical.
71
** P.N. Kondekar **

Application Of Gilbert Cell
• It is a ‘VGA’ which has application in system where the signal amplitude experience
large variations and hence requires inverse change in gain.
• Circuit is widely used in many analog system as voltage multiplier.
Vout is function of gm.Vin (i.e. Vout = gMRDVin where gM = goverall)
gM is function of (ISS)1/2 and ISS is function of (Vcont)2. Therefore gM is function of Vcont.
Vout is function of Vcont multiplied by Vin i.e. as voltage multiplier
Disadvantage in Gilbert Cell
Gilbert Cell consumes a greater voltage headroom than a simplified diff. pair because
the two differential pair M1-M2 and M3-M4 are stacked on top of differential pair M5-M6
Vcont – VTH5 ≤ VA for M5-M6 to be in saturation.
As VA↓ due to greater headroom
Therefore Vcont must be decreased so that
M5 or M6 will not goes into triode region.
(For Input CM level, VA = VB = VCM,in – VGS1)
VCM,cont ≤ VCM,in – (VGS1 – VTH5,6)
Control CM level must be lower that input CM level by at least to one overdrive voltage.
72
** P.N. Kondekar **

Gilbert Cell (by exchanging Control Voltage and Input Voltage)
• In previous Gilbert cell, we vary the gain through its tail
current by applying control voltage to bottom pair and
input signal to top pairs.
• In this Gilbert cell we exchange the order of input and
control voltage while still obtaining a VGA.
Idea is same as previous that convert the input voltage to
current by means of M5 and M6 and route current through
M1-M4 to output nodes.
Working
1) If Vcont (Vcont1 – Vcont2) is very positive
M1 and M3 are ON and Vout = gm5,6RDVin
2) If Vcont is very negative
M2 and M4 are On and Vout = – gm5,6RDVin
3) If Vcont is zero (i.e. Vcont1 = Vcont2)
M1-M4 carry equal current and Vout = 0 73
** P.N. Kondekar **

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