Digital Alarm Clock 446 project report

California State University Fullerton
Department of Computer Engineering
EGCP 446: Advanced Digital Design using Verilog HDL
Professor: Dr. Pradeep Nair
Digital Alarm Clock Verilog Project
Designed by:
1. Aakash Mhankale (803000470)
2. Deeksha Sivakumer (893513473)
3. Shreeyash Honrao ( 802673293)
Semester: Fall 2015
Date: 12/22/15

2
Content Page
1. Introduction / Objective 3
2. Design Description 5
3. Testing Methodology 10
a. Hardware Testing
i. Results
4. Discussion 10
5. Conclusions and Future Work 11
6. Equipment and Software 11

3
Introduction / Objectives
We implemented the digital clock that displays time in hours, minutes and seconds blinks
in between the hour and minute display. The objective of our project is to implement all
the basic functions of the digital clock which we find in our daily life routine. The
features like 24 hour display, clock, clock setting, alarm setting, alarm alert indicator.
List of features implemented:
1. time (24 hour format)
2. Clock setting functionality
3. Alarm time setting functionality
4. Alarm indicating Sound output
The design has been implemented on an Artix7 FPGA development board.
How to use:
The user can set the clock by selecting the set button and toggle between Hour and
minute to set the current time as well as for the alarm time.

5
Design Description
The board contains many I/O ports. The following input are given and we are using on
board 50 MHz crystal oscillator clock. 4 momentary-contact push buttons, 2 slide
switches, 8 seven segment display. The pin locations are defined in constraint file. The
constraint file is attached with the report.
Below is the Verilog code describes the I/O that is in the constraint file.
module digi(clk,rst,set1,tg,inc,dec,CA,CB,CC,CD,CE,CF,CG,AN,DP,ld,PWM,SD);
output PWM,SD;
input clk,rst,inc,dec,set1,tg;
output CA,CB,CC,CD,CE,CF,CG;
output [7:0]AN;
output DP,ld;
A full list of the inputs and output and their purpose is displayed below. This list
corresponds with the entity above, the design constraint file attached with the report.
Inputs:
1. Momentary Push Buttons:
a. Decrement of Hour and Minute
b. Increment of Hour and Minute
c. Toggle between current time and alarm time
2. Slide Switch:
a. Reset
b. Select 1
Outputs:
1. 8 Seven-Segment Display
2. Blinking LED second indicating decimal point
3. Alarm Alert ( LED / Sound)

6
Design Details - How the Clock was designed:
The FPGA board has an external oscillator that can generate the accurate clock speed, so
we can use FPGA to generate timing signals. THE FPGA also handles de-bouncing. In
clock module the clock divider counts up to 5000000 i.e. (0 to 49999999) for generating
clock signal with a 1 second period.
We want the decimal LED to flash like on for 0.5 second and off for 0.5 second so on and
off time is 1 sec. i.e. when a decimal point gets on and off it signifies 1 second. To
achieve this we are using counter process that will count from 0 to 49999999. So when
clock reaches at its max value it counter will reset to 0 and if not it will count up to
49999999 and will reset by inverting clk_snd.
Clock Conversion: -
always @(posedge clk)
begin
if(count_clk==49999999) begin
clk_snd<=~clk_snd;
count_clk<=0;
end
else begin
count_clk<=count_clk+1;
end
end
Seconds Logic: -
always @(clk_snd)
begin
if (clk_snd)
begin
temp_DP=1'b1;
temp_d_blink=7'b1110111;
end
else
begin
temp_DP=1'b0;
temp_d_blink=7'b1111111;
end
end

7
LED blinking logic
LED Logic:
The LED (Light Emitting Diode) is a semiconductor which emits light energy when there
is a flow of current through it. Current will flow only in one direction. An LED has very
low internal resistance, hence when left to itself; it might pass more current and will end
up burning up. Therefore, they require an external resistor to limit the current.
Most LED's have a current rating to determine the size of the resistor needed. The current
rating will tell you how much the maximum allowable current for the part is. In general,
the higher the flow of current, the brighter the LED glows.
LEDs have polarity that passes from anode to cathode to activate. The anode is
labelled a or + , and cathode is labelled k or -. The cathode is the short lead and there
may be a slight flat spot on the body of round and the anode is the longer lead. Usually,
these segments are connected together and are made as a common pin called as “common
cathode” or “common anode” devices.
Here, we have designed a seven-segment decoder by assuming a common anode device
and implemented it on FPGA using Verilog. A segment on common anode device is
visible when the input is cathode 0. Hence, the truth table is given as:
The circuitry for displaying the numbers consists of a combinational logic circuit which
accepts the 4 bit BCD input and generates seven output signals to control the individual
segments of a 7-segment display device.

8
Synthesis:
Device utilization summary:
---------------------------
Selected Device : 7a100tcsg324-1
Slice Logic Utilization:
Number of Slice Registers: 129 out of 126800 0%
Number of Slice LUTs: 316 out of 63400 0%
Number used as Logic: 316 out of 63400 0%
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 317
Number with an unused Flip Flop: 188 out of 317 59%
Number with an unused LUT: 1 out of 317 0%
Number of fully used LUT-FF pairs: 128 out of 317 40%
Number of unique control sets: 15

9
IO Utilization:
Number of IOs: 25
Number of bonded IOBs: 25 out of 210 11%
IOB Flip Flops/Latches: 1
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 2 out of 32 6%
Unit <digi> synthesized (advanced).
===============================================================
==========
Advanced HDL Synthesis Report
Macro Statistics
# RAMs : 5
32x14-bit single-port distributed Read Only RAM : 2
# Adders/Subtractors : 4
5-bit adder : 1
5-bit subtractor : 1
6-bit adder : 1
6-bit subtractor : 1
# Counters : 8
15-bit down counter : 1
2-bit up counter : 1
5-bit updown counter : 1
6-bit updown counter : 1
# Registers : 32
Flip-Flops : 32
# Comparators : 2
5-bit comparator equal : 1
6-bit comparator equal : 1
# Multiplexers : 59
1-bit 2-to-1 multiplexer : 14

10
Testing Methodology
Hardware Testing:
The primary means of testing for this design was using hardware. The design was
implemented by synthesizing the Verilog code, then generating a bit file using Xilinx ISE
tools. This bit file was downloaded to the NEXYS 4 Artix 7 development using Xilinx
Vivado. To complete the program download, I had to power the FPGA board by
plugging it into an USB cable to the FPGA board and the other end to the computer’s
USB port.
Results
The design is performing well as expected. Further, the clock’s functionality is working
properly. It is using all the 8 seven segment display. When the reset switch is works all
the LEDs will get 0 and u can set the time by selecting select switch and then toggling
between the hour and Minuit display to set the current as well as the alarm time by the
use of push buttons to increment or decrement the count.
The Alarm will ring when the current hour and Min exactly matches with the alarm set
time.

11
Discussions
Lessons Learnt:
Much was learnt while developing this project. We learnt how to implement hardware
using Verilog code. This includes learning about implementation of constraint file, input
and output buffers. We learnt how to use the development board’s display by
multiplexing the digit signal to the 7-segment decoder and also on how to divide down
the board’s internal clock to use it in the design. We also learnt in detail on how to work
with Xilinx Vivado 2015.2 and how to use Artix 7 FPGA development Kit.
Difficulties faced & How we overcame it:
The major difficulties we faced were that the hour display at eighth seven segment
display was displayed the same as the seventh seven segment display of the LED. Also,
the alarm was not ringing for a particular set/reset time. But we overcame these
difficulties by changing the “if..else” condition in our code and by setting the alarm in a
proper way and by correcting few human errors. Our alarm clock then worked perfectly
and did all the necessary functions that we initially designed it for.
Conclusion & Future work:
The clock’s display is fully functional and it is capable of using all the digits of the
seven-segment display. The alarm clock is also working as expected In future, we can
change the clock format from 24 hour to 12 hour A.M/P.M format and also we can make
few changes in the code and use it to display the date (in mm/dd/yyyy format) in LCD.
Equipment
1. Hardware Device:
a) Device Family: Artix 7
b) Device: XC7A100T
c) Package: CSG324
2. Software: Xilinx Vivado 2015.2

Digital Alarm Clock 446 project report

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