Digital integrated circuits

DIGITAL INTEGRATED CIRCUITS
Important characteristics of digital ICs
1. Fan out
2. Power dissipation
3. Propagation Delay
4. Noise Margin
5. Fan In
6. Operating temperature
7. Power supply requirements
FAN-OUT
The fan-out of a gate specifies the number of standard loads that can be connected to the output of the gate
without degrading its normal operation. A standard load is usually defined as the amount of current needed
by an input of another gale in the same logic family..
POWER DISSIPATION
The power dissipation is a parameter expressed in milli watts (mW) and represents the amount of power
needed by the gate. The number that represents this parameter does not include the power delivered from
another gate rather it represents the power delivered the gate from the power supply.
PROPAGATION DELAY
Propagation delay is the average transition delay time for the signal to propagate from input to output when
the signals change in value. It is expressed in ns.
NOISE MARGIN
It is the maximum noise voltage added to an input signal of a digital circuit that does not cause an
undesirable change in the circuit output. It is expressed in volts.
FAN IN
Fan in is the number of inputs connected to the gate without any degradation in the voltage level.
OPERATING TEMPERATURE
All the gates or semiconductor devices are temperature sensitive in nature. The temperature in which the
performance of the IC is effective is called as operating temperature. Operating temperature of the IC vary
from 00
C to 700
C.
DIGITAL IC FAMILIES
RTL – Resister Transistor Logic
DTL – Diode Transistor Logic
HTL – High Threshold Logic
I2
L – Integrated Injection Logic
TTL – Transistor Transistor Logic
ECL – Emitter Coupled Logic
MOS – Metal – Oxide Semiconductor Logic
CMOS– Complementary Metal – Oxide Semiconductor Logic
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Resister Transistor Logic (RTL)
The basic circuit of the RTL digital
logic family is the NOR gate shown
in Fig. Each input is associated with
one resistor and one transistor. The
collectors of the transistors are tied
together at the output.
The voltage levels for the circuit are
0.2 V for the low level(logic 0) and
from 1V to 3.6V for the high level (logic 1).
If any input of the RTL gate is high, the corresponding transistor is driven into saturation and the output goes
low, regard less of the states of the other transistors, If all inputs are low at 0.2 V, all transistors are cut off
because VBE < 0.6 V and the output of the circuit goes high.
Diode Transistor Logic (DTL)
The basic circuit in the DTL digital logic family is
the NAND gate shown in Fig. Each input is
associated with one diode. The diodes and the 5kΩ
resistor form an NAND gate. The transistor serves
as a current amplifier while inverting the digital
signal.
The two voltage levels are 0.2 V for the low level
and between 4 and 5 V for the high level. The
analysis of the DTL gate should conform to the
conditions for the NAND gate
If any input of the gate is low at 0.2V. The corresponding input diode conducts current through VCC and the
5kΩ resistor into the input node. The transistor is cut off with no drop across the 2-kΩ resistor and the output
voltage is high at 5V. If all inputs of the gate are high, the transistor is driven into the saturation region so the
output at the collector is zero.

Transistor Transistor Logic (TTL)
The original basic transistor- transistor logic (TTL) gate was a slight improvement over the DTL gate. As
TTL technology progressed improvements were added to the point where this logic family became widely
used in the design of digital systems.
There are several subfamilies or series of the TTL technology. The names and characteristics of eight TTL
series appear in Table below. Commercial TTL ICs have a number designation that starts with 74 and
follows with a suffix that identifies the series
The speed-power product is an important parameter used in comparing the various TTL series. The product
of the propagation delay and power dissipation the speed-power product is measured in picojoules (pJ). A
low value for this parameter is desirable because it indicates that a given propagation delay can be achieved
without excessive power dissipation and vice versa
Classification
1. Open-collector output
2. Totem-pole output
3. Three-state output
Open-Collector Output Gate
The basic TTL gate shown in Fig is a modified circuit of the DTL gate. The multiple emitters in
transistor Q1 are connected to the inputs, Most of the time these emitters behave like the input diodes in the
DTL gate, since they form a PN junction with their common base. The base-collector junction of Q1 acts as
another PN junction diode corresponding to D1 in the DTL gate. Transistor Q2 replaces the second diode.
D2 in the DTL gate.

The output of the TTL gate is taken from the open
collector of Q3. A resistor connected to must be inserted
externally to the IC package for the output to "pull up" to
the high voltage level when Q3 is off otherwise the output
acts as an open circuit. The two voltage levels of the TTL
gate are 0.2V for the low level and from 2.4V to 5V for
the high level.
The above fig shows open collector TTL NAND gate. If any
input is low, the corresponding base-emitter junction in Q1 is
forward biased. So Q1 ON making the transistor Q2 and Q3 to OFF state. The output becomes high level.
If all the inputs are high the emitter –base junction of transistor Q1 becomes reverse biased and comes to
OFF state. So the transistor Q2 and Q3 becomes ON state, the output becomes low level (zero).
Totem-Pole Output
The output impedance of a gate is normally a resistive
plus a capacitive load. The capacitive load consists of the
capacitance of the output transistor. The capacitance of
the fan-out gates and any stray wiring capacitance and
transistor saturation capacitance. When the output
changes from the low to the high state the output
transistor of the gate goes from saturation to cut-off and
the total load capacitance C charges exponentially from
the low to the high voltage level with a time constant
equal to RC
For the open-collector gate R is the external resistor marked RL. For a typical operating value of C = 15 pF
and RL = 4 kΩ the propagation delay of a TTL open-collector gate during the turnoff time is 35 ns.With an
active pull-up circuit replacing the passive pull-up resistor RL The propagation delay is reduced to 10 ns.
This configuration shown in Fig is called a totem-pole output because transistor Q4 sits upon Q3.
If any one of the input is logic 0(low level), the emitter base junction of transistor Q1 becomes forward
biased (Q1 ON), which makes the transistor Q2 to OFF state. So the transistor Q4 becomes ON and Q3
remains OFF state and the output goes to high level.

If all the inputs are at logic 1(high level). The emitter base junction of Q1 becomes reverse biased
(Q1 OFF), which makes the transistor Q2 to ON state. So the transistor Q4 becomes OFF and Q3 is ON
state. So the output changes from high to low level.
SCHOTTKY TTL GATE
As mentioned before, a reduction in storage time results in a
reduction in propagation delay. This is because the time
needed for a transistor to come out of saturation delays the
switching of the transistor from the on condition to the off
condition. Saturation can be eliminated by placing a Schottky
diode between the base and collector of each saturated
transistor in the circuit.
The Schottky diode is formed by the junction of a metal and
semiconductor. The voltage across a conducting Schottky
diode is only 0.4 V. compared with 0.7V in a conventional
diode. The presence of a Schottky diode between the base and collector prevents the transistor from going
into saturation. The resulting transistor is called a Schottky transistor. The use of Schottky transistors in a
TTL decreases the propagation delay without sacrificing power dissipation.
The Schottky TTL gate is shown in Fig note the special symbol used for the Schottky transistors and diodes.
The diagram shows all transistors except Q4 to be of the Schottky type. An exception is made for Q4, since
it does not saturate but stays in the active region. Note also that resistor values have been reduced in order to
decrease the propagation delay further.
Two new transistors Q5 and Q6, have been added, and Schottky diodes are inserted between each input
terminal and ground. There is no diode in the totem-pole circuit. However the new combination of Q5 and
Q4 still gives the two VBE drops necessary to prevent Q4 from conducting when the output is low.
The Darlington pair provides a very high current gain and extremely low resistance, exactly what is
needed during the low-to-high swing of the output, resulting in a decrease in propagation delay.
The diodes in each input shown in the circuit help clamp any ringing that may occur in the input lines. The
diodes connected to ground help clamp this ringing, since they conduct as soon as the negative voltage
exceeds 0.4V.

The emitter resistor of Q2 in totem pole has been replaced in a circuit consisting of transistor Q6 and
two resistors. The effect of this circuit is to reduce the turnoff current spikes discussed previously. The
analysis of such a circuit, whose operation help s to reduce the propagation time of the gate, is too involved
to present in this brief discussion.
Emitter Coupled Logic (ECL)
The basic ECL circuit is shown in the
Fig can be used as an inverter, if the
output is taken at Vo1 This basic
circuit can be expanded to more than
one input by making transistor Q1
parallel to the other transistors for
other inputs. By connecting one more
transistor Q in parallel with Q1 as
shown in the Fig the circuit becomes
a two input ECL OR/NOR Gate with
inputs A and B.
If both inputs A and B are low then both transistors Q and Q1 are in the OFF state. If either A or B is HIGH,
then accordingly either transistor Q or Q1 conducts and the transistors Q2 is in the OFF state, resulting in
HIGH state at its collector.
transistor Q3 and Q4 provide the necessary DC shift for voltage correction. Thus, if the output is
taken at Vol the circuit acts as a NOR Gate; if the output is taken at V02 it acts as an OR gate.
The propagation delay of the ECL gate is 2 ns and the power dissipation is 25 mw, giving a speed-
power product of 50, which is about the same as that for the Schottky TTL. The noise margin is about 0.3 V
and is not as good as that in the TTL gate.

Metal Oxide Semiconductor Logic (MOS)
The inverter circuit shown in Fig (a) uses
two MOS devices Q1 acts as the load
resistor and Q2 as the active device. The
load-resistor MOS has its gate connected to
VDD thus maintaining it in the conduction
stale.
When the input voltage is low (below VT)
Q2 turns off. Since Q1 is always on the
output voltage is about VDD.
When the input voltage is high (above VT) Q2 turns on Current flows from VDD through the load resistor Q1
and into Q2. The geometry of the two MOS devices must be such that the resistance of Q2 when conducting is
much less than the resistance of Q1 to maintain the output Y at a voltage below VT.
The NAND gate shown in Fig (b) uses transistors in series. Inputs A and B must both be high for all transistors
to conduct and cause the output to go low.
If either input is low the corresponding transistor is turned off and the output is high. Again the series
resistance formed by the two active MOS devices must be much less than the resistance of the load-resistance
formed by the two active MOS devices must be much less than the resistance of the load-resistor MOS.
The NOR gate shown in Fig (c) uses transistors in parallel. If either input is high the corresponding transistor
conducts and the output is low. If all inputs are low, all active transistors are off and the output is high.
Complementary Metal Oxide Semiconductor Logic (CMOS)
A basic inverter connection is shown in the Fig. The driver is transistor Q2 which is the n-channel
and Ql (p channel) acts as the load. Note that the drains are connected together to provide the output and that
the source and substrate are connected together. The source of p-channel device is connected to +VDD and
the source of n-channel is connected to ground. The gates of the two devices are connected together as a
common input.

Operation
When Vin is low, Q2 is OFF but Q1 is ON. This
means the output voltage is HIGH. On the other hand, When
Vin is HIGH, Q2 is ON and Q1 is OFF. In this case, the
output voltage is low. Since the output voltage is always
opposite in phase to the input voltage, the circuit acts as an
inverter.
The operation of CMOS transistors can be described by
(i) n-channel MOSFETs are turned ON by a positive gate
voltage.
(ii) p-channel MOSFETs are turned ON by a negative gate voltage.
In the CMOS digital circuits the power consumption is very low and this is the reason for the
popularity of the CMOS devices in pocket calculators digital Wrist watches and portable microcomputers.
Propagation delay is about 25 to 100ns
CMOS NAND GATE (74C00)
A two input NAND gate which
consists of two p-type units in parallel and
two n-type units in series shown in the Fig
Notice that Q1 and Q2 form one
complementary connection Q3 and Q4
form another.
If both inputs are high, both p-
channel transistors turn OFF and both n-
channel transistors turn ON. The output has
low impedance to ground and produces a
low state. If any input is low, the associated n-channel transistor is turned off and p-channel transistor is
turned ON. The output is coupled to +VDD and goes to the HIGH state. This functions as a logic NAND gate.
[To produce AND logic the output of the CMOS NAND gate can be connected to a CMOS inverter]

CMOS NOR GATE
Two inputs A and B either of the inputs
can turn ON the PMOS of NMOS device
connected to it. The Fig shows the CMOS NOR
Gate. When both inputs are low, both PMOS
devices are driven ON: and both NMOS devices
OFF. The output is coupled to +VDD and goes to
the high state.
If any input is BIGH the associated p-
channel transistor is turned OFF and the n-
channel transistor turns ON. This connects the
output to the ground causing a low output.
Thus this circuit functions as a NOR gate A CMOS OR Gate can be formed by combining the output of the
CMOS NOR Gate with a CMOS inverter.
COMPARISON OF LOGIC FAMILIES
Logic family
Propagation
delay (ns)
Power
dissipation
per gate
(mW)
Noise
morgin (v)
Fan-in Fan-out cost
RTL 12 20 3.4 - 5 Low
DTL 12 9 2.5 3 8 Low
TTL 9 10 0.4 8 10 Low
ECL 1 50 0.25 5 10 High
MOS 50 0.1 1.5 - 10 Low
CMOS <50 0.001 5 10 50 Low
IIL 1 0.1 0.35 5 8 Very low
Integrated Circuits:
An integrated circuit (IC) is a miniature, low cost electronic circuit consisting of
active and passive components fabricated together on a single crystal of silicon. The
active components are transistors and diodes and passive components are resistors and
capacitors.
Advantages of integrated circuits:
 Miniaturization and hence increased equipment density.
 Cost reduction due to batch processing.
 Increased system reliability due to the elimination of soldered joints.

 Improved functional performance.
 Matched devices.
 Increased operating speeds.
 Reduction in power consumption
Step 1: Wafer preparation
A p type silicon bar is taken and cut into thin slices called wafers, these wafers after being lapped
and polished to mirror finish serve as the base or substrate for hundreds of ICs, the enlarged views of the
circular and reactangular wafers are shown separately.
Fig 1 (a): P-Type Silicon Crystal Fig 1 (b) : Wafer Fig 2 : Rectangular Wafer

Step 2: Epitaxial growth
As shown in figure an N type of silicon layer is now grown
on the p type substrate by placing the wafer in a furnace a at 1200°
C and introducing a gas containing phosphorus (donor impurity). It
is in this epitaxial layer that all active and passive components of an
IC are formed. This layer ultimately becomes the collector for transistor or an element for a diode or a
capacitor.
Step 3: Oxidation Step
In order to prevent the contamination of the epitaxial layer, a thin layer
of SiO2 is formed over the entire surface, as illustrated in fig. The SiO2 layer is
grown by exposing the epitaxial layer to an oxygen atmosphere to about
1,000o
C. This surface layer of SiO2 will prevent any impurities from entering
the N-type epitaxial layer. However, selective etching of this layer will permit
the diffusion of the proper impurity into designed areas of the N-type epitaxial region of the silicon wafer.
Step 4: Photolitho-graphic Process
This involves selective etching of Sio2 layer with the help of photographic mask, photo-resist and
etching Solution. It helps to select particular areas of the N-layer which are subjected to an isolation
diffusion process
step 5: Isolation Diffusion
SiO2 layer is removed from
the desired areas (four selected
portions from the wafer, as illustrated
in fig 6 using photolithographic
etching process explained above.
The remaining SiO2 layer

serves as mask for the diffusion of acceptor impurities. The wafer is now subjected to isolation diffusion at a
suitably high temperature and for appropriate time period allowing P-type impurity (boron in this case) to
penetrate into the N-type epitaxial layer through the openings in SiO2 layer and ultimately reach the P-type
substrate.
The temperature and time period of diffusion are required to be carefully controlled. The process
results in formation of N-type regions, called the isolation islands. Then name is given as they are separated
by back-to-back P-N junctions.
Step: 6 Base and emitter Diffusion
The p type base of transistor is now diffused into the N-type layer
which itself act as collector. The sequence of steps is same as in 4
and 5 above i,e., by the use of photo-resist and mask which creates
windows in the Sio2 layer as shown in fig. it is carried out in a
phosphorus atmosphere. Next, N type emitter is diffused into the base
after another photo-resist and mask process as shown in fig.
Step 7: Pre-ohmic Etch
For good metal ohmic(non- Rectifying) contact with diffused layers, N regions are diffused into the
structure as shown in Fig. this is done once again by the Sio2 layer , photo-resist and masking process.
Step 8: Metallization
It is done for making interconnections and
providing bonding pads around the circumference
of the chip for later connection of wires.
Step 9: Circuit probing
Each IC on the wafers is checked
electrically for proper performance by placing
probes on the bonding pads.
Step 10: Scribing and separating into chips
Once the metallization is complete, wafer is broken down into individual chips containing the
integrated circuits. For this purpose, wafers are first scribed with a diamond tipped tool and then separated
into single chips.

Step 11: Mounting and packing
The individual chip is very small and brittle. Hence, it is cemented or soldered to a gold plated header
through which leads have already been connected.
Step 12: Encapsulation
A cap is now placed over the circuit and sealing is done in an inert atmosphere.
Fabrication of Components on Monolithic IC
The outstanding feature of an IC is that is comprises an number of circuit elements inseparably associated in
a single small package to perform a complete electronic circuit. We shall now see how various circuit
elements (such as transistors, diodes, resistors etc.) can be fabricated in an IC form.
Diodes and Transistors
Diodes and transistors are usuallyformed using the epitaxial planar diffusion process described previous article.
Diodes
One or more diodes are formed by diffusing one or more small n-type deposits at appropriate locations on
the substrate.
Fig. 1 shows how a diode is formed on a portion of substrate of a monolithic IC.
1. Part of SiO2 layer is etched off, exposing the epitaxial layer as shown in Fig. 1 (i). The wafer is then put
into a furnace and trivalent atoms are diffused into the epitaxial layer. The trivalent atoms change the
exposed epitaxial layer from n-type semi-conductor to p-type.
2. Thus we get an island of n-type material under the SiO2 layer as shown in Fig. 1 (ii).

3. Next pure oxygen is passed over the wafer to form a complete SiO2 layer as shown in Fig. 1 (iii).
4. A hole is then etched at the centre of this layer ; thus exposing the n-epitaxial layer [See Fig. 1 (iv)].This
hole in SiO2 layer is called a window. Now we pass trivalent atoms through the window.
5. The trivalent atoms diffuse into the epitaxial layer to form an island of p-type material as shown in Fig. 1 (v).
6. The SiO2 layer is again formed on the wafer by blowing pure oxygen over the wafer [See Fig. 1
(vi)].Thus a p-n junction diode is formed on the substrate .The last step is to attach the terminals. For this
purpose, we etch the SiO2 layer at the desired locations as shown in Fig 2 (i).
Fig 2
By depositing metal at these locations, we make electrical contact with the anode and cathode of the
integrated diode. Fig. 2 (ii) shows the electrical circuit of the diode .
Transistor
Transistors are formed by using the same principle as for diodes. Fig. 3 shows how a transistor is
formed on a portion of the substrate of a monolithic IC. For this purpose, the steps used for fabricating the
diode are carried out upto the point where p island has been formed and sealed off [See Fig. 1 (vi) above].

This Fig. is repeated as Fig. 3 (i) and shall be taken as the starting point in order to avoid repetition.
Fig 3
1. A window is now formed at the centre of SiO2 layer, thus exposing the p-epitaxial layer as shown in
Fig. 3 (ii).
2. Then we pass pentavalent atoms through the window. The pentavalent atoms diffuse into the
epitaxial layer to form an island of n-type material as shown in Fig. 3 (iii).
3. The SiO2 layer is re-formed over the wafer by passing pure oxygen [See Fig. 3 (iv)].
4. The terminals are processed by etching the SiO2 layer at appropriate locations and depositing the
metal at these locations as shown in Fig. 3 (v). In this way, we get the integrated transistor.
5. Fig. 3 (vi) shows the electrical circuit of a transistor.
Resistors
Fig. 4 shows how a resistor is formed on a portion of the substrate of a monolithic IC.
Fig 4
1. For this purpose, the steps used for fabricating diode are carried out upto the point where n island has
been formed and sealed off [Refer back to Fig. 1 (iii)].
2. This figure is repeated as Fig. 4 (i) and shall be taken as the starting point in order to avoid repetition.

3. A window is now formed at the centre of SiO2 layer, thus exposing the n-epitaxial layer as shown in
Fig. 4 (ii). Then we diffuse a p-type material into the n-type area as shown in Fig. 4 (iii).
4. The SiO2 layer is re-formed over the wafer by passing pure oxygen [See Fig. 4 (iv)].
5. The terminals are processed by etching SiO2 layer at two points above the p island and depositing the
metal at these locations [See Fig. 4 (v)].
Capacitors
Fig. 5 shows the process of fabricating a capacitor in the monolithic IC.
1. The first step is to diffuse an n-type material into the substrate which forms one plate of the capacitor
as shown in Fig. 5 (i).
2. Then SiO2 layer is re-formed over the wafer by passing pure oxygen as shown in Fig. 1 (ii).
3. The SiO2 layer formed acts as the dielectric of the capacitor.
4. The oxide layer is etched and terminal 1 is added as shown in Fig. 5 (iii).
5. Next a large (compared to the electrode at terminal 1) metallic electrode is deposited on the SiO2
layer and forms the second plate of the capacitor.
6. The oxide layer is etched and terminal 2 is added. This gives an integrated capacitor.
7. The value of capacitor formed depends upon the dielectric constant of SiO2 layer, thickness of SiO2
layer and the area of cross-section of the smaller of the two electrodes.
Integrated JFET
The basic processes used for the fabrication of JFET are exactly similar to those used in the fabrication of
BJT. The JFETs are further classified as n-channel JFET and p-channel JFET. The development of n-
channel JFET is as shown in the Fig. 1.25.

the JFET, the epitaxial layer is used as n-channel.
The p+ gate is formed in n-type channel by ion-
implantation or diffusion process. While good ohmic
contacts are_ achieved by using n+ diffusion layers
below drain and source regions.
Integrated MOSFETs
MOSFETs are classified as follows
 enhancement mode MOSFET
 depletion mode MOSFET
In MOSFETs gate terminal is isolated from the FET channel by silicon dioxide insulating layer. As the layer
is insulating type, it provides very high input resistance. In providing superior barrier for impurities
penetrating Si02 layer, silicon nitride (Si3N4 ) is sandwitched between two silion dioxide (Si02) layers. This
helps in increasing overall dielectric constant.
The n-channel MOSFET of enhancement and depletion mode are as shown in the Fig. 1.26 (a) and (b)
respectively.
Integrated CMOSs
When n-channel MOSFET and p-channel MOSFET both are integrated on same chip, the device is termed
as complementary CMOS. In CMOS fabrication, n-type well is diffused in p-type substrate. Also p-
channel MOSFET is fabricated within this n-well. Basically this n-well forms substrate for p-channel
MOSFET. In the fabrication of p-channel MOSFET two additional steps are required as compared to n-
channel MOSFET fabrication. The additional steps are formation of n-well and ion-implantation of p-type
source and drain regions. The cross section of CMOS IC is as shown in the Fig. 1.27.

The CMOS can be fabricated using different processes such as:
 N-well process for CMOS fabrication
 P-well process
 Twin tub-CMOS-fabrication process
The fabrication of CMOS can be done by following the below shown twenty steps, by which CMOS can be
obtained by integrating both the NMOS and PMOS transistors on the same chip substrate. For integrating
these NMOS and PMOS devices on the same chip, special regions called as wells or tubs are required in
which semiconductor type and substrate type are opposite to each other.
A P-well has to be created on a N-substrate or N-well has to be created on a P-substrate. In this article, the
fabrication of CMOS is described using the P-substrate, in which the NMOS transistor is fabricated on a P-
type substrate and the PMOS transistor is fabricated in N-well.
The fabrication process involves twenty steps, which are as follows:
Step1: Substrate
Primarily, start the process with a P-substrate.
Step2: Oxidation
The oxidation process is done by using high-purity oxygen and hydrogen,
which are exposed in an oxidation furnace approximately at 1000 degree
centigrade.

Step3: Photoresist
A light-sensitive polymer that softens whenever exposed to light is called as
Photoresist layer. It is formed.
Step4: Masking
The photoresist is exposed to UV rays through the N-well
mask
Step5: Photoresist removal
A part of the photoresist layer is removed by
treating the wafer with the basic or acidic
solution.
Step6: Removal of SiO2 using acid etching
The SiO2 oxidation layer is removed through
the open area made by the removal of
photoresist using hydrofluoric acid.
Step7: Removal of photoresist
The entire photoresist layer is stripped off, as
shown in the below figure.
Step8: Formation of the N-well
By using ion implantation or diffusion process N-well
is formed.
Step9: Removal of SiO2
Using the hydrofluoric acid, the remaining SiO2 is
removed.
Step10: Deposition of polysilicon
Chemical Vapor Deposition (CVD) process is
used to deposit a very thin layer of gate oxide.

Step11: Removing the layer barring a
small area for the Gates
Except the two small regions required for
forming the Gates of NMOS and PMOS,
the remaining layer is stripped off.
Step12: Oxidation process
Next, an oxidation layer is formed on this
layer with two small regions for the
formation of the gate terminals of NMOS
and PMOS.
Step13: Masking and N-diffusion
By using the masking process small gaps are made for the purpose of N-diffusion.
The n-type (n+) dopants are diffused or ion implanted, and the three n+ are formed for the formation of the
terminals of NMOS.
Step14: Oxide stripping: The
remaining oxidation layer is
stripped off
https://www.edgefx.in/understanding-cmos-fabrication-technology/
Step15: P-diffusion :Similar to the above N-
diffusion process, the P-diffusion regions are
diffused to form the terminals of the PMOS.
Step16: Thick field oxide:A thick-
field oxide is formed in all regions
except the terminals of the PMOS and
NMOS.

Step17: Metallization :Aluminum is
sputtered on the whole wafer.
Step18: Removal of excess metal :The
excess metal is removed from the wafer
layer
Step19: Terminals: The terminals of the
PMOS and NMOS are made from
respective gaps
Step20: Assigning the names of the terminals of the NMOS and PMOS
Fabircation of CMOS using P-well process
Among all the fabrication processes of the CMOS, N-well process is mostly used for the fabrication
of the CMOS. P-well process is almost similar to the N-well. But the only difference in p-well process is that
it consists of a main N-substrate and, thus, P-wells itself acts as substrate for the N-devices.
Twin tub-CMOS Fabrication Process
In this process, separate optimization of
the n-type and p-type transistors will be
provided. The independent optimization of
Vt, body effect and gain of the P-devices, N-
devices can be made possible with this
process.
Different steps of the fabrication of the

CMOS using the twintub process are as follows:
 Lightly doped n+ or p+ substrate is taken and, to protect the latch up, epitaxial layer is used.
 The high-purity controlled thickness of the layers of silicon are grown with exact dopant
concentrations.
 The dopant and its concentration in Silicon are used to determine electrical properties.
 Formation of the tub
 Thin oxide construction
 Implantation of the source and drain
 Cuts for making contacts
 Metallization
By using the above steps we can fabricate CMOS using twintub process method
I2
L logic
IIL logic circuits are constructed using BJT only
1. Basic logic units use multi collector
NPN transistor which are powered from
PNP transistor.
2. Due to absence of resistor, it use very
small silicon chip area even a complete
microprocessor can be obtained in single
chip.
3. Easily fabricated and economical
4. Power consumption is low and speed
power product is constant
5. IIL has propagation delay is 1ns and
power dissipation is 1mw
6. Fan out of 8 and noise margin of 0.35V
Sample circuit diagram

Digital integrated circuits

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