Unit 5 session 4

Mrs. P.Sivalakshmi
Assistant Professor/ECE
R.M.K College of Engineering & Technology
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

■ Resistor Transistor Logic.
■ Transistor-Transistor Logic.
■ Emitter coupled Logic.

RTL is the first logic family which is not
available in monolithic form.
The basic circuit of the RTL logic family is the
NOR.
Each input is associated with one resistor and
one transistor.

•• The input and Base are connected to VCC
•• Base-Emitter voltage VBE > 0.7v
•• Base-Emitter junction is forward biased
•• Base-Collector junction is forward biased
•• Transistor is “fully-ON” ( saturation region )
•• Max Collector current flows ( IC = Vcc/RL )
•• VCE = 0 ( ideal saturation )
•• VOUT = VCE = ”0″
•• Transistor operates as a “closed switch”
•• The input and Base are grounded ( 0v )
•• Base-Emitter voltage VBE < 0.7v
•• Base-Emitter junction is reverse biased
•• Base-Collector junction is reverse biased
•• Transistor is “fully-OFF” ( Cut-off region )
•• No Collector current flows ( IC = 0 )
•• VOUT = VCE = VCC = ”1″
•• Transistor operates as an “open switch”

➢ The collector of the transistor are tied together
at the output
➢ The voltage levels for the circuit are 0.2v for the
low level and from 1 to 3.6v for the high level
CIRCUIT DIAGRAM

Working:
➢ If any input is high. The corresponding
transistor is driven into saturation and the
output goes low, regardless of the states of the
other transistor.
➢ If all inputs are low. Then all transistor are in
cutoff state and the output of the circuit goes
high.

RTL Characteristics
It has a fan-out of 5.
Propagation delay is 25 ns.
Power dissipation is 12 mw.
Noise margin for low signal input is 0.4 v.
Poor noise immunity.
Low speed.

➢ It can perform many digital function and have
achieved the most popularity.
➢ TTL IC are given the numerical designation as
5400 and 7400 series
➢ The basic circuit of TTL with totem pole output
stage is NAND gate

➢ TTL uses a multi-emitter transistor at the input
and is fast saturation logic circuit.
➢ The output transistor Q3 and Q4 form a totem-
pole connection.
➢ This extra output stage is known as totem-pole
stage because three output components Q3 and
Q4 and Diode are stacked on one another.

➢ This arrangement will increase the speed the
speed of operation and also increase output
current capability.
➢ The function of diode in this circuit prevent
both Q3 and Q4 being turned ON
simultaneously

Working
• When A=0,B=0;A=1,B=0;A=0,B=1;
➢ The emitter base junction ofQ1 turns on.
➢ The collector potential ofQ1 falls to 0v,then
Q2 turns off.
➢ Therefore, at point M we have 0volt i.e., the
base voltage of Q2 is 0volt.

➢ So that, Q2 is also turns off.
But at the same time we have L=+VCC, this
voltage is applied on the base of Q4
➢ As a result transistor Q4 is turned ON.
➢ Therefore, the output voltage is given by
➢ V0=+VCC-[Voltage dropin R4+drop in diode ‘D’]
Working

A=1,B=1;
➢ When both input are high then emitter base
junction of transistor Q1 becomes reverse bias.
Hence Q1 is turned off.
➢ However its collector base junction is forward bias,
supplying base current to the transistor Q2. Hence
Q2 turns ON.
➢ As a result collector potential of Q2 becomes “0”
volts.

➢ Now if L=0volt is applied to the base of Q3, it
is turns off .
➢ At the same time Q4 is turn ON. Then its
collector potential nearly equal to 0volts.
➢ Hence the output is low or logic o.
Working

characteristics
Power dissipation is 10mw.
It has fan-in of 8 and fan-out of 10.
Propagation time delay is 5-15nsec.
TTL has greater speed than RTL,DTL.
Less Noise immunity (Noise margin=0.4mV)

➢ ECL is non saturated digital logic family.
➢ The output of ECL provides OR and NOR
function.
➢ Each input is connected to the base
of transistor.

The circuit consists of three parts.
1.differential input amplifier.
2.Internal temperature and voltage compensated
bias network.
3.emittor follower output.
The emitter output requires a pull down resistor
for current flow.
In this logic family we consider the logic 0 as
-1.6v and logic 1 as -0.8v.

working:-
A=0,B=0;
• If all inputs are at low level(-1.6v),the transistor
are turn OFF and Q3 conducts .
• Then at point L the potential is 0volts is applied
to the base ofQ5,it is to be turn OFF.
• So, the output of OR gate is logic ‘o’.
• At the same time , the potential at point M= vcc
is applied to the base ofQ6,it is to be turn ON.
• So, the output ofNOR is at logic 1.

A=0,B=0,A=0,B=1,A=1,B=0
• The corresponding transistor is turned ON and
Q3is turned OFF.
• Becauseits voltage needs at least 0.6v to start
conduction on.
-0.8v
apply
causes the transistor to
-1.6v on the remaining
• An input of
conduct and
emitters

• Therefore,Q3 is cut off. The voltage in resistor
R2 flows into the base of Q5(L=Vcc) then Q5 is
turned ON.
• The output is at logic 1.
• At the same time, at point M the voltage is 0v
is applied to the base of the transistor Q6,it is
to be turns off. So, the NOR output is logic 0.

Characteristics
➢ Propagation delay is very LOW(<1ns)
➢ ECL is fastest logic family.
➢ ECL circuit usually operate with –Ve supplies
(+Ve terminal is connected to ground).

Unit 5 session 4

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Unit 5 session 4