Digital electronics logic families
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This document provides an overview of different digital logic families. It begins by introducing logic gates and integrated circuits. It then classifies logic families as either bipolar or unipolar, and lists examples of each. Key specifications of digital ICs are defined, including propagation delay, fan-in/fan-out, input/output logic levels, and noise margin. Transistor-transistor logic (TTL) and complementary metal-oxide-semiconductor (CMOS) circuits are described. The TTL NAND gate uses multiple emitter transistors while the CMOS NAND gate uses both P-channel and N-channel MOSFETs. Emitter-coupled logic (ECL) provides the fastest
![9. EMITTER COUPLED LOGIC(ECL)
ECL is the fastest among all logic families
The basic component is current switch or difference
amplifier with out-of phase output .
This reason ECL is known as Current Mode Logic(CML)
Transistor operates on Non- saturated at limited collector
current, so the emitter coupling is used, it doesn't allow
transistor to saturate.
ADV: [1]. So switching speed is high, [2]. propagation
delay is >3ns and [3]High Fan – in & out.
DIS: [1] Highest power dissipation [2] additional reference
voltage source. so it is used in Superfast computing.](https://image.slidesharecdn.com/digitalelectronicslogicfamilies-190628101225/85/Digital-electronics-logic-families-31-320.jpg)
Digital electronics logic families
- 1. UNIT - 2 LOGIC FAMILIES Digital Electronics By R. Blessina Preethi.. M.E Assistant Professor
- 2. CONTENTS 1. Introduction 2. Classification of Logic Families 3. Important point 4. Level of Integration 5. Specification of Digital ICs 6. TTL Circuit 7. TTL NAND Gates 8. MOS/CMOS Circuits 9. CMOS NAND Gate 10. ECL Circuit 11. Comparison 12. Numbers of Digital ICs
- 3. 1. INTRODUCTION Logic gates are available in the form of Integrated circuit( IC’s) As per the level of integration, the IC’s can accommodate more number of logic gates and digital functions. These forms are referred as logic family
- 4. 2.CLASSIFICATION OF LOGIC FAMILIES Digital Logic Families Bipolar logic family Saturated Resistor Transistor Logic(RTL) Direct coupled transistor logic(DCTL) Integrated Injection Logic(IIL) Diode Transistor Logic (DTL) High Threshold Transistor Logic Transistor – Transistor Logic (TTL) Standard TTL High Power TTL Low Power TTL Low Power Schottly Schottly Non Saturated Schottly TTL Emitter Coupled Logic (ECL) Uni polar logic family P MOS N MOS C MOS
- 5. 3. IMPORTANT POINTS The digital familiy is categorized by two types (i)Bipolar and (ii) Unipolar In Saturated Bipolar logic families, the transistor in the IC driven in to saturation. In Non Saturated Bipolar logic families, the transistor in the IC not driven in to saturation In PMOS & NMOS Unipolar logic family only P & N channel MOSFETs are used. CMOS Unipolar logic family both P& N- channel MOSFETs are used. All family same logic level & same Voltage.
- 6. 4. LEVEL OF INTEGRATION Number of gates fabricated in single IC There are 4 generation Small Scale Integration (SSI) = 12 gates in 1 Chip Medium Scale Integration (MSI) = 12 to 100 gates Large Scale Integration(LSI)= 100 to 1000 gates Very Large Scale Integration(VLSI)= Up to 1,00,000 or more
- 7. 5. SPECIFICATION OF DIGITAL IC’S Different types of ICs are manufactured, based on the components used and their interconnections. These ICs are compared using certain performance specifications. 1.Power Dissipation 2. Propagation Delay 3. Fan-In 4. Fan-Out 5. Input Logic Level 6. Output Logic Level 7. Compatibility 8. Noise Margin 9. Speed – Power Product
- 8. 1. POWER DISSIPATION This is the mean power of logic circuit draws from the supply during one complete cycle. This parameter is very important because if the power dissipation is large, then the life period of the IC is reduced. It should be noted that in one complete cycle, the IC is in logic ‘1’ for half the time and in logic ‘0’ during the remaining half. The power dissipation of a logic gate is equal to the de supply voltage (VCC) times the average supply current IC).
- 9. 2. PROPAGATION DELAY This parameter characterizes the speed of a logic circuit. The propagation delay of IC is the mean time required for a pulse to pass through the IC. It is thus defined as the time interval between a change in input and the resulting change in the output of an IC. It is represented by tp.
- 10. 4. FAN-OUT Fan in of a logic circuit gives the maximum number of inputs that can be connected to the logic circuit without impairing other primary parameters. 3. FAN-IN Fan-out of a logic circuit is the maximum number of outputs the circuit may have and still operate properly. The fanout is the limiting factor which determines the number of loads that the given data can drive.
- 11. 5. INPUT LOGIC LEVEL (VIL & VIH) If the input voltage level changes without changing the output, this is known as Input Logic Level . The input is either in logic 0 – low(0V)or logic 1 – High(+5 V) some tolerance is allowed to the input voltage. Eg: If the input voltage may change from 0V to 0.8V without changing the output level. This voltage of 0.87V is defined as the Maximum low input voltage (VIL). If the logic 1 may change from + 5V to + 2V without affecting, the output level, then the + 2V is known us the Minimum high level input voltage (VIH).
- 12. 6. OUTPUT LOGIC LEVEL The output voltage is at 0V for logic 0 and at 5V for logic 1. Eg: In supply voltage variations, voltage drop across resistors etc., so these voltages tend to vary. Thus any voltage say, from 0V to 0.4V is considered as low output. Similarly any voltage from 2.7V to 5V is considered as logic 1. Thus the worst-case output voltages are the Maximum low level output voltage (VOL) and the Minimum high level output voltages (VOH).
- 13. 7. COMPATIBILITY(ABILITY TO WORK WITH ANOTHER) Compatibility is defined as the ability of one device to drive the input of another device. If the output of one device is connected to the input of another device, for both the devices the the Input Logic Level and Output Logic Level must be same, then these two devices are compatible .
- 14. 8. NOISE MARGIN There is a minimum permissible variation between the drive device and the load device this difference is known as the noise margin. As long as the noise level of any stray interference picked by the various leads of the device is within this value of 0.4V the input of the load device is not affected
- 15. 9. SPEED – POWER PRODUCT It is specified by the manufacture as a measure of the performance of a logic circuit based on the product of the propagation delay time and the power dissipation at a specified frequency. It is expressed in the units of joules (J).
- 16. REVIEW OF SPECIFICATION OF DIGITAL IC’S 1.Power Dissipation 2. Propagation Delay 3. Fan-In 4. Fan-Out 5. Input Logic Level 6. Output Logic Level 7. Compatibility 8. Noise Margin 9. Speed – Power Product
- 17. IMPORTANT CIRCUIT(TOTEM POLE CIRCUIT) e
- 18. 6. TRANSISTOR –TRANSISTOR LOGIC(TTL) CIRCUIT The most widely used logic family is Transistor – Transistor Logic (TTL) It has Bipolar Transistor High Speed(tp= 10 ns) Low power dissipation Fan – In from 12 -14 Fan out equals to 10 or more
- 19. TTL NAND GATES The multi emitter transistor T1 is used to drive the output of T2 Inputs are given in Emitter of T1& output is taken from Collector of T2. Circuit of Emitter Coupled Logic
- 20. OPERATION If one of the input is ‘0’(LOW), the corresponding Emitter juction is forward biased (VE< VB) So T1 is in Saturation region (ON) & collector also biased to conduct but the voltage is low(0.3V) , this forces T2 OFF. Because the collector voltage of T1 is Base voltage of T2. So the output taken from the collector of T2 is HIGH ie “1” If both the input is HIGH then both emitter reverse bias so T1 is in CutOff (OFF) region , this increases collector voltage of T1 that Pulls T2 to Saturation (ON) thus the output is LOW(0) EMITTER INPUT T1 T2 COLLECTOR OUTPUT 0,0 0,1 1,0 SATURATION ON OFF HIGH= 1 HIGH= 1 HIGH= 1 1,1 CUT OFF OFF SATURATION ON LOW = 0
- 21. 6.1.OPEN COLLECTOR TTL NAND GATE 6.TTL NAND GATE
- 22. 6.1. OPEN COLLECTOR TTL NAND GATE In Open collector TTL circuit the output of T2 is given to input of T3 at base, the collector of it is open. The collector of T2 & collector of T3 in phase, so this works as NAND gate. This circuit needs an external Pull-Up resistor between the output and power supply for proper operation. Disadvantage: Low speed
- 23. OPEN COLLECTOR TTL NAND GATE Disadvantage: Low speed If the output has change from Low to High, the Transistor T3 has to change from saturation to cutoff. This means the charge carrier in the collector of T3 should be removed As the current path is through the pull up resistor, more time is taken to change the output from 0 to 1. This Disadvantage can be rectified by ‘Totem pole’.
- 24. 6.2. TOTEM POLE TTL NAND GATE In TTL Logic circuit there are three stages 1. Multi Emitter Input Stage - where T1 has multiple input in emitter 2. Phase splitter stage – in this the T2 acts as switch that makes if T3 ON then T4 OFF If T3 OFF then T4 ON 3. Totempole output stage- the out put is taken out between T3&T4. INP UT T1 T2 T3 T4 OUTP UT 0,0 0,1 1,0 SATURA TION OFF OFF SATURA TION 1/HIG H 1,1 CUTOFF SATURATI ON SATURA TION OFF 0/ LOW
- 25. 6.2. TOTEM POLE TTL NAND GATE In Totem pole NAND gate circuit, the output is taken from T3. When both input is ‘1’ then the T1 is in cutoff this makes T2 in saturation, so the current flows through T2&Re this makes T3 in Saturation. So the output Y is LOW. At this time T4 is also OFF(Vb<Ve) Base is not higher than Emitter Ve = D(0.8V)+T3(0.3V) Vb= T2(0.3V)+T3 –Veb (0.7V)
- 26. 6.2. TOTEM POLE TTL NAND GATE If any one of the input is made low ’0’ at T1 emitter , the corresponding emitter junction becomes conductive. This makes T1 on ,T2&T3 off and the T4 is ON that makes output High. Then the circuit act as NAND gate. So always one of the totem pole transistor is in ON state for giving low or High,the output impedance is low thus the extra charge carrier passes via ON transistor. ADVANTAGES: 1. Low propagation delay 2. Low output Impedance 3. High Fan out
- 27. 7. MOS/ CMOS CIRCUIT Metal Oxide Semiconductor(MOS) field effect transistor. There are 3 types P MOS- P- Channel MOSFET – slowest N MOS – N Channel MOSFET – Microprocessor & Memories C MOS (Complementary MOS) – both N& P Channel ADVANTAGES: LOW POWER DISSIPATION LOW NOISE HIGH FAN OUT HIGH SWITCHING SPEED BETTER COMPATIBILITY
- 28. 8. CMOS NAND GATE
- 29. 8. CMOS NAND GATE OPERATION Complementary MOSFET T1 & T2 are p-channel MOSFET T3 & T4 are n-channel MOSFET If inputs are high ‘1’ then p-channel MOSFET (T1 & T2 – OFF), n-channel MOSFET (T3& T4 – ON), so the output is low.
- 30. 8. CMOS NAND GATE OPERATION If any one of the input is high then the pmos transistor is OFF & its Combinational nmosTransistor is On For Eg: INPUT T1 T2 T3 T4 OUTPUT 0,0 ON ON OFF OFF 1/HIGH 0,1 ON OFF ON OFF 1/HIGH 1,0 OFF ON OFF ON 1/HIGH 1,1 OFF OFF ON ON 0/ LOW
- 31. 9. EMITTER COUPLED LOGIC(ECL) ECL is the fastest among all logic families The basic component is current switch or difference amplifier with out-of phase output . This reason ECL is known as Current Mode Logic(CML) Transistor operates on Non- saturated at limited collector current, so the emitter coupling is used, it doesn't allow transistor to saturate. ADV: [1]. So switching speed is high, [2]. propagation delay is >3ns and [3]High Fan – in & out. DIS: [1] Highest power dissipation [2] additional reference voltage source. so it is used in Superfast computing.
- 32. 9. ECR NOR GATE: OPERATION: If one of the input or all the input are high then the output is low because one or more transistor conducts. Output is high when all input is low
- 33. 10. COMPARISON OF TTL, CMOS & ECL LOGIC FAMILY S.N O CHARECERIZATION TTL CMOS ECL 1 GATES NAND NAND/NOR NOR 2 Noise ImmunityVin (V) 0.50 1.50 0.16 3 Fan out Fout >10 >10 >10 4 Fan in Fin 12 to 14 >10 >10 5 Propagation Delay tpd (ns) 15 15 < 3 6 Power Dissipation Pd (mw) 0.1 175 0.001
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