![Open Collector TTL
The collector point of Q4 is brought out of the
IC that is why it is called open collector TTL
For proper operation of this circuit 𝑅3
resistance has to be introduced externally. This
resistance is called pull up resistance
For A and B low: Q1 will be on Saturation
Mode, there will be no base current to Q2
making it in cut-off mode. This Q4 is also in
cut-off: O/P [High]
For A and B High: Q1 will be on Reverse Active Mode, there will be huge collector current of Q1 =n base
current of Q2 making it in saturation mode. This will allow large emitter current to flow, major of that flows to
base of Q4 setting it in saturation mode: O/P [Low]](https://image.slidesharecdn.com/yjdml7ssgwvjwydfc10g-lecture37-logic-family-complete-250114150028-92fe42dd/85/Lecture37_Logic_families_dcd_complete-pdf-43-320.jpg)
Lecture37_Logic_families_dcd_complete.pdf
- 1. Digital Circuit Design Logic Families By: Dr. Hemant Kumar
- 2. Classification Digital ICs Bipolar Saturated RTL (Resistor Transistor Logic) DCTL (Direct Coupled Transistor Logic) DTL (Diode Transistor Logic) TTL (Transistor- Transistor Logic) Unsaturated Schottky TTL ECL (Emitter Coupled Logic) Unipolar PMOS NMOS CMOS
- 3. BJT Reminder Region of Operation EBJ (J1) CBJ (J2) Saturation mode Forward Bias Forward Bias Active Mode Forward Bias Reverse Bias Reverse active mode or inverted mode Reverse Bias Forward Bias Cut-off mode Reverse Bias Reverse Bias
- 5. Voltage Transfer Characteristics Cut-off Region (OFF) Active Region (Ideally This Region should not exist as of now) Saturation Region (ON) For the case of Digital Circuits
- 6. Invertor Circuit Points: 1. Input (0) can be as low as zero so that BJT remains in cut- off i.e. O/C. 2. Input (1) can be sufficient to move BJT towards saturation region i.e. S/C. Qualitative View: 1. Taking 𝑉𝑖 as input signal and 𝑉 𝑜 as output signal 2. Case 1: for Low 𝑉𝑖 → 0 1. BJT will move to cut-off (OFF), 𝑉 𝑜 = 𝑉 𝑐𝑐 (High) 3. Case 2: for high 𝑉𝑖 → 1 1. BJT will move to saturation (ON), 𝑉 𝑜 is directly connected to ground, 𝑉 𝑜 → 0 (Low) 𝑨 𝒀 0 1 1 0
- 7. Invertor Circuit - VTC 𝑉 𝑜 𝑉𝐼 𝑉𝐼𝐿 𝑉𝐼𝐻 𝑉𝑂𝐻 𝑉𝑂𝐷 𝑉𝑂𝐿 𝑉𝑂𝐻 The insensitivity of inverter output to the exact value 𝑉𝐼 within allowed regions are important. 1. Output will be 𝑉𝑂𝐻 if 𝑉𝐼 does not exceed 𝑉𝐼𝐿 2. Output will be 𝑉𝑂𝐻 if 𝑉𝐼 does not go below 𝑉𝐼𝐻
- 8. Invertor Circuit – Noise Margin Thus, 1. 𝑉𝐼𝐿: It is the maximum value that 𝑉𝐼 can have while being interpreted by the inverter as representing a logic 0. 2. 𝑉𝐼𝐻: It is the maximum value that 𝑉𝐼 can have while being interpreted by the inverter as representing a logic 1. 3. In between these two points inverter will remain in transition region. Ideally that region should not exist 𝑣𝐼 𝑣𝑜1 𝑣𝑁 𝑣𝑖2 𝑣𝑜
- 9. Invertor Circuit – Noise Margin 𝑣𝑖2 = 𝑣𝑜1 + 𝑣𝑛 𝑣𝑛 can be positive or negative voltage Let, 𝑣01 = 𝑉𝑂𝐿 (0) Now, 𝑣𝑜 should be 𝑉𝑂𝐻 (1) This condition will hold as long as 𝒗𝒊𝟐 < 𝑽𝑰𝑳. Then maximum value of 𝒗𝒏 = 𝑽𝒊𝑳 − 𝑽𝑶𝑳 for which second inverter will function properly. 𝑁𝑀𝐿 = 𝑉𝐼𝐿 − 𝑉𝑂𝐻 Similarly 𝑁𝑀𝐻 = 𝑉𝑂𝐻 − 𝑉𝐼𝐻 Ideally: 𝑉𝐼𝐿 = 𝑉𝐼𝐻 = 𝑉𝑀 = 𝑉𝐷𝐷 2
- 10. Characteristics of Digital ICs • Fan Out • Fan In • Propagation Delay • Power Dissipation • Noise Margin/ Noise Immunity • Figure of Merit • Current and Voltage • Power Supply • Operating Temperature Range • Flexibility Available
- 11. Fan Out Fan out is some times also referred as loading Fan-out of a gate specifies the number of standard loads that can be connected to the output of the gate without degrading its normal operation The term loading is derived from the fact that the output if a gate can supply a limited amount of current above which it ceases and it is said overloaded Fan out is calculated from the amount of current available of a gate and the amount of current needed in each input stage
- 12. Fan Out Acting as current source (𝐼𝑂𝐻) Acting as current sink (𝐼𝑂𝐿) 𝐼𝐼𝐻 is the current required for loaded gates 𝐼𝐼𝐿 is the current supplied by each fan out gate
- 13. Fan Out Fan out is calculated from the ratio 𝐼𝑂𝐻/𝐼𝐼𝐻 or 𝐼𝑂𝐿/𝐼𝐼𝐿, whichever is small. For example: 𝐼𝑂𝐻 = 400 𝜇𝐴 𝐼𝐼𝐻 = 40 𝜇𝐴 𝐼𝑂𝐿 = 16 𝑚𝐴 𝐼𝐼𝐿 = 1.6 𝑚𝐴 Then, 𝐼𝑂𝐻 𝐼𝐼𝐻 = 400 40 = 10 = 𝐼𝑂𝐿 𝐼𝐼𝐿 = 16 1.6 Therefore fan-out is 10. Means no more than 10 gates can be connected at load
- 14. Power Dissipation Digital systems are implemented using very large numbers of logic gates. For space and other economic considerations When 𝒗𝒊 is low, there is no power dissipation When 𝒗𝒊 is high, 𝐼𝑐𝑠𝑎𝑡 current flows through 𝑅𝑐. Thus 𝑃𝑑 = 𝐼𝑐𝑠𝑎𝑡 2 𝑅𝑐 = 𝑉 𝑐𝑐 2 /𝑅𝑐 This is substantial for single device as we have millions of logic devices in VLSI The power dissipation when the logic is not switching is called static power consumption
- 15. Power Dissipation Assuming Load Capacitor High Level and Low Level will be These are the modified circuits with Pull-Up and Pull-Down resistances and does not dissipate any static power consumption But things slightly modifies as the load connected to logic have capacitance. As the inverter is switched from one state to another, current must flow through the switch(es) to charge (and discharge) the load capacitance. These currents give rise to power dissipation in the switches, called dynamic power dissipation. 𝐿𝑜𝑤 𝐻𝑖𝑔ℎ
- 16. Power Dissipation For 𝑣𝐼 → 𝐿𝑜𝑤 (0) 𝐿𝑜𝑤 𝐻𝑖𝑔ℎ 1. Capacitor will charge through 𝑅𝑃𝑈 2. Capacitor voltage will start rising from 0 to 𝑉𝐷𝐷 3. Instantaneous power drawn from 𝑉𝐷𝐷 𝑝𝐷𝐷 𝑡 = 𝑉𝐷𝐷𝑖𝐷(𝑡) Energy delivered by the power supply 𝐸𝐷𝐷 = න 0 𝑇𝑐 𝑉𝐷𝐷𝑖𝐷(𝑡) 𝐸𝐷𝐷 = 𝑉𝐷𝐷𝑄 𝑄 is the delivered charge to capacitor during the interval. As we have assumed initial charge zero 𝑄 = 𝐶𝑉𝐷𝐷 making 𝐸𝐷𝐷 = 𝐶𝑉𝐷𝐷 2
- 17. Power Dissipation 𝐿𝑜𝑤 𝐻𝑖𝑔ℎ We know energy stored by capacitor 𝐸𝑠𝑡𝑜𝑟𝑒𝑑 = 1 2 𝐶𝑉𝐷𝐷 2 Then dissipated energy will be 𝐸𝑑𝑖𝑠𝑖𝑝𝑎𝑡𝑒𝑑 = 𝐸𝐷𝐷 − 𝐸𝑆𝑡𝑜𝑟𝑒𝑑 = 1 2 𝐶𝑉𝐷𝐷 2 For 𝑣𝐼 → 𝐻𝑖𝑔ℎ (1) 1. Capacitor is charged to 1 2 𝐶𝑉𝐷𝐷 2 2. At the end of the cycle this completed stored energy will be dissipated against 𝑅𝑃𝐷 𝐸𝑑𝑖𝑠𝑖𝑝𝑎𝑡𝑒𝑑 = 1 2 𝐶𝑉𝐷𝐷 2 Thus for each cycle: 𝐸𝑑𝑖𝑠𝑠𝑖𝑝𝑎𝑡𝑒𝑑 𝑐𝑦𝑐𝑙𝑒 = 1 2 𝐶𝑉𝐷𝐷 2 + 1 2 𝐶𝑉𝐷𝐷 2 = 𝐶𝑉𝐷𝐷 2 For cycle of 𝑓 𝐻𝑧 𝑃𝑑𝑦𝑛 = 𝑓𝐶𝑉𝐷𝐷 2 Reducing 𝑉𝐷𝐷 reduces 𝑃𝑑𝑦𝑛. That's one motivation to move for small devices
- 18. Propagation Delay A very important measure of the performance of a digital system, such as a computer, is the maximum speed at which it is capable of operating. The core of this issue is time taken by logic to respond to a change at its input. 1. The output signal is no longer an ideal pulse. Rather, it has rounded edges; that is, the pulse takes some time to fall to its low value and to rise to its high value. 2. There is a time delay between each edge of the input pulse and the corresponding change in the output of the inverter. If we define the “switching point” of the output as the time at
- 19. Propagation Delay If we define the “switching point” of the output as the time at which the output pulse passes through the half-point of it excursion. 𝑡𝑝 = 1 2 (𝑡𝑃𝐻𝐿 + 𝑡𝑃𝐿𝐻) 𝑡𝑝 is propagation delay This can help to determine maximum switching frequency Minimum period for each cycle should at least Tmin = 𝑡𝑃𝐻𝐿 + 𝑡𝑃𝐻𝐿 = 2𝑡𝑝 Maximum frequency is 𝑓𝑚𝑎𝑥 = 1 𝑇𝑚𝑖𝑛 = 1 2𝑡𝑝
- 20. Other Properties Figure of Merit: The figure of merit of a logical family is the product of power dissipation and propagation delay. It is called the speed power product. The speed is specified in seconds and power is specified in 𝑊. 𝐹𝑜𝑀 = 𝑡𝑝 × 𝑃𝑑 Practically the value of figure of merit should be very small. Fan in: The number of inputs a logic can have, for example a two input AND gate has fan in of 2
- 21. Other Properties Current/Voltage: 𝑉𝐼𝐻= High level input voltage 𝑉𝐼𝐿= Low level input voltage 𝑉𝑂𝐿= Low level output voltage 𝑉𝑂𝐻= High level output voltage 𝐼𝐼𝐿= Low level input current 𝐼𝐼𝐻= High Level input current Flexibility : Compatibility or flexibility is defined as the ability of one device to derive the input of another device Power Supply Requirement : The amount of power required by IC is important as it will directly affect power dissipation Operating temperature range: Industrial (0°𝐶 to 70°𝐶), Military (−55 °𝐶 to 125 °𝐶)
- 22. Resistor Transistor Logic (RTL) 𝑨 𝒀 0 1 1 0 Inverter Circuit Disadvantages 1. Low Noise Margin 2. Lower Fan out 3. Slow speed 4. High power dissipation
- 23. Resistor Transistor Logic (RTL)- Invertor 50 𝑯𝒛 𝟓𝟎 𝑲𝑯𝒛 1 𝑴𝑯𝒛
- 24. Resistor Transistor Logic (RTL)
- 25. Resistor Transistor Logic (RTL) 𝑨 𝑩 𝒀 0 0 1 0 1 0 1 0 0 1 1 0 𝐴 𝐵 𝑂/𝑃 𝑌 Implemented a NOR gate using two transistors 𝟏𝟎 𝑲𝑯𝒛 5𝟎 𝑲𝑯𝒛
- 26. Direct Coupled Transistor Logic (DCTL) Low Low High A B O/P High Low Low
- 27. TTL Circuits Discussion 𝑨 𝑩 𝒀 0 0 0 0 1 0 1 0 0 1 1 1 Implemented a AND gate using two diodes
- 28. TTL Circuits Discussion We have prepared AND date using Diodes and Resistors, now we can look back and integrate RTL based inverter circuit with AND gate 𝑨 𝑩 𝒀 0 0 1 0 1 1 1 0 1 1 1 0 Implemented a NAND gate using two diodes and BJT with Resistors
- 29. TTL Circuits Discussion We have prepared AND date using Diodes and Resistors, now we can look back and integrate RTL based inverter circuit with AND gate If we apply low voltage (0.2V) at 𝐷1 or 𝐷2, diode will be turned ON (F.B). 𝐴 Issue with the structure: Then a potential of (0.7 V) also come across the diode. So the total potential at 𝑁𝑜𝑑𝑒 A is (0.9V) This potential is sufficient to turn on the BJT(saturation mode) whereas we are expecting BJT to remain in cut-off mode for low input from AND gate
- 30. TTL Circuits – First Modification In order to remove the issue of turning on BJT due to 0.9 V at Node A, we can introduce an additional diode against resistor R2 in base of the BJT 𝑨 𝑩 𝒀 0 0 1 0 1 1 1 0 1 1 1 0 Implemented a NAND gate using three diodes with BJT
- 31. TTL Circuits – First Modification In order to remove the issue of turning on BJT due to 0.9 V at Node A, we can introduce an additional diode against resistor R2 in base of the BJT Benefit: Now, 𝐷3 are biased with 0.9 V but have 𝐵𝐸𝐽 also in series so (0.9 V) is distributed between 𝐷3 and 𝐵𝐸𝐽 equally (0.45 V each). Thus, 𝐷3 will remain in off state and BJT will remain in cut-off mode increasing the noise margin of the circuit Problem: The circuit has a problem related to switching property. To switch the BJT from saturation to cu-off we have to remove excess base charge through reverse base current. Otherwise it will take long time to switch. In this circuit there is no mechanism so another modification is required
- 32. TTL Circuits – First Modification Output 𝟏𝟎 𝑴𝒉𝒛 𝟏 𝑴𝑯𝒛
- 33. TTL Circuits – Second Modification Output 𝟏𝟎 𝑴𝑯𝒛 𝟏 𝑴𝑯𝒛 Introduction to alternate path for reverse base current When input A and B (Low), 𝐷3 will be R.B and base current from Q1 will move towards 𝑉𝐵𝐵 = −5𝑉. Providing faster discharge Problem: 1. This system require two supply 𝑉𝐶𝐶 and −𝑉𝐵𝐵. Which is not a good design choice 2. Under switch on condition 𝐷3 is F.B and current is divided towards 𝑅𝐵 leading to reduction in 𝐼𝐵. Here we have taken high 100𝐾Ω to observe the relation.
- 34. TTL Circuits – Achieving TTL TTL is derived from DTL Part from DTL circuit
- 35. TTL Circuits – Achieving TTL Then equivalent circuit with multi-emitter circuit is
- 36. TTL Circuits – Achieving TTL 𝑨 𝑩 𝒀 0 0 1 0 1 1 1 0 1 1 1 0 Implemented a NAND gate with BJT only
- 37. TTL Circuits – Achieving TTL Working: 1. For U1 and U2 (Low 0.2 V) EBJ of Q1,Q2 is F.B and 𝑉𝐶𝐸 is high 2. Then potential at point A is 0.2𝑉 + 0.7 𝑉 = 0.9 𝑉 A 3. For 𝑉𝐶𝐶 = 5𝑉 and 𝑅 = 1 𝐾, 𝐼𝐵 = 4.1 𝑚𝐴 for 𝑄1 and 𝑄2 4. There will be no collector current as it has to be extracted from base of 𝑄3 5. Thus high 𝐼𝐵 and low 𝐼𝐶 indicated 𝑄1 and 𝑄2 are in saturated state. 6. The, the 0.9 V is distributed between CBJ of Q1,Q2 and EBJ of Q3 (0.45 each). So Q3 is in cut-off mode. 𝒀 = 𝑯𝒊𝒈𝒉
- 38. TTL Circuits – Achieving TTL Working: 1. For U1 and U2 (high) EBJ of Q1,Q2 is R.B and operate in reverse active mode (as Q1,Q2 are in saturation mode) 2. Then potential at point A is increased to 0.7𝑉 + 0.7 𝑉 = 1.4 𝑉 from CBJ of Q1, Q2 and EBJ of Q3 A 3. For 𝑉𝐶𝐶 = 5𝑉 and 𝑅 = 1 𝐾, 𝐼𝐵 = 3.6 𝑚𝐴 for 𝑄1 and 𝑄2 4. For multi emitter junction reverse 𝜷 is very small in terms of 0.02, then 𝐼𝐶 = 𝐼𝐵 ∗ 0.02 = 72 𝜇𝐴 5. So the total current flowing into base of Q3 is ~3.6 mA as 𝐼𝑐 is very small 6. High current makes 𝑄3 saturated and thus 𝒀 = 𝑳𝒐𝒘 Please note: in reverse active region emitter is behaving as collector and collector is behaving as emitter
- 39. TTL Circuits – Achieving TTL Output 𝟏 𝑴𝑯𝒛 0.5 𝑴𝑯𝒛 At highlighted point EBJ of Q1,Q2 id F.B making Q1,Q2 to come out of reverse active region. 𝐼𝑐 of Q1,Q2 will extract reverse base current from Q3. This extraction will support 𝐼𝑐 till there is charge in base region of Q3 After this 𝐼𝑐 of Q1,Q2 will move to zero and 𝑄1, 𝑄2 will move to saturation and Q3 will move to cut-off
- 40. TTL Circuits – Achieving TTL Advantage of TTL The propagation delay compared to DTL is “1/10” due to improved removal of base charge. Problem with this circuit Let say the load derived by the circuit has effective capacitance “C”
- 41. TTL Circuits – Achieving TTL 1. When Q3 is ON there is no charging across C 2. But when Q3 is OFF O/P is high there will be charging of capacitor “C” and time constant for the same is 𝜏 = 𝑅𝑐𝐶 = 0.1 𝜇𝑠 3. Now to reduce the time constant we have to reduce 𝑅𝑐 4. Now this is a problem as 𝑅2 = 𝑅𝑐 is low then high amount of current will flow when Q3 is ON leading to “𝐼2𝑅” losses i.e. power dissipation 5. And for low 𝑅𝑐 it is very difficult to derive Q2 to saturation as it will require large base current which is not a good option.
- 42. TTL Circuits What we want exactly? 1. When 𝑄3 is OFF 𝑅𝑐 to be low 2. When 𝑄3 is ON 𝑅𝑐 to be high Conflicting requirements This requirement is impossible to achieve with Passive components. Thus we require active elements
- 43. Open Collector TTL The collector point of Q4 is brought out of the IC that is why it is called open collector TTL For proper operation of this circuit 𝑅3 resistance has to be introduced externally. This resistance is called pull up resistance For A and B low: Q1 will be on Saturation Mode, there will be no base current to Q2 making it in cut-off mode. This Q4 is also in cut-off: O/P [High] For A and B High: Q1 will be on Reverse Active Mode, there will be huge collector current of Q1 =n base current of Q2 making it in saturation mode. This will allow large emitter current to flow, major of that flows to base of Q4 setting it in saturation mode: O/P [Low]
- 45. TTL Circuits – Totem Pole circuit Also Called Phase Splitter 𝑨 𝑩 𝒀 0 0 1 0 1 1 1 0 1 1 1 0 Implemented using pull-up and pull-down loads
- 46. TTL Circuits – Totem Pole circuit Step 1: • For 𝑈1 and 𝑈2 go low: Q1,Q2 goes to saturation and Q3 go to cut-off state. Then Q5 will also be off as there will be no base current to Q5 • Q4 is on as the base is directly connected to power supply. • The current flow will flow through: 1.4 𝐾Ω → 𝑄4 𝐸𝐵𝐽 𝐹. 𝐵 𝐿𝑜𝑤 𝑟𝑒𝑠𝑖𝑠𝑡𝑎𝑛𝑐𝑒 𝑝𝑎𝑡ℎ → 𝐷1 𝐹. 𝐵 {𝐿𝑜𝑤 𝑟𝑒𝑠𝑖𝑠𝑡𝑎𝑛𝑐𝑒 𝑝𝑎𝑡ℎ} • Resistance seen at O/P is Base Resistance divided by 𝛽 of Q4 𝑅𝑜 = 1.4 𝛽 𝐾Ω → 𝑣𝑒𝑟𝑦 𝑙𝑜𝑤 𝑟𝑒𝑠𝑖𝑠𝑡𝑎𝑛𝑐𝑒
- 47. TTL Circuits – Totem Pole circuit Step 2: • For 𝑈1 and 𝑈2 go High: Q1,Q2 goes to reverse active mode and Q3 turns on due to 𝐼𝑐 current working as base current. A B • Large base current of Q3 will contribute to emitter current out of which major current will be base current for Q5. setting it in saturation region. • As Q5 is in saturation O/P is directly low • Now, potential at point B as Q2 is saturated is (0.75 V {at the base of Q5} + 0.2V = 0.95 V) • Now, 0.95 V is divided across EBJ of Q4 and D1 which is less than 0.7 V. • Thus neither of Q4 and D1 turns On and O/P resistance will turn out to be very large IC7400: Power Dissipation 𝑃𝑑 = 10 𝑚𝑊 Propagation delay 𝑡𝑑 = 10 𝑛𝑠 Fan In: 12 to 14 Fan Out: 10 or more Supply: 5V
- 48. Comparison S.No Parameter Open Collector Totem-Pole 1 Circuit Components on O/P side Pull Up and Pull Down Pull Up only (R3) 2 Wired ANDing Cannot be done Can be done 3 External Pullup Resistor Not required Required 4 Power Dissipation Low due to pull up transistor High due to external pull up only (R3) 5 Speed High operating speed Low operating Speed
- 50. CMOS
- 51. CMOS
- 52. Thank You