Digital Timing and Carrier Synchronization.ppt

Digital Timing and Carrier
Synchronization
Paul Husted
Professor Robert Brodersen

Motivation
• Increased Algorithm Complexity
– Designed to Better Utilize Channel
– Requires Very Accurate Synchronization
• Low Power Requirements
– Preserve Battery Life for Mobile Applications
– Low Power CMOS Digital Design Capability
• Increased Digital Circuitry Reduces Analog
Complexity to Save Power

System Specifications
• Direct Sequence CDMA System
– Data Uses Length 31 MLSR Code
– Up to 31 Users May Transmit Simultaneously
– Chip Rate of 25 MHz
– QPSK Symbols Allow Bit Rate of 1.61 Mbit/s
• System Assumes 15 dB SNR
– Allows 10-5 BER
• Max 100 ns Channel Length Assumed

Pilot Sequence
• Pilot Sequence Transmitted Periodically
– Uses Unmodulated Length 31 MLSR Code
• Interacts with Data Code as Gold Code
– Multiple (10-15) Repetitions of MLSR Code
• Pilot Sequence Allows:
– Carrier Offset Estimation
– Symbol and Chip Timing Determination
– Packet Synchronization

Sigma-Delta A/D
• Oversampled Converter Uses Decimation
Filterting to Provide Output
– 25 Msample/sec (200 Mhz Oversample Rate)
– 10 bits
• Additional Decimation Filters Used
– Provide 8 Evenly Spaced 25 Ms/sec Streams
– Digital Circuitry Chooses “Best” Stream
• Combining Streams Leads to Lower SNR

Synchronization Block Diagram
Sigma-Delta
A / D
Converter
Free-
Running
Baseband
Clock
Pilot
Acquisition
and Coarse
Timing
(Adaptive)
Data
Correlator
Digital
Phase
Locked
Loop
Fine Timing
and Carrier
Offset
Estimation
MUX MUX
8
3
3
3
1
Analog
A/D
Digital

Pilot Detection
• 3 Evenly Spaced Streams Passed Through
Pilot Matched Filter
– Dual Threshold System Detects Pilot
• Pilot Code Correlation Value Must Exceed
high_thresh
• Sum of Pilot Code Correlation Values Between
Peaks Must be Below low_thresh
• Second In-Phase Correlation Value Must Again
Exceed high_thresh
• Variable Thresholds Set Based on Received Signal
Power Estimate

Pilot Detection - cont.
• Adaptive Thresholds Found Empirically
– Many Thanks to Andy!
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55
0
5
10
15
20
25
30
HIGH: SNR=15 dB, c=[0.1601+0.55561i -0.062717+0.047182i -0.0067073+0.021089i ]
AGC factor=0.1, carrier offset=-200 kHz, Threshold multiplier: 1.0938
pilot
data
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2
0
2
4
6
8
10
12
LOW: SNR=15 dB, c=[0.1601+0.55561i -0.062717+0.047182i -0.0067073+0.021089i ]
AGC factor=0.1, carrier offset=-200 kHz, Threshold multiplier: 1.75
pilot
data

Pilot Detection cotd.
• Attempt to Ensure Extremely Low
Probability of False Pilot Detection
– Missed Detection May Lead to Packet Loss
– False Pilot Detection
• May Temporarily Cause Loss of Synchronization
• May Cause Loss of Multiple Packets
• Probabilities of Missed Detection and False
Alarm Depend on Channel Conditions

• MACs Borrowed from Correlator for:
–
–
• Carrier Offset Estimate Determined
– Initially,  [1] =  [1]
– In Steady State, [n] = [n-1] +  [n]
– Accumulator Creates Opposite Rotating Phasor
Fine Timing and Carrier Synch
 
 
μ
μ
L
l
l
L
l
l
μ
UW
l
μ
l
μ
UW
l
μ
l
μ
d
z*
z
T
Ω
d
z*
z
μ
ˆ
1
1
1
1
arg
ˆ
max
arg
ˆ



















64
63
64
1

Length of Pilot Symbol
• The Variance of the Frequency Estimation is
Determined by:
– L = Length of Observation Window
– D = Spacing Between Observed Values




















 2
0
2
0
2
2
2
2
1
2
2
1
]
ˆ
var[
N
E
L
N
E
L
D
D
T
s
s

Frequency Estimation Results
1 2 3 4 5 6 7 8 9 10
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
Standard Deviation of Carrier Offset Measurement ([1 -1 .5] channel)
Number of Correlation Measurements
Standard
Deviation
Theoretical Value
Measured Value
1 2 3 4 5 6 7 8 9 10
0
0.05
0.1
0.15
0.2
0.25
Standard Deviation of Carrier Offset Measurement(no channel)
Number of Correlation Measurements
Standard
Deviation
Theoretical Value
Measured Value
• Measured Values vs. Theory

Digital Phase Locked Loop
• Data-Aided Mode
– Creates Coherent Mode During Pilot
• Decision Directed Mode Runs During Data
X Im( )
Loop
Filter
K1 + z-1
ejq

Digital Phase Locked Loop cotd
• Phase updated as:
– Linear Response When Close to Correct Phase
– Update Has Same Sign as Linear Detector
– Easy to Implement
• Does Not Require Lookup Table of Linear Detector
)
sin( 0
1
1 n
n
n K q
q
q
q 




Digital Phase Locked Loop cotd
• Loop Filter is Built as a 2 Tap FIR
• Phase Transfer Function Becomes:
• FIR Not Restricted to be Monic
– Scaling of Tap Values Can Create Lowpass
Filter with Sharp Cutoff
0
1
2
0
1
)
1
(
)
(
a
z
a
z
a
z
a
z
H






CORDIC Blocks
• Angle Estimator
– Takes Real and Imaginary Components from
Carrier Offset Estimator as Inputs
– 8-stage Recursive in 4 cycles
– Output to a Accumulator to Simulate Rotating
Phasor
• Rotator
– Rotates Chosen Stream by Sum of DPLL Phase
Update and Accumulator Phase Update

Correlator
• Multi-User Detection (MUD) System
– Adapts to Environment
• Multipath Gain Estimates
• Correlation to Other Users
– Significantly Improves Performance
• Non-Adaptive Correlator
– Uses Fixed +/-1 Tap Values
– Easier to Implement
• Implemented on this Test Chip

Conclusion
• Low Power Synchronization Design
– Additional Digital Circuitry Allows for Less
Complex Analog Circuitry
• Free Running Oscillator instead of VCO
• Relaxed Requirements for Analog Components
• Digital Circuitry Uses Less Power than Analog
– MACs Time Multiplexed from MUD
• Packet Style System for Networks
• Compensates for Indoor Channel

Digital Timing and Carrier Synchronization.ppt

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Digital Timing and Carrier Synchronization.ppt