Digital Wave vs. Nodal Analysis for Circuit Simulation: an experimental comparison (Part 2)

1 Piero Belforte Marcel Hendrix Digital Wave vs. Nodal Analysis for Circuit Simulation: an experimental
comparison (Part 2)

Piero Belforte - 2015-12-22
The content of this discussion has been loaded here as post collection:
https://www.researchgate.net/publication/287813903_DWS_VS_SPICE_COMPARISONS_FROM_NGSPICE_USERS_FORUM_DISCUSSION_
SPICE-_DWS_INTEGRATION
It seems that some posted content has disappeared...I don't know the reason why this happened. It can be recoverd at the previous link, but the
related attachments no longer work.
Last edit: Piero Belforte 2015-12-23

marcel hendrix - 2015-12-23
Hi Piero,
There is always the wayback machine
( https://archive.org/web ).
I deleted all my posts that were not
improved or refined in later summaries
or conclusions, or which were not
strongly connected to a discussion of
the usage, quality, or implementation of
NGSPICE's transmission lines.
I do not consider the discussion settled
on the question how SPICE and DWS compare
on general circuits that make use of
transmission lines. There is a post that
outlines how such a comparison can be
done in an objective way. Once this loose
end has tightened, I expect that this
whole thread can be summarized very
concisely in the NGSPICE manual.
-marcel
Hi Marcel,
nice to hear from you.
Yes, this discussion has been only suspended, it is yet
a work in progress. I got other results of comparations
but so far i didn't have the time to post them.
I propose you to open another discussion on this very
interesting topic to summarize the results obtained so far
and to go ahead using the method you proposed.
I'm convinced that the result of this work have then
to be published in a specific paper.
Pier
The content of this discussion merged with the Transmission Line model issue in ngspice has been published here:
https://www.researchgate.net/publication/288668128_Digital_Wave_vs_Nodal_Analysis_for_Circuit_Simulation_an_experimental_comparison
The content of this discussion merged with the Transmission Line model issue in ngspice has been published here:
Here the interactive plots of DWS vs. Spice comparisons:

comparison (Part 2)
https://plot.ly/~piero.belforte/folder/piero.belforte:543
o
https://www.researchgate.net/publication/294893036_MICROSTRIP_PEEC_MODELS_DWSNgspice_SPEEDUP_vs_PEEC_CELL_NUMBER
https://www.researchgate.net/publication/295010055_LTSPICE_INTEGRATION_ERROR_400-CELL_PEEC_MICROSTRIP_MODEL
VIDEO SHOWING A 2400X SPEEDUP OF DWS VS NGSPICE:
https://www.youtube.com/watch?v=U-Rt9PQLic8
https://www.youtube.com/playlist?list=PLoyVchXc6Iro65tkestKgtiKbTYzgx32G
DWS vs ngpsice for PEEC application, presetation video:
https://www.youtube.com/watch?v=FLWehNtgiQg
DWS vs ngpsice for PEEC application, presentation :
https://www.researchgate.net/publication/302898051_Digital_Wave_Formulation_of_Quasi-Static_Partial_Element_Equivalent_Circuit_Method
POWER DIVIDER PEEC MODEL
627X_POWER_DIVIDER_DWS_SPEED_UP_SPI2016.jpg
Article containing DWS/Spice comparisons in multigigabit
applications: https://www.researchgate.net/publication/306508351_Digital_Wave_Simulation_of_Lossy_Lines_for_Multi-Gigabit_Applications
Using attosecond time steps in DWS for nonlinear PEEC models (diode-clamped coplanar stripline)
: https://www.researchgate.net/publication/306018733_PEEC-DWS_DIODE-
CLAMPED_COPLANAR_STRIPLINE_SIMULATION_USING_ATTOSECOND_RANGE_TIME_STEPS
DWS VS NGSPICE SIMULATION PROCESS COMPARISON FOR A PEEC MULTICONDUCTOR TL
MODEL: https://www.researchgate.net/publication/305567149_DWS_VS_NGSPICE_SIMULATION_PROCESS_COMPARISON_FOR_A_PEEC
_MULTICONDUCTOR_TL_MODEL
DIODE-CLAMPED COPLANAR STRIPLINE PEEC MODEL: DWS, NGSPICE, LTSPICE COMPARISON OF INPUT CURRENT
STARTUP: https://www.researchgate.net/publication/305780097_DIODE-
CLAMPED_COPLANAR_STRIPLINE_PEEC_MODEL_DWS_NGSPICE_LTSPICE_COMPARISON_OF_INPUT_CURRENT_STARTUP

comparison (Part 2)
COPLANAR STRIPLINE PEEC MODEL: CLAMP DIODE AT PORT 2, DWS VS NGSPICE
SIMULATIONS https://www.researchgate.net/publication/305723454_COPLANAR_STRIPLINE_PEEC_MODEL_CLAMP_DIODE_AT_PORT_2_
DWS_VS_NGSPICE_SIMULATIONS
Hi Marcel,
I'm just back from my holydays. Yes, the site of ischematics has been shut down against our request, and a legal dispute is going on because I
personally spent about 4 years of work on Spicy SWAN development. For this reason I uploaded the content of simulation reports directly on the
discussion involving DWS.
I'll search to find the netlist you are interest in.
Here the original netlist.
TEST_30CM_ZYTL_SPICE_50.cir
Sorry, I did not understand...does this circuit run on your fixed step version?
Ok. Do you still solve the matrix at each step in this fixed step version?
In case of fixed step you should theoretically avoid to solve the matrix at each step and this could speed up the simulation. The matrix could be
inverted once at the start up.
Why not working on a pure fixed-step ngspice version? This version should be an ideal counterpart of DWS. Nyquist criterion on sampled data
system applies to Spice too.
Four different PEEC models are simulated using both DWS and Spice starting from the same extracted netlist.
Performance in terms of CPU time and required RAM on the same machine are compared at growing size of the extracted netlist and reported in
the table. An impressive speed-up factor of up to 1500X and a lower RAM requirement (up to 20X) have bee observed using DWS instead of
Spice with excellent matching between numerical results. While Spice is practically limited to 10-20 thousand lines netlists of the PEEC model,
DWS can deal with PEEC models of up to half million netlist lines.
https://www.researchgate.net/publication/308508001_PEEC-DWS_VS_PEEC-SPICE_PERFORMANCE_COMPARISON
PEEC-DWS: DWS SIMULATON REPORT OF A DIODE- CLAMPED COPLANAR STRIPLINE COMPLEX PEEC MODEL.
The expanded netlist contains about 400,000 lines. The simulated wave digital network contains: Resistors: 1501 Capacitors: 42396 Inductors:
405750 Independent Sources: 1 Diodes : 1 Series Adaptors: 44328
totaliizing 493977 Elements and 46116 Nodes all mapped as 540093 scatternig elements.
This simulation is impossible using Spice due to circuital complexity.
https://www.researchgate.net/publication/308514546_PEEC-DWS_DWS_SIMULATON_REPORT_OF_A_DIODE-
CLAMPED_COPLANAR_STRIPLINE_COMPLEX_PEEC_MODEL
https://www.researchgate.net/publication/308675690_DWS_450K-LINES_NETLIST_OF_A_COPLANAR_STRIPLINE_PEEC_MODEL
As stated several times in this discussion, MNA an DWN (Digital Wave Network) are fully COMPLEMENTARY approaches to circuit simulation.
There are fields where one approach is superior to the other, and fields where the performance is comparable.
The ultimate tool is the union of the two approaches. Spicy SWAN (Ngspice + DWS under the same schematic entry) is a first example of some
INTEGRATION of SPICE with DWS. Unfortunately, for reasons not dependent on myself, Spicy SWAN servers have been shut down despite
more than 20 thousand users.
This discussion has determined a lot of work of Marcel and I in the effort to better understand the differences and improve the tools.

comparison (Part 2)
These discussions have been also reported here:
with 364 reads so far.
This published content has bee also reported as biblio references inf recent IEEE publications:
https://www.researchgate.net/publication/304457427_Digital_Wave_formulation_of_quasi-static_Partial_Element_Equivalent_Circuit_method
https://www.researchgate.net/publication/306508351_Digital_Wave_Simulation_of_Lossy_Lines_for_Multi-Gigabit_Applications
I think this is a good opportunity to enhance ngspice knowledge in the scientific/academic world too.
My intention is still to contribute to ngspice improvement as demonstrated by the content of this discussion (see the recent Marcel trial with a
fixed step version of ngpsice of few days ago in this discussion).
https://sourceforge.net/p/ngspice/discussion/133842/thread/8f20bc1b/#8d9a/1730/a0ee/aea8/d757/7d02/b552/7a4b
Hi Marcel,
all suggestions to improve our specific knowledge of the tools are welcome, and the huge work done so far to compare them is extremely useful
in my view. For sure the comparison methodology used can be improved as already discussed, but this requires some additional work.
As you know, I collected our posts in a document that was published in our Research Gate accounts with the aim of spreading out the results
obtained so far in the scientific community. The number of reads collected so far demonstrates the success of this initiative.
DWS is something like the hidden side of the moon in the field of circuit simulation despite it has been developed about 30 years ago...
Other interesting side results have been the comparisons of ngspice with different Spice versions including Microcap, LTspice and recently
Pspice.
Piero
PEEC circuits are very challenging for MNA circuit simulators due to their very fast growng sizes vs spatial resolution and dense matrix. Here a "
small" PEEC circuit you could try with your "fixed step" ngspice version.
1PS_10NS_CPS_1_DIODE.cir
Marcel, could you post the options you set to get this elapsed time? My spice sims of this circuit requires hours, not seconds.
I see, I didn't notice the dot after fixedstep. The speedup obtained with this option is exceptional and comparable to DWS. Do you solve the
matrix only once?
What is the time step used? Can you try with 1ps and 200fs without XMU?
o
Despite these issues I think this is an important step toward Spice-DWS integration and should be investigated more.
The values of circuits components are as they come from a PEEC extractor, that calculates them from a 3D description of the physical
configuration. This is a small size example, million elements networks can be dealth with using the PEEC method. Stability is also an important
issue especially when you use the full-wave solution of Maxwell equations that leads to the so called retarded PEEC. In this case the EM
coupling among cells are delayed by the propagation delays.
It would be interesting to know sim times of fixedstep at 1ps (single CPU?), and may the numerical values to compare them to
DWS.


comparison (Part 2)
It would be interesting to know sim times of fixedstep
at 1ps (single CPU?),
This netlist can only run on a single CPU. With a fixed
step of 1ps, using the KLU solver, it took 66 seconds.
To my surprise/delight factoring the matrix takes 49.290s,
meaning that caching the result, possible because of the
fixedstep, potentially can bring the time down to 16
seconds or so.
Total elapsed time: 66.033 seconds.
Total DRAM available = 32702.8 MB.
DRAM currently available = 25011.7 MB.
Total ngspice program size = 40.3 MB.
GENERAL: #callocs = 203, #reallocs = 18359,
MATRICES: #allocs = 1, #resizes = 1,
ADDRESS calculations = 0, ASRC evaluations = 0,
BOHICA passes: 0, CALLOCed memory: 5.5 MB.
Time used by C compiler: 0.000 seconds.
Number of lines in the deck = 18263
Netlist loading time = 0.077 sec.
Netlist parsing time = 0.019 sec.
Nominal temperature = 27
Operating temperature = 27
Total iterations = 26768
Transient iterations = 26768
Circuit Equations = 674
Circuit original non-zeroes = 37288
Circuit fill-in non-zeroes = 23987
Circuit total non-zeroes = 61275
Transient timepoints = 10006
Accepted timepoints = 10006
Rejected timepoints = 0
Total analysis time = 65.863 sec.
Matrix load time = 14.642 sec.
Matrix synchronize time = 0 sec.
Matrix reorder time = 0.005 sec.
Matrix factor time = 49.290 sec.
Matrix solve time = 1.288 sec.
Checking the condition number of the matrix
brings the expected bad news:
MATRIX SUMMARY
Size of matrix = 673 x 673.
Matrix before factorization:
Largest element in matrix = 3.011e+04.
Smallest element in matrix = 1.
Largest pivot element = 3.011e+04.
Smallest pivot element = 1.
Density = 38.11%.
Number of originals = 37299.
Number of fill-ins = 135294.
A condition number of 30,000 means that a small error
(say an 8-bit digital oscilloscope == 1%) on the input of the transmission line translates to 300% error of the
predicted result at the other end. This is not yet counting the round-off error of the simulator, which should be
substantial given the extracted values.
I found a way to optionally post-process the traces so that the trap-ringing artifact is removed. It only works when
XMU=0, and has the side-effect that the time-resolution is halved.
-marcel
Last edit: marcel hendrix 2016-10-03
This sounds very interesting...does the bad condition number depend on both fixed step choice and LU
factorization?
I got much higher sim times, in the order of 360min using the .TRAN of the attached netlist. What could be the reason of this HUGE difference?
(The first waveforms are damped, the second results are better).

comparison (Part 2)
In NGSPICE, TRAP has the XMU extension (which introduces damping to prevent the well-known 'trap ringing' artifact).
Attached with XMU=0.001 (is 10% slower).
-marcel
peec3.png
I understand; what happens if you deactivate this MMU extension to get the correct damping?
See the picture above for XMU=1m (0 is the same).
LTspice has 'modified trap', which is active when neither Trap nor Gear is selected in the .options line. Modified trap is claimed "not to have
ringing", although mathematically that makes no sense. To see its effect, remove the "method=trap" from the .options line.
Marcel, this is the current waveform I get from ngspice with the original .TRAN. The damping is ok and is different with respect
peec3 waveform.
Attached here also the DWS results for the port1 current at 200FS (orange) and 10FS (yellow) TSTEP.
CPS_1_DIODE_DWS_10FS_200FS.jpg
CPS_1_DIODE_NGSPICE.jpg
Zoomed view of DWS results for the current at 10FS and 200FS.
CPS_1_DIODE_DWS_10FS_200FS_9NS-10NS.jpg

comparison (Part 2)
Looks ok to me with respect to amplitude.
(Here XMU = 0, not 1m.)
-marcel
peec4.png
Here waveform resolution (bandwith) seems limited by the number of samples, this could
partially explain the huge speedup with respect the sim carried out with enough time
resolution (tmax=1ps) and the default trap method. Otherwise I'm not understanding why with
tmax=1ps the sim requires about 6 hours to run.
Zoomed view of DWS results for the current at 10FS and 200FS.
CPS_1_DIODE_DWS_10FS_200FS_9NS-10NS.jpg
Even in the second plot the behavior of input current seems too damped. Here the result I got from LTspice.
It seems that with used options Ngspice introduces some additional losses to the circuit.
This doesn't happen with the original settings of the netlist I posted, but the sim times get very high (the same happens with Ltspice).
CPS_1_DIODE_LTSPICE.jpg
"SPICE uses second order integration. Most SPICE implementations follow Berkeley SPICE and provide two forms of second order implicit
integration: Gear and trapezoidal (trap).6 Trap integration is both faster and more accurate than Gear. But trap integration can give rise to a
numerical artifact where the integrated discrete time step solution oscillates time step to time step about the true continuous-time behavior. This
can cause the user to be suspicious of the correctness of the simulator even though each trapezoid contains the correct integrated area.
Trap ringing has been feared to be so unacceptable to analog circuit designers7 that trap integration has been eliminated from one commercial
SPICE implementation, PSpice, leaving the slower and less accurate Gear integration as the only available option.
But Gear integration doesn’t just dampen numerical ringing, it dampens all ringing, even physical ringing, making it possible for a circuit that
malfunctions in real life, due to an oscillation, to simulate as perfectly stable and functional because the instability was damped out of numerical
existence. This has led to disastrous situations where an IC design is simulated in PSpice, laid out, and fabricated only to find that the circuit
doesn’t function due to an instability that PSpice’s Gear integration missed. A mask revision cycle—at considerable expense in time and
treasure—is required to remove the instability to try to achieve initial functionality.
In principle, Gear integration error could be reduced by having the IC designer stipulate a small maximum time step. But this is not a viable
solution because (1) small time steps slow simulation speed to a crawl and (2) there’s no way to ensure that the time step is small enough
anyway.
PSpice’s documentation states that it uses a modified Gear method and does indeed seem better at picking a small enough time step to reduce
the error than the Gear integration implementation in Berkeley SPICE.
But PSpice’s method often fails. It is easy to compose a trivial circuit and see the PSpice numerically integrated result deviate dramatically from
the true solution than can be found by inspection. Consider Figure 2, which shows a parallel tank circuit with a parallel piecewise linear current
source. The current source asserts a spike of current over the first 0.2ms and is zero thereafter. The solution should be that the tank circuit
resonance is excited by the spike of current and thereafter ring at constant amplitude."
from: http://www.linear.com/solutions/5739

comparison (Part 2)
Here a LTSPICE DWS comparison of the input current startup (0-1PS) working at 100AS as TSTEP and TMAX:
https://plot.ly/~piero.belforte/8086.embed
The "TRAP RINGING" effect is well visible in the DWS waveform but decays in the first 100FS. The numerical values are well matched.
Relaxing TMAX at 10PS the sim runs on Ngpsice in 1h56min with a quasi -linear growth of required RAM from 19MB to 120MB at the end of run.
Using Ltspice at TMAX=10PS with ALT. solver, Modified TRAP, all additional R of Inductances disabled (very important to get a good result) the
sim runs in 2h24min with a quasi constant RAM requirement of 156MB.
Attached also the plot of in current from LTspice at TMAX=200FS.
CPS_1_DIODE_LTSPICE_TMAX_10PS.jpg
CPS_1_DIODE_LTSPICE_TMAX_200FS.jpg
Here the comparison between "foreign softwares" results.
See
also: https://www.researchgate.net/publication/305781766_DIODE_CLAMPED_COPLANAR_STRIPLINE_PEEC_MODEL_DWS_VS_LTSPICE_
FREE_OSCILLATION_PATTERNS
CPS1_DIODE_LTS_200FS_VS_DWS_50FS.jpg
LTSPICE (200FS) VS NGSPICE (LATEST MARCEL'S RESULT)
CPS!_DIODE_LTSPICE_200FS_NGSPICE.jpg
Marcel, are these differences due to the bad conditioning of the matrix in the fixedstep version of ngspice?

comparison (Part 2)
Marcel, here a version of the PEEC test circuit with a couple of TLs (100 ohm, 23ps delay) added at the connections of the clamp diode to
Coplanar Stripline output port . You could try it with the fixedstep ngspice.
TL1 10037 0 37 0 Z0=100 TD=23PS
TL2 10031 0 31 0 Z0=100 TD=23PS
DCLAMP 10037 10031 DIODE
1PS_10NS_CPS_1_TL_DIODE.cir
This would kill a true fixedstep algorithm.
Mine is saved by the events: Total elapsed time: 72.140 seconds,
result see below.
-marcel
diode_tl.png
The comparison with Ltspice seems acceptable.
Sim time is of the same order of magnitude of DWS at 200FS (38 sec).
DWS result seems to be different.
CPS1_TL_DIODE_DWS_200FS.jpg
CPS1_TL_DIODE_LTS_1PS_VS_NGspice_FS_1PS.jpg
LTspice 1PS vs DWS 200FS
The progressive phase shift of DWS is due to magnetic coupling model (link TL model). At 50FS the difference is smaller.
CPS1_TL_DIODE_LTS_1PS_VS_DWS_200FS.jpg

comparison (Part 2)
DWS 50FS vs 200FS
CPS1_TL_DIODE_LTS_1PS_VS_DWS_200FS_VS_50FS.jpg
DWS 50FS VS LTSpice 1PS: voltages almost coincident, slight differences in currents.
This difference is smaller comparing LTSPICE 1PS to DWS 10FS. Residual differnces in current waveform could be due to TL model.
CPS1_TL_DIODE_LTS_1PS_VS_DWS_10FS_I.jpg
CPS1_TL_DIODE_LTS_1PS_VS_DWS_50FS.jpg
CPS1_TL_DIODE_LTS_1PS_VS_DWS_50FS_I.jpg
This means that Ngpsice difference can be due to TL model, fixedstep issues or both. Should be tried with normal ngspice at TMAX=1PS to see
the differences and understand where the problem is.
Based on a lot of experiments I think the issue is as follows.
The particular simulation requested here is plotting the response after 10ns of a long lossless transmission line excited with a
10ps rise-time single edged pulse.
Obviously, with such a tiny amount of input energy and the (relatively) very long simulation time, the integration method used
by the simulator should be lossless and absolutely stable. AFAIK, this means we only can use the standard SPICE
method=TRAP. Unfortunately, this method is plagued with the so-called 'trap-ringing' effect where the sign of the error
oscillates. The amplitude of the error oscillation is proportional to the step size.
What can be observed for this particular TL circuit is therefore that with method=gear a large stepsize and a short simulation
time are possible. However, after 10 ns the damping of Gear has eaten all the energy of the 10ps edge and all features have
been smoothed away (as would probably happen in practice for a TL that has realistic, non-zero, losses).
When using TRAP with a large step size the simulation is also very quick, but now the response is superimposed with a
triangular ringing signal. When using a fixedstep TRAP (as I did) the amplitude of this triangular error signal is constant - this is
because the signal on the TL is (approximately) a stable repetitive pattern.
When using TRAP, to make the amplitude of the ringing invisible, the (fixed) step should be 100fs or less. This is a large price
to pay just to get rid of a simple visual distraction.
For our special case there is another solution: keep the step size constant at 1ps and average the output over two samples.
This will remove the ringing (only for this special case). In NGSPICE this can be very easily
done with the following script:

comparison (Part 2)
.save V(37,31) I(VIN1) id
.TRAN 1ps 10ns 0 1ps uic
.options method=trap maxord=2 XMU=0 klu fixedstep
.control
run
let i1=i(vin1)[1,10014]
let i2=i(vin1)[0,10013]
let id=i1
let id=0.5*(i1+i2)
set filetype=ascii
write diode.raw
rusage all
quit
.endc
Instead of I(vin1), look at the average id instead.
-marcel
diode_tl_trap_noring.png
Marcel,
these are very interesting and important considerations.I fully agree with your considerations about the effect of losses introduced by the
integration method. I want to remind that the trap method maps the reactive elements (L and C) into IDEAL TLs. DWS converts the PEEC model
in a network containing only adaptors and unit delay TLs. The contribution of resistive elements is negiglible in this case because only the DC
resistance is taken into account (quasi-static model).
I can also say that at 200FS tstep the voltage response is not affected by TRAP ringing and the sim time is yet in the order of ten of seconds
(DWS). Only the input current can be affected by trap ringing but only in the first ten picoseconds of the response.
Working with Tsteps higher than 500FS this model (TRAP + LINK) gets instable using DWS.
Only the input current can be affected by trap ringing but only
in the first ten picoseconds of the response.
This is an indication that the numerical damping of the DWS integration method is not zero. I see the same effect when I set
TRAP's XMU in the region of 1e-4 .. 1e-3.
The contribution of resistive elements is negiglible in this case
because only the DC resistance is taken into account (quasi-static model).
The DC resistances and the diode are the only lossy components the circuit has. The transients have to die down because of
this. It should be possible to estimate how long that will take.
-marcel
The numerical damping of DWS is virtually zero. The only cause of damping is the GMIN GMAX limit of resistance values.
The damping of the TL model is exactly ZERO. In the wave domain the TL model is simply implemented by two delays on the progessive and
regressive wave respectively. A delay applied to a numerical value obviously doesn't cause any damping at all. The same applies to STUB and
LINK models of L and C (the first is exactly equivalent to the TRAP method applied to v,i vaiables) that are modeled as UNIT DELAY TLs.
The model has 300 resistors in it.
Are you saying DWS neglects them?
-marcel
Absolutely no. I'm only saying that their value is very low (maximum is about 55 milliohms) because they are calculated as DC
values of PEEC cell resistance (quasi-satic model), so that their contribution to oscillation decay is relatively low, and it is not
perceivable in the first tens of nanoseconds. By setting these resistors to 0, and may be opening the diode you could check
what is the fixedstep-ngspice behavior for relativey long times (in the us region). For DWS this decay is absent due to the
intrinsic lossless nature of the simulator (except at the GMIN,GMAX terminations).

comparison (Part 2)
Here an example of numerical damping evaluation of a TL approximated by a chain of LC cells:
https://www.researchgate.net/publication/272818374_VI_TRAJECTORY_PLOTS_FOR_TRASMISSION_LINE_MODELS_EVALUATION
Marcel,
you could also utilize the simple test circuits of the previous RG publication to check the losses of your fs-ngspice prototype. In these examples,
the decay due to GMIN, GMAX terminations is checked after million back and forth reflections of TL models (ideal, LC ladder). The decay, due to
nonideal termination only, is so low that it is not visible in the FOPs (V,I Free Oscillation Patterns).even after million oscillations.
This is what I get from DWS after 1usec on a 1ns window. This means about 12K oscillations of input current. The damping with repect the
startup is only due to PEEC cells resistance, diode resistance and Gmax at input port.
This kind of simulations are practically impossible with standard Spice because they wiil require hundred of hours to run.
CPS1_TL_DIODE_DWS_200FS_AFTER_1US_I.jpg
CPS1_TL_DIODE_DWS_200FS_AFTER_1US_V.jpg
Without the diode, after 1 usec, voltage oscillations damping is about 50% due to PEEC cell reistances. DWS simulations ran with a
TSTEP=200FS.
It can also be pointed out that the high-frequency (in the multi-gigahertz range) components are still present after 1us. This is a feature that
differentiates the effect of resistive DC losses from integration method (non TRAP) losses.
The presence of high frequency components after 1 usec also indirecectly demonstrates that DWS doesn't add any loss effect.
Obviously this is the result of a theoretical quasi-static PEEC model where high frequency losses (skin and dielectric) are neglected. These
losses, if added, will dampen the response
more quickly and the high-frequency components will also quicky disappear after a number of back and forth reflections.
Trap ringing is still not present in these simulations.
Thsi circuit could be simulated also with FS-Ngpice for damping comparison
CPS1_TL_DWS_200FS_AFTER_1US.jpg

comparison (Part 2)
CPS1_TL_DWS_200FS_STARTUP.jpg
See also:
https://www.researchgate.net/publication/308938019_COPLANAR_STRIPLINE_PEEC_MODEL_FREE_OSCILLATION_PATTERNS_EVOLUTI
ON_AFTER_1US
The outer shape of FOP after 1us is still rectangular, and looks very different with respect the shape of nontrapeziodal integration method and/or
high frequency losses (skin effect, dielectic etc.)
https://www.researchgate.net/publication/309096937_COPLANAR_STRIPLINE_PEEC-BTM_DWS_SIMULATIONS_OF_TIME-DOMAIN_S-
PARAMETERS
Here a simple test circuit I prepared to evaluate oscillations decay for a DIODE CLAMPLED TL circuit. A simple ideal TL models the coplanar
differential stripline of previous PEEC circuits. The dide is connected at its out port via a short ideal TL as in the previous cases.
TL_DIODE.cir
I ran the sim using LTspice, DWS and Ngspice. Here the plots of voltage at node 2000 after 100 usec from the startup. While Ltspice and DWS
with TMAX=1PS=DWS TSTEP arestill in relatively good agreement (about 100 mVpp max), Ngspice result looks very different showing very
damped oscillations (about 10mVpp max) at a lower feequency.
Ngspice runs in about 56min while DWS requires 30sec (112X speedup).
TL_DIODE_100US_LTSPICE_VS_DWS (2).jpg
TL_DIODE_NGSPICE_100US.jpg
Exploiting the speed of DWS it is possible to investigate after milleseconds after the startup still working at 1PS TSTEP.
After 2 milliseconds the damped oscillations are still present.
This very slow decay is due to diode resistance.
Following attached results in terms of Free Oscillation Patterns are obtained setting GMAX=1E10 in the DWS options in order to keep negligible
energy losses at the generator.

comparison (Part 2)
2-screenshot.15-10-2016 09.13.49.jpg
5-screenshot.15-10-2016 09.38.59.jpg
Test circuit TL_DIODE points out the "lossy" nature of Ngspice TL model. This effect is well visible after a suitable number of free oscillations.
A basic one-TL test circuit can point out the edge aberrations. These aberrations are strongly dependent on maximum integration step (TMAX)
chosen, as shown in the attached figure.
TL model losses and Edge aberrations are uncorrelated. LTspice TL model shows edge aberrations but it is not affected by losses using the
TRAP method. Ngspice TL model is affected by both issues.
TL_FO_NGSPICE_VS_DWS.jpg
Similar edge aberrations are visible using LTspice. They depend on integration method (trap or modified trap) and on TMAX choice. Attached the
comparisons at TMAX=1PS.
Despite this behavior LTspice TL model seems less "lossy" than the corresponding Ngspice model (see TL_DIODE comparisons).
Running the TL_FO circuit in the microdecond time range the edge aberrations seem constant in LTspice.
TL_FO_DWS_LTSPICE_1PS.jpg
It's much easier than that.
A diode with model line
.MODEL DIODE D CJO=1PF TT=100PS
is not lossless, neither in NGSPICE, nor in
LTspice -- it has about 8 Ohms at 100mA.
As the diode rectifies, there will be a current
harmonic at the input frequency and thus losses.
I didn't investigate how well NGSPICE tries to
model more esoteric HF losses. For LTspice we
will never know how accurate it intends to be
here (as there is no source code available).
-marcel

comparison (Part 2)
diode.png
In the circuit TL_DIODE the diode contribution to losses becomes very low when the voltage approaches 500mV.
Oscillation decay is very slow, after 2 milliseconds the oscillations are still present. (see previous post). GMAX
should be set to 1E9-1E10 to reduce the losses due to generator's resistance.
Ngspice simulation is affected by a significant extra loss due to TL model (see the result at 100 usec) not present
using LTspice or DWS.

https://www.researchgate.net/publication/309212658_LTSPICE_TRANSMISSION_LINE_MODEL_EDGE_ABERRATIONS
Trying to run this simple test circuit using ngspice, The sim practiclly stops at 27% after more than one hour with a grwing RAM consumption of
about 400MB.
LTspice runs without apparent issues.
At TMAX=1PS Ngspice is able to finish the simulation, but requires about 194 MB of RAM and the result is affected by overshoots.
Ltspice TL model seems to be definetily better tha the ngspice counterpart.
2TL_FO.cir
2TL_FO_Ngspice_100FS_PROCESS.jpg
For the current dev. TRAP method, see attachment.
With TMAX=0.1ps it takes 40s to run.
Indeed, with the current NGSPICE-26 the simulation
practically slows down to nothing after about 56ns.
This seems to be related to TMAX=0.1p -- with TMAX=1p
there is no problem (163s, result about the same as
my dev version at 0.1ps).
-marcel
2TL_FO.png
This simple test circuit containing 5 TLs is able to point out the issues of Ngpsice TL model.
After 100usec DWS at 1PS., LTSPICE and Ngspice at TMAX=1PS are compared on a 1ns window.
GMAX has. been set to 1E10 to minimize the effect of voltage generator resistance.
DWS results are virtually exact because 1PS is an integer submultiple of all TL delays
.
Attached the plots for comparison.

comparison (Part 2)
While the differences between DWS and LTSPICE (LTSPICE error) are small and due to edge aberrations of LTSPICE, Ngspice response is
affected by a significant smoothig due to model losses.
DWS is about 60X faster than Ngpice (21 sec vs 23min 20sec), about the same speedup with respect LTSPICE.
Here the related interactive plots to see the details:
DWS_LTSPICE_GMAX_5_FIVE_TL_FO.jpg
DWS_LTSPICE_GMAX_5_FIVE_TL_FOP (2).jpg
DWS_LTSPICE_GMAX_5_FIVE_TL_FOPS.jpg
GMAX_5_FIVE_TL_FO.cir
Ngspice_GMAX_5_FIVE_TL_FOPS.jpg
The simple lossless transmission line (Tx) shouldn't be used with an unsuitable TMAX, as you did here. The results start to
become reasonable with TMAX <= 0.1ps.
However, in this case one should probably use the TXL type of line:
YXXXXXXX N1 0 N2 0 mname <LEN=LENGTH >
With Y models the circuit is calculated in 238 seconds, and the output resembles your pictures.
-marcel
BTW: NGSPICE does not know GMAX; you probably meant GMIN.
GMAX_5_FIVE_TL_FO.cir
GMAX_5_FIVE_TL_FO.png

comparison (Part 2)
Other versions of Spice (LTspice and MC11) perform better than Ngspice as shown in the examples.MC11 is the
best.
I don't understand why Ngspice basic TL model can't be improved to be comparable at least to LTspice level .
Otherwise this is still a serious drawback of Ngspice.
GMAX is an option of DWS.
NGSPICE supports the following transmission lines.
Although some are called "Lossy", their parameters can be set such that they have no losses. The
original 3F5 model is TXXXXXX -- all other models are more efficient.
Lossless Transmission Lines; General form:
TXXXXXXX N1 N2 N3 N4 Z0= VALUE <TD=VALUE>
Lossy Transmission Lines; General form:
OXXXXXXX n1 n2 n3 n4 mname
* where the following modelnames mna are valid:
.model mname LTRA ()
.model mname TRA ()
Uniform Distributed RC Lines; General form ('):
UXXXXXXX n1 n2 n3 mname l= len <n=lumps>
.model mname URC ()
KSPICE Lossy Transmission Line; General form:
YXXXXXXX N1 0 N2 0 mname <LEN=LENGTH>
.model mname TXL () $ Single Lossy Transmission Line
.model mname CPL () $ Coupled Multiconductor Line
Although none of these models is able to beat DWS on its own turf,
I don't think any available SPICE supports this many transmission line variants.
(') I'm not sure of this format.
Piero Belforte - 6 days ago
Yes, we discussed some applications of the other TL models in the previos discussion related
to TL model of Ngspice.
The basic TL model is very important because it is at the same level of basic circuit elements
like R,L and C. The steady increasing speed of electronics is requiring more and more models
taking into account propagation effects. This is one of the reason why the basic lossless TL
element is so important for modeling purposes (TLM: Transmission Line Modeling).
DWS was created having TLs and propagation delays as main features and reaches its
maximum efficiency dealing with TLs. On the other hand, even if at different simulation speed,
it is very important to have an accurate basic TL element in Spice.
This is possible, because at least a Spice version (Microcap) has an accurate TL element.
Here the same test circuit adding the simulated result of Microcap11 using a fixed step of 1PS.
Even MC11 seems affected by a small error, even if it should be not affected by edge aberrations.
Here the related interacive plot:
MC11 elapsed time is about 38 min with 51.4 MB RAM requirement.
FIVE_TL_FO_100US_DWS_LTS_MC11_CMP (2).jpg
FIVE_TL_FO_100US_DWS_LTS_MC11_CMP.jpg

comparison (Part 2)
In this interactive plot the differences among DWS, NGSPICE, LTSPICE and MICROCAP11 are shown in details. MC11 (fixed step) and DWS
are almost coicident. Also the calculated samples are visible, so that it is possible to see what Ngpsice does at the edges.
9_GMAX_ONE_TL_FO.cir
ONE_TL_FO_DWS_NGS_LTS_MC11.jpg
ONE_TL_FO_DWS_NGS_LTS_MC11_DETAIL.jpg
Tour Eiffel variations (another way to look at TL model aberrations):
https://www.researchgate.net/publication/309374736_SPICE_TRANSMISSION-
LINE_MODEL_ABERRATION_IMPACT_ON_3D_FREE_OSCILLATION_PATTERNS_FOPs
Last edit: Piero Belforte 6 days ago
9_GMAX_ONE_TL_FO.cir
9_GMAX_ONE_TL_FO.txt
ONE_TL_RS_3D_FOPS_IMPACT.jpg
DWS vs SPICE interactive plots available here:
https://plot.ly/~piero.belforte/543
Just published: http://ieeexplore.ieee.org/document/7676326/
The partial element equivalent circuit (PEEC) method is a well-established technique for obtaining a circuit equivalent of an electromagnetic
problem. The time domain solution of such models is usually performed using nodal voltages and branch currents, or sometimes charge and
currents. The present paper describes a possible alternative approach, which can be obtained expressing and solving the problem in the waves
domain. The digital wave theory is used to find an equivalent representation of the PEEC circuit in the wave domain. Through a pertinent
continuous to discrete time transformation, the constitutive relations for partial inductances, capacitances, and resistances are translated in an
explicit form. The combination of such equations with Kirchhoff laws allows to achieve a semiexplicit resolution scheme. Three different physical
configurations are analyzed and their extracted digital wave PEEC models are simulated at growing sizes using the general-purpose digital wave
simulator. The results are compared to those obtained by using standard SPICE simulators in both linear and nonlinear cases. When the size of
the model is manageable by SPICE, an excellent accuracy and a speed-up factor of up to three orders of magnitude are observed with much
lower memory requirements. A comparative analysis of results including the effect of parameters like the simulation time step choice is also
presented.
Published in: IEEE Transactions on Electromagnetic Compatibility ( Volume: PP, Issue: 99 )
Page(s): 1 - 10
Date of Publication: 25 October 2016
ISSN Information:
DOI: 10.1109/TEMC.2016.2615426
Publisher: IEEE
Sponsored by: IEEE Electromagnetic Compatibility Society

comparison (Part 2)
Last edit: Piero Belforte 7 minutes ago
marcel hendrix - 3 days ago
Hi Piero,
Thanks for the reference; I read this paper with interest.
The first part is very good. Apparently there will be a computation error related to the timestep T. As there is no explicit formula
given, it is unclear how to make a good choice here.
In Section VI ('Simple Examples and Discussion') I can't follow any more: too many new concepts are introduced but never
properly explained. The first one is how the PEEC network needs to be solved: "At this stage, we can start the computation
going back and forth from the borders to the middle of the circuit and vice versa." That is not much to go on :-)
Section VI solves the problem of the "golden reference" by showing in Fig.7 a simple 3rd order network and its equivalent
DWN in Fig.8. Unfortunately, the example stops without giving any practical values or showing results. Doing Fig.7 with SPICE
and Fig. 8 with DWS, then comparing the results, would have directly showed the inaccuracies (if any) PEEC has.
Instead, the paper goes on with translating spatially distributed circuits (i.e. the three-port microstrip power-divider) into
equivalent DWNs. How to go about spatial discretization (in 3D) is hardly talked about (if at all) in the main text?
The examples compare SPICE simulators with DWS. It is not explained that DWS is a commercial closed-source program (is it
not)? Anyway, although PSPICE and LTspice are mentioned, no results for these simulators are given, only the open source
NGSPICE is quantified (in a way that a commercial vendor probably would take issues with).
The main text makes clear that to simulate the DWN, the SPICE tool must use a fixed time step. Unfortunately, NGSPICE,
PSPICE and LTspice can/will not do this. The reviewers must have caught that this invalidates any accuracy comparisons, and
of course it is useless to talk about simulation time differences when the outcomes are (possibly) wrong.
The discussion of the results is rather strange because it mentions problems with LTspice for computations that are not
present in the text (only the NGSPICE results are there).
The paper could have been improved by doing measurements on the real stripline circuits and compare these with the
DWS/SPICE results directly.
-marcel
Hi Marcel,
thank you for your comments to the paper.
This paper was only intended to be a first step to show how DWS works to solve a network generated by the PEEC method and what are the
main advantages with respect the more conventional use of MNA techniques (Spice). It was not intended to show how PEEC models are
performing with respect actual measurements or other electromagnetic simulation tools. A lot of papers cover already this topic.
You can find some of them among the articles written by prof. Giulio Antonini ( coauthor of the present paper)
here: http://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=%22Authors%22:.QT.Giulio%20Antonini.QT.&newsearch=true
Dear Piero,
Thanks for the reference.
I understand now that the PEEC method is already well-established for use with SPICE-like simulators. The aim of the paper is
apparently to show a less well-known alternative called Digital Wave Simulation. It is unclear from the paper if DWS is a
method that has been completely described somewhere, or if it is the name of a commercial closed-source software package.
If the latter, a more rigorous comparison with SPICE (or whatever used to solve PEEC) should have been made than the
authors do now.
Are there any Journal papers about the details of the DWS method? (I found "A combined wave digital/full-wave
electromagnetic approach used for response calculation in equivalent networks of microwave circuits", B. Stošić; N. Dončov; J.
Russer; B. Milovanović, Electromagnetics in Advanced Applications (ICEAA), 2013 International Conference on, Year: 2013,
Pages: 569 - 572, DOI: 10.1109/ICEAA.2013.6632304, but it shows quite big errors for the approximation).
If the focus of the paper was on DWS, the solver method should have been properly discussed.
-marcel
Dear Marcel,
Here a reference to DWS story (may be some old links aren't working anymore):
https://www.researchgate.net/publication/273573985_DWS_STORY_2013
Being a commercial product in the '90s (its name was SPRINT at that time, its price was about 20K$) the internal
algorithms were never disclosed in detail. In this paper there is a fist description on how it works when dealing with
PEEC models. The specific application to PEEC models was made in HDT about 18 years ago:
https://www.researchgate.net/publication/294581073_Alessandro_ARNULFO_and_Alberto_BERGESIO_working_o
n_3Dpeec_at_HDT_Turin_1999
The aim of the paper is to present DWS methds to the academic community.The limitation of number of pages of an
IEEE article limited the possibilty of deeper discussions.
The Stosic paper is not specifically related to DWS but is an example of application of Digital Wave methods to
Microwave circuit simulation. DWS, being a general purpose simulation tool, is obviously capable to do the same
things presented in this paper without the need of specific implementations.
About numerical comparison with Spice, hundreds or even thousands comparative tests have been carried out during the last 30 years and some
of them are shown in this discussion. The fact that Spice normally uses a variable step (but not always, depends on the actual version) doesn't

comparison (Part 2)
preclude numercal comparisons. At comparable accuracy levels the speedups are those shown in the tables.
It is also necessary to point out that the DWS implementation presented is only one of several possible alternatives.
https://www.researchgate.net/publication/301197549_PEEC-DWS_MODEL_IMPLEMENTATION_TABLE
It refers to a QUASI-STATIC model because a FULL WAVE model would require delayed couplings and this is a very difficult task for standard
Spice versions unless custom modifications to the code are introduced. Conductor and dielectric losses should also added to improve the
bandwidth of the PEEC model.
The main issues about PEEC methods are the growth rate of the resulting electrical network size vs the number of peec cells and numerical
stability of the model with particular reference to delayed couplings (retarded PEEC needed for the full wave implementations.
marcel hendrix - 2 days ago 2016-10-28
The fact that Spice normally uses a variable step (but not
always, depends on the actual version) doesn't preclude
numercal comparisons.
The DWS uses a discretization based on assumed TRAP integration and a fixed, known, simulation step. It is not obvious to
me that the equivalent circuit that comes out of this discretization can be run on a SPICE by setting .OPTION method=trap and
limiting the maximum step size. The paper should have elaborated on this.
depends on the actual version
The paper only compares with NGSPICE, which definitely does not use a fixed step. If e.g. MC11 can be trusted, it should
have been used here.
-marcel
If you set on Spice the method to TRAP, the result is virtually the same of DWS (mathematics is not an opinion).
This for sure applies to Spice versions supporting fixed step. In case of variable step a possibilty to get well
matched results is by setting TAMX equal to DWS step.
An example of comparison to a fixed step version of Spice (MC11) is given in this paper recently published (August
2016 ) by IEEE:
http://ieeexplore.ieee.org/document/7543950/
The present discussion, as well as the previous one started in 2015, shows several numerical examples of Spice vs
DWS comparisons. The results are also published as interactive plots here:
https://plot.ly/~piero.belforte/543/
while those related to PEEC-DWS are shown here:
https://plot.ly/~piero.belforte/7091
"The paper only compares with NGSPICE, which definitely does not use a fixed step. If e.g. MC11 can be trusted, it
should have been used here."
Yes. This was done in my article on Lossy Lines for Multigigabit applications (see next post) with excellent results
(accuracy in the order of 1E-6) verified in case of ZY-TL networks. This confirms (if necessary) the perfect
mathematical equivalence between DW and MNA provided that the same integration methd is used and a good
model of TL is available on Spice ,as happen for the version 11 of Microcap, while the previous one had some
issues.
Now I'm use the free version of Microcap11 (the full version is not free), so I'm limited to 50 elements. This is the
reason why we don't use MC11 in the case of PEEC models.
Last edit: Piero Belforte 21 hours ago
"In Section VI ('Simple Examples and Discussion') I can't follow any more: too many new concepts are introduced but never properly explained.
The first one is how the PEEC network needs to be solved: "At this stage, we can start the computation going back and forth from the borders to
the middle of the circuit and vice versa." That is not much to go on :-)"
This is the algorithm implemented about 30 years ago in DWS. This algorithm solves the delay.frre loop (DFL) problem of DWN by choosing a
proper port impedance to open the loops. If some loop can't be solved in this way the rest of the network is solved in a traditional way by means a
matrix solver limited to the this remaining network. This wiil became a root of wave calculations.
So DWS is able to separate big netlists into smaller ones of specific classes, solve them separately, and then combine the
results again? I certainly would want to read much more on that :-)
-marcel
"So DWS is able to separate big netlists into smaller ones of specific classes, solve them separately, and then
combine the results again? I certainly would want to read much more on that :-)"
The DWN extracted from the netlist is processed as a DSP. Parallel processing is also well allowed to gain further
speed advantage (not implemented in the present version of DWS because of its already high sim speed). The
order of calculations is decided by our wave calculation scheduler algorithm (1985) that is the core of DWS.
Eventually remaining roots are dealth with individually as scattering "super-elements" by a standard matrix solver,
(not a whole matrix but eventually a number of small ones. Matrix inversion is only required once at the sim setup.
RAM requirement are reduced with respect SPICE for the same reason. An order of magnitude reduction of RAM
requirement is typical for medium-large RCL-TL networks (up to 10-20K nerlist size).
When propagation effects are involved, as usually happens for SI and PI problems and in general for fast
electronics, the processing is fully explicit, very fast,even at very small time steps, and stable.

comparison (Part 2)
"Section VI solves the problem of the "golden reference" by showing in Fig.7 a simple 3rd order network and its equivalent DW N in Fig.8.
Unfortunately, the example stops without giving any practical values or showing results. Doing Fig.7 with SPICE and Fig. 8 with DWS, then
comparing the results, would have directly showed the inaccuracies (if any) PEEC has."
In fig 7 is shown a simple example to explain the DWN equivalent of RLC circuit. The purpose was not to have a golden reference. Tests with
golden reference and with Spice are already shown in this discussion and in the previous one.
"Instead, the paper goes on with translating spatially distributed circuits (i.e. the three-port microstrip power-divider) into equivalent DWNs. How
to go about spatial discretization (in 3D) is hardly talked about (if at all) in the main text?"
PEEC accuracy (bandwidth) vs spatial discretization is a topic covered by several papers on PEEC method and is not a topic dealth with in this
paper. Obviously the use of lumped circuits to model propagation can become very cumbersome. TLM modeling is much more efficient, but
requires efficient and accurate TL models as DWS does.
"The examples compare SPICE simulators with DWS. It is not explained that DWS is a commercial closed-source program (is it not)? Anyway,
although PSPICE and LTspice are mentioned, no results for these simulators are given, only the open source NGSPICE is quantified (in a way
that a commercial vendor probably would take issues with)"
The detailed four decades long story of DWS, as well as a great portion of historical documents, are included .in my Research Gate account:
https://www.researchgate.net/profile/Piero_Belforte
DWS (former SPRINT) has been a top-performing sim engine for pre and post-layout pcb SI/PI/EMC verification tool produced by my company
HDT until the year 2001. It was adopted by major companies. After the end of HDT activity due to financial and partrneship issue with Zuken-
Redacs, DWS is no more in the market, except the 2012-2016 parenthesis of Spicy SWAN web app including Ngspice suddenly stopped against
my will on May 2016 with 20,000 free and about 500 paying users.. A legal dispute is open and still going due to the huge damage caused.
Elapsed time comparisons shown in the paper have been carried out using ngspice 2.6, while the plots compare DWS to Pspice results. LTspice
results are similar if default params for inductance are retouched. Unfortunately the original paper wass to long so we had to cut it. An extended
version will soon be avaialble on Research Gate.
"The main text makes clear that to simulate the DWN, the SPICE tool must use a fixed time step. "
Obviously SPICE can't simulate the DWN. To get top-matched result you can use fixed step if possible as MC11 does, in this case the matching
is within 1E-6 (trap option) but with the usual speedups of DWS.
In any case when you deal with speedups of 2-3 orders of magnitude or network size unmanageable by Spice, as in case of large PEEC or TL
networks,it is no more an issue of accuracy.
I'd like als to remind that trap (stub) and link ( for DWS ) method are the only lossless (pure TL equivalent), the other methods introduce resistive
equivalents and related losses for both MNA and DWN.
Last edit: Piero Belforte 2 days ago
It was clear from day 1 that DWS can perform certain simulations involving large networks much faster than SPICE, so of
course it should be used when you have those.
A transmission line (where it all started here) can be done with a specific comapct model (SPICE) or done the DWS way. The
DWS way results in a very large netlist of very simple elements which therefore simulates slowly in SPICE. My interest in this
is why the SPICE model for a specific transmission line is so much slower. Is the SPICE model not using the best algorithms?
Related to this is the question whether smaller circuits should be run with SPICE or with DWS, or more importantly, if a SPICE
implementation can benefit from the ideas used in DWS.
-marcel
"A transmission line (where it all started here) can be done with a specific compact model (SPICE) or done the DWS way. The DWS way results
in a very large netlist of very simple elements which therefore simulates slowly in SPICE. My interest in this is why the SPICE model for a specific
transmission line is so much slower. Is the SPICE model not using the best algorithms?"
It is not clear whay you mean with "DWS way". DWS way to deal with basic lossless TL is obviously not to use a large netlist but the simple basic
TL model. As already pointed out this is the basic element DWS was built around. It is extremely fast because running it means only to increase
a pointer of a discretized wave buffer. This model is not influenced by the integration method used for L and C (as happens for example using
LTSPICE) and is virtually exact if the simulation step used is an integer submultiple of TL delay. If the chosen step doesn't satisfy this conditions
DWS offers 2 options: rounding or interpolation (for reference see the manual here:
https://www.researchgate.net/publication/272576412_DWS_85_USER_MANUAL).
The reasons of the slow SPICE sim times with large netwoks were already discussed, and you experience them directly by developing a "fixed
step" experimental version of ngpsice.
With time variant and or nonlinear netwoks there are additiona reasons of DWS speedup. For example the pwl nonlinearities are directly
processed by LUT (Look UP Tables) without any need of iterations. In case of Spice-like models like diodes or bjt (the onl implemeented in the
present version of DWS the Newton-Rapson iterations are confined to the single nonlinear element.

comparison (Part 2)
"Related to this is the question whether smaller circuits should be run with SPICE or with DWS, or more importantly, if a SPICE implementation
can benefit from the ideas used in DWS."
We already discussed with Francesco too (see previous discussion) a possible implementation of a combined Spice-DWS simulator. In this case
Spice models should run at a fixed step explointing the possibilties open by very small steps as already done in the DWS juncton diode model.
The first step to improve ngspice (I think this is mandatory) is to improve its basic TL model,
About fixed step you have already developed a "fixed step" version of ngspice and you experienced important speedups with respect the
standard one at least for certain classe of circuits.
marcel hendrix - 19 hours ago
About fixed step you have already developed a "fixed step" version of
ngspice and you experienced important speedups with respect the standard
one at least for certain classe of circuits.
This alternative solver is not really fixedstep, as it allows
events (generated by advanced models and XSPICE) to happen at their
precise moment in time. After (and before) an event the timestep
is momentarily made much shorter. This works only satisfactory when
a mix between TRAP (order=2) and backward EULER (order=1) is used, i.e. when XMU=0.1. It is relatively easy to understand
how this solver influences accuracy of SPICE results, but the algorithm is incompatible with what I understand to be necessary
for the equivalent circuits that are generated by a DWS. This was one of the issues the paper under discussion could have
cleared up.
-marcel
Piero Belforte - 15 hours ago
Yes, I agree, if this is what you implemented, it is not exactly what DWS implements
.
I again point out that DWS implementation is numerically equivalent to MNA working at fixed step using TRAP as
integration method for reactive components (L and C) and an accurate TL model. Obviously the specific
calculations are not the same as DWS does, so some numerical rounding error difference could arise especially
when the number of calculated samples gets very high (1E8-1E9 or so). I suspect that, being Spice calculations
more cumbersome, Spice sims should more affected by rounding errors than DWS.
The comparisons of DWS vs MC11 at fixed step confirm this fact. MC11 seems as as accurate as DWS even if it is
still slower ( 2 orders of magnitude) for the test circuits tried.
Here you can directly see a comparison of numerical results for a ZYTL cell among DWS, MC11 at 1FS and
Ngpsice. Please enlarge the waveforms using the zoom, an also look at the calculated difference between MC11
and DWS by selecting the waveforms (click on the colored line within the label on the right top corner to
select/deselect the waveforms).
An example of what happens after a large number of samples (1E8) for DWS, MC11,LTSPICE is here:
You can try to play zooming in and out, panning, secting etc. in order to have an idea of the numarical differences in
this case.
Piero Belforte - 2 days ago 2016-10-28
To complete the picture of DWS algorithm benefits I'd like to mention here the BTM (Behavioral Time modeling) capability that shows a further 2-
3 order of magnitude speedup with respect the even fast simulation of a circuital implementation. Using the BTM a PEEC TL model like the
coplanar example shown previously can run in a fraction of second:
https://www.researchgate.net/publication/309096937_COPLANAR_STRIPLINE_PEEC-BTM_DWS_SIMULATIONS_OF_TIME-DOMAIN_S-
PARAMETERS
"Frequency domain Vector Fitting (VF) is a well known technique to generate circuital models of a spatially discretized lossy transmission lines
from theoretical formulation of losses. The subpicosecond time steps required by multi-gigahertz bandwidths and short transmission lines
included in the models, determine long Spice simulation times. A 100X speedup can be gained using the Digital Wave Simulator (DWS) instead
of Spice. DWS processes the waves of a Digital Network built up connecting together scattering blocks (circuit elements, nodes and S-parameter
multi-ports) coming from a Spice-like description. Being a DSP wave processor instead of a classical nodal equations solver, DWS is
computationally very fast and numerically stable. Comparisons with commercial simulators like Microcap11 and CST Cable Studio show a good
matching of results. A further 10-100X simulation speedup is obtained if Piecewise-Linear Fitting (PWLF) is used to describe the time-domain
behaviors of Scattering Parameters. Single or multiple cell Behavioral Time Models (BTM) can be extracted by PWLF from TDR/TDT
measurements and processed by DWS fast convolution algorithms. A setup de-embedding can be performed by PWL breakpoints optimization to
fit actual measurements. A RG58 coaxial cable is analyzed and its VF-derived eye-diagrams are compared to PWLF measurement-derived
results. At multi-gigabit rates significant differences, due to cable physical implementation effects, are observed. The modeling/simulation
alternatives (VF/Spice, VF/DWS and PWLF/DWS) are compared together and the advantages of PWLF/ DWS in term of simplicity, stability and
speed are highlighted."
Reference is here: http://ieeexplore.ieee.org/document/7543950/
Its content is also avaible here:
https://www.researchgate.net/publication/306508351_Digital_Wave_Simulation_of_Lossy_Lines_for_Multi-Gigabit_Applications

Digital Wave vs. Nodal Analysis for Circuit Simulation: an experimental comparison (Part 2)

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