![10 1 Introduction to Real-Time Systems
4. Application Design: This part is fundamental to aid designers of real-time system
software. We describe the design procedure from high-level design methods to
low-level design and implementation. We also provide a survey of real-time
programming languages and fault tolerance techniques. This part ends with
a detailed case study in which we show the implementation of the methods
reviewed in a real-life application.
1.8 Review Questions
1. What is the relationship between a real-time system and an embedded system?
Are all embedded systems real time? Discuss by giving examples.
2. What are the main components of a real-time system?
3. What is a sensor and an actuator in a real-time system? Give an example of each.
4. What type of hardware do you expect to be in the input interface of a real-time
computer system?
5. What is hard real-time, soft real-time, and a firm real-time system?
6. Give an example each of event-driven and time-driven real-time system.
7. What are the main characteristics of a distributed real-time system?
1.9 Chapter Notes
We have looked at the main components of a real-time computer system, its basic
architecture, and different classifications of these systems. Real-time systems can
have hard, soft, and firm deadline tasks when tasks are considered. On the other
hand, the processing can be handled as event driven and time driven. A real-time
computer can be embedded in the environment it has to control in an embedded
system and it can be distributed over a real-time network. Generally, a real-time
system has a combination of these properties. General concepts about real-time
systems are described in [2] and real-time programming languages are contained in
[1].
References
1. Burns A, Wellings A (2001) Real time systems and programming languages: Ada 95, Real-time
Java and real-time C/POSIX, 3rd edn. Addison-Wesley
2. Laplante PA, Ovaska SJ (2011) Real-time systems design and analysis: tools for the practitioner,
4th edn. Wiley](https://image.slidesharecdn.com/5244432-250617135305-714262ca/85/Distributed-Realtime-Systems-Theory-And-Practice-1st-Ed-K-Erciyes-30-320.jpg)
![2
The Hardware
2.1 Introduction
Most of the real-time computing systems employ general-purpose hardware com-
ponents such as the processor, memory, and input/output units. An embedded real-
time system may have special input/output interface units dedicated for the appli-
cation. The main difference between a non-real-time system and a real-time system
at hardware-specific software level is the structure of the low-level software such
as handling of the interrupts and time management. In order to fully understand the
operation of this software and operating system interface to it, we need to look at the
hardware characteristics.
In this chapter, we review the hardware of a real-time system node at component
level by deferring the review of the architecture and basic software structure of a dis-
tributed real-time system to the next chapter. We start with the basic interface units:
sensors and actuators and review characteristics of the common types of these com-
ponents. The processor is where the actual processing is performed and single cycle,
multi-cycle, and pipelined datapaths are discussed next. Memory and input/output
units are other main parts of a real-time system as we will see. We will use the MIPS
processor [1] to describe the hardware-related concepts as this processor is widely
used in embedded systems and yet simple enough to display operation.
2.2 Processor Architecture
The Von Neumann model of computation is based on stored program computer
concept where instruction and data are stored in the same memory. This architecture
is the basis of most of the contemporary processors. The processor consists of a
control unit, arithmetic logic unit (ALU), and registers in this model of computing
© Springer Nature Switzerland AG 2019
K. Erciyes, Distributed Real-Time Systems, Computer Communications
and Networks, https://doi.org/10.1007/978-3-030-22570-4_2
11](https://image.slidesharecdn.com/5244432-250617135305-714262ca/85/Distributed-Realtime-Systems-Theory-And-Practice-1st-Ed-K-Erciyes-31-320.jpg)
![14 2 The Hardware
Read reg1
Read reg2
Write reg
Write data
RegWrite
ALU
ALUOp
Instruction .
.
Instruction
Memory
Read
address
[25-21]
[20-16]
[15-11]
[31-0]
Read
data1
data2
Read
Fig.2.3 MIPS datapath for R-type instruction
in binary and hexadecimal notation would be
op rs rt rd shamt func
----- ------ ------ ------ ------ -------
00 0000 0 1110 0 1010 0 0111 0 0000 10 0000
The 32-bit instruction would then be 0 x 01CA:3820 in hexadecimal notation. Let
us take a closer look at how this instruction is executed in the simple datapath of
Fig.2.3.
1. The read address is provided to the instruction memory and the 32-bit instruction
word (01CA:3820) is fetched.
2. The instruction word is at the output of the instruction memory and its 11–25 bits
are fed to the register file to select the read registers and the write register.
3. The contents of the read registers 14 and 10 appear at read data outputs of the
register file and at the inputs of ALU.
4. The add operation is selected in ALU by the ALUOp.
5. The sum of contents of registers 14 and 10 appears at the output of ALU and at
Write data input of the register file.
6. Activating RegWrite signal provides writing of the sum to the contents of
register 7.
The task of the control unit is to provide the control signals ALUOp and RegWrite
by the value present in the opcode field of the instruction word. Providing these
signalsintheabove-describedsequenceisdifficultandnotnecessary.Wecanhavethe
control signals present throughout a whole cycle and if the cycle is long enough, the
produced output will be correctly settled in the single cycle datapath implementation.
Determining the length of the cycle is crucial in this design method and it should be
as long as the longest instruction.](https://image.slidesharecdn.com/5244432-250617135305-714262ca/85/Distributed-Realtime-Systems-Theory-And-Practice-1st-Ed-K-Erciyes-34-320.jpg)
![2.2 Processor Architecture 15
Read reg1
Read reg2
Write reg
Write data
RegWrite
ALU
ALUOp
Instruction
Instruction
Memory
Read
address
[25-21]
[20-16]
[15-11]
[31-0]
Data
Memory
MemWrite
MemRead
.
. 0
1
0
1
Read
address
Write
address
Write
data
Sign
data1
Read
Read
data2
extend
Mux
Mux
0
1
Read
data
.
.
.
.
RegDst
MemToReg
ALUSrc
[15-0]
Fig.2.4 MIPS datapath with data memory
We need to write the generated output to external data memory instead of a
destination register commonly. The I-type of addressing with the format shown in
Fig.2.2 is used for this purpose and MIPS has two instructions to store data to and
remove data from data memory as follows:
lw $2, 12($1)
sw $2, 12($1)
In this example, the load word (lw) instruction loads a 32-bit word from the data
memory location at the address pointed by the contents of register $1+12 into register
$2 and the store word (sw) does the opposite by storing the contents of the register $2
at data memory address $1+12. We will now extend the datapath to include I-type of
instructions as shown in Fig.2.4. There are three additional 2:1 multiplexers to be able
to distinguish the instruction modes. In I-type instruction, the second register field
contains the write address now, so we need to pick bits (20–16) as this value for this
mode by activating RegDest control of the first multiplexer. There is a sign-extend
circuit to extend the 16-bit value in the lower half of the instruction word for addition
of the first register value to the contents of the address contained in the register plus
the offset value. The second multiplexer selects the R-type or I-type operation by
its ALUSrc input. Lastly, the third multiplexer selects whether the contents of the
data memory location (I-type) or the results of the ALU operation (R-type) are to be
written to the register file by the MemToReg control signal or not. Loading from or
writing to data memory is selected by MemWrite or MemRead signals.
Let us list the control signals needed for the lw 2, 12($1) instruction. We only
need to supply the address of the instruction to the instruction memory without the
need for a read signal since all write operations are controlled by the control unit. The
opcode for this instruction which is 100011 is fed to the control unit which outputs
the following signal values:](https://image.slidesharecdn.com/5244432-250617135305-714262ca/85/Distributed-Realtime-Systems-Theory-And-Practice-1st-Ed-K-Erciyes-35-320.jpg)
![2.2 Processor Architecture 17
Read reg1
Read reg2
Write reg
Write data
RegWrite
ALU
ALUOp
Instruction
Instruction
Memory
Readaddress [25-21]
[20-16]
[15-11]
[31-0]
Data
Memory
MemWrite
MemRead
.
. 0
1
0
1
Read
address
Write
address
Write
data
Sign
data1
Read
Read
data2
extend
Mux
Mux
0
1
Read
data
.
.
.
.
RegDst
MemToReg
ALUSrc
0
1
Mux
4
Add
Add
PC
Shift
left 2
.
.
.
PCSrc
[15-0]
Fig.2.5 Final MIPS single cycle datapath
Table 2.1 MIPS control signals for sample instructions
Operation RegDest RegWrite ALUSrc ALUOp MemWrite MemRead MemToReg
add 1 1 0 010 0 0 0
and 1 1 0 000 0 0 0
lw 0 1 1 010 0 1 1
sw X 0 1 010 1 0 X
beq X 0 0 110 0 0 X
with 10 ns cycle time and 100 MHz frequency. However, many MIPS instructions
require less time, for example, R-type instructions do not use data memory and hence
execute in four steps requiring a clock cycle of 8 ns. In reality, accessing external data
memory is much slower and hence the single cycle datapath has poor performance.
2.2.2 Multi-cycle Datapath
Single cycle datapath is not efficient as it uses the same length clock for all instruc-
tions. Our aim in improving the single cycle implementation is to have variable length](https://image.slidesharecdn.com/5244432-250617135305-714262ca/85/Distributed-Realtime-Systems-Theory-And-Practice-1st-Ed-K-Erciyes-37-320.jpg)
![18 2 The Hardware
Table 2.2 MIPS pipelining stages
Stage Abbrev. Description
Instruction fetch IF Instruction is fetched from
memory
Instruction decode ID The opcode in instruction is
decoded
Execute EX Instruction is executed in ALU
Memory MEM Memory for read or write
operation is accessed
Write back WB The read data from memory is
written to register file
Memory
address
[15-11]
PC
.
ALU ALUout
Read reg1
Read reg2
Write reg
Write data
0
1
Sign
data1
Read
Read
data2
extend
4
Shift
left 2
.
2
3
A
B
0
1
Write Data
Register File
0
1
.
[25-21]
[20-16]
0
1
.
.
.
.
Inst/Data .
IR
MDR
0
1
.
.
.
Fig.2.6 MIPS multi-cycle datapath without the control signals
of execution time for each instruction. We will start by dividing the instruction in
MIPS into the stages of Table2.2 which each stage taking one clock cycle.
The instructions now take multiple cycles, branches and jumps take three cycles,
register instructions take four cycles, and only the load word instruction uses all
five steps above. Some components of the datapath need to be reused necessitating
rearrangement of the hardware. Extra registers are needed now to hold intermediate
results between cycles. Instruction and data memory can be merged and we can have
a single ALU that will also handle branch and jump instructions simply because
the processor cannot use these hardware components simultaneously as these are
employed at different cycles. The new multi-cycle datapath without control signals
is depicted in Fig.2.6. The newly introduced registers are the instruction register
(IR), memory data register (MDR), two registers A and B at the output of the register
file, and the ALUout register to hold the value obtained from the ALU to write back
to data memory.](https://image.slidesharecdn.com/5244432-250617135305-714262ca/85/Distributed-Realtime-Systems-Theory-And-Practice-1st-Ed-K-Erciyes-38-320.jpg)
![2.2 Processor Architecture 19
The control unit of a multi-cycle may be realized using a finite state machine
(FSM) which consists of a finite number of states and transitions between the states.
Informally, an FSM receives inputs in a state and based on its current state and the
inputs, it produces output and may change state. We can have each multi-cycle stage
represented by a state of the FSM and the control signals needed in that stage will be
output by the FSM [1]. Although multi-cycle datapath results in a better performance
than the single cycle one, the pipelining described next improves performance better
and is the basis of modern processors.
2.2.3 Pipelining
Pipelining is commonly employed in real life to improve performance. Consider a
washing system that has three machines; a washer (W), a drier (D), and a folder (F).
We will assume a person needs to use these machines in sequence as washer, drier,
and folder. Let us further assume the washer, the drier, and folder take 20min each.
Allocating all of these machines to a person X as shown in Fig.2.7a is not sensible
since the washer, for example, can be used by another person Y at the drying stage
of person X . Pipelining shown in Fig.2.7b allows the unused machines to be used by
the next person and reduces the completion of the laundry process for three persons
W D F
W D F
W D F
W D F
P1
P1
P2
P3
t=100 minutes
t=180 minutes
W D F
P2
W D F
P3
(a)
(b)
Fig. 2.7 Pipelining example. Three machines in a laundrette are used without pipelining in (a) to
result in a total time of 180min. Pipelining reduces the completion time to 100min as shown in (b)](https://image.slidesharecdn.com/5244432-250617135305-714262ca/85/Distributed-Realtime-Systems-Theory-And-Practice-1st-Ed-K-Erciyes-39-320.jpg)
![2.2 Processor Architecture 21
IF ID EX MEM WB
IF ID EX MEM WB
IF ID EX MEM WB
IF ID EX MEM WB
lw $2, 12($8)
sw $4, 16($8)
lw $3, 14($8)
add $5, $9, $12
Fig.2.8 Pipelining in MIPS assembly language program
Instruction
Instruction
Memory
Readaddress
[31-0]
PC
.
Read reg1
Read reg2
Write reg
Write data
RegWrite
[25-21]
[20-16]
.
Sign
data1
Read
Read
data2
extend
.
.
.
0
1
4
Add
PCSrc
.
[15-0]
[20-16]
[15-11]
ALU
ALUOp
0
1
Mux
0
1
RegDst
ALUSrc
Add
Shift
left 2
.
.
Z
R
Registers
Data
Memory
MemWrite
MemRead
0
1
address
Write
data
Read
MemToReg
data
IF/ID ID/EX EX/MEM
MEM/WB
Fig.2.9 Pipelining in MIPS
the first stage. A data value required in a later stage must be forwarded between the
pipeline registers. For example, the write register address is carried all through the
stages since this is needed in the last stage in the case of store word (sw) instruction.
Note that an instruction goes through one stage at each cycle requiring five cycles
for a whole instruction.
Control Signals
Controlsignalsneededfortheinstructionshouldbetransferredalongwiththeinstruc-
tionusingthepipelineregisters.Therearedistinctcontrolsignalsneededateachstage
and once the instruction passes through a stage, control signals needed for that stage
can be abandoned resulting in fewer signals to be propagated as the instruction goes
through the stages as shown in Fig.2.10.](https://image.slidesharecdn.com/5244432-250617135305-714262ca/85/Distributed-Realtime-Systems-Theory-And-Practice-1st-Ed-K-Erciyes-41-320.jpg)
![22 2 The Hardware
Control
Unit
Instruction
Instruction
Memory
Readaddress
[31-0]
PC
.
Read reg1
Read reg2
Write reg
Write data
RegWrite
[25-21]
[20-16]
.
Sign
data1
Read
Read
data2
extend
.
.
.
0
1
4
Add
PCSrc
.
[15-0]
[20-16]
[15-11]
ALU
ALUOp
0
1
Mux
0
1
RegDst
ALUSrc
Add
Shift
left 2
.
.
Z
R
Registers
Data
Memory
MemWrite
MemRead
0
1
address
Write
data
Read
MemToReg
data
IF/ID
ID/EX
EX/MEM
MEM/WB
EX
WB
MEM MEM
WB WB WB
Fig.2.10 Pipelining in MIPS with the control signals
2.2.3.1 Hazards
The pipelined structure of a processor improves efficiency; however, we have
assumed the instructions that are fed to the pipeline stages one after the other are
independent. The instructions that follow each other may be dependent meaning the
value of a register produced is used in one of the following instructions which cause
hazards.
Data Hazards
Consider the following lines of MIPS code:
lw $3, 10($2) First example of a data hazard
and $4, $3, $5
add $3, $1, $2 Second example of a data hazard
|
sw $3, 12($4)
The first instruction load word (lw) loads the value in data location ($2)+10 into
register 3 which is done at the final and fifth write back (WB) stage. The following
instruction however needs the value in register 3 in the third execute (EX) cycle.](https://image.slidesharecdn.com/5244432-250617135305-714262ca/85/Distributed-Realtime-Systems-Theory-And-Practice-1st-Ed-K-Erciyes-42-320.jpg)
![2.2 Processor Architecture 23
This situation is termed data hazard in a pipelined processor. A possible solution
is forwarding the value of $3 which is fetched from memory in the fourth memory
(MEM) stage of the load word instruction to the and instruction that needs this value
in its second instruction decode (ID) stage. This type of forwarding results in handing
over of the register value to two stages back. In order to accomplish correct operation,
we need to stall the processor for one cycle between these two instructions. Stalling
a processor means stopping its operation for one cycle by resetting the values in the
required pipeline registers.
In the second example above, the store word (sw) instruction needs the correct
value of register 3 at the fourth MEM stage, and hence this value can be forwarded
by the add instruction at its second EX stage without stalling the processor. When
and where to forward register values can be handled by a forwarding unit which
is a circuit which compares the destination register (rd) value at the end of the EX
stage (EX/MEM pipeline register) and also at the end of the MEM stage (MEM/WB
pipeline register) with the values of the first (rs) and second (rt) register values at the
end of the ID stage (IF/ID pipeline register). Whenever a match is found the matched
register value is forwarded one or two stages back depending on where the match
is found. The comparisons to be performed at the forwarding unit are as follows. A
detailed description of the forwarding operation in MIPS is given in [1].
• EX/MEM.rd = ID/EX.rs
• EX/MEM.rd = ID/EX.rt
• MEM/WB.rd = ID/EX.rs
• MEM/WB.rd = ID/EX.rt
The MIPS datapath with the forwarding unit is depicted in Fig.2.11. This unit
basically compares the destination register (rd) identifier input to MEM stage with
the input registers of the EX stage (rs and rt), and the destination register (rd)
identifier input to WB stage with the input registers of the EX stage (rs and rt). If a
match is found, the rd value is fetched back one or two stages. This carrying back of
the rd value is accomplished by selecting the 1 (2 stages back) or 2 (1 stage back)
inputs of the multiplexers now present at the input of the ALU.
Control Hazards
The sequence of instructions may divert to another location after the branch (beq)
instruction which compares values in two registers and jumps to the location specified
in the instruction if these values are the same. Instructions are fetched in the first stage
(IF) and the branch decision is made at the third stage (EX). Consider the following
MIPS code segment:
beq $1, $2, 16($6)
and $4, $3, $5
add $7, $8, $9](https://image.slidesharecdn.com/5244432-250617135305-714262ca/85/Distributed-Realtime-Systems-Theory-And-Practice-1st-Ed-K-Erciyes-43-320.jpg)
![PART II.
IN NORWAY.
CHAPTER I.[C]
Fröken Knudsgaard pretended to grumble a good deal at having
to leave Copenhagen and go to Norway with Gerda and Ejnar. But
there was no help for it. It was a time-honoured custom that she
spent the whole summer with her nephew and niece. It was true
that they saw each other constantly all through the year, for Tante
lived opposite the Orstedpark, and the botanists, who lived at
Frederiksberg, passed that way every time they went to the Botanic
Museum and Library, and would never have neglected to run in for a
chat. Sometimes, also, they lunched with her in her cosy little home,
where, in the spring, she saw the limes of the Boulevard unfold their
tender leaves, and where in summer she watched the sun disappear
in the north-west behind the trees. It was indeed a pretty little
home, made, so she said, wickedly comfortable by her Clifford's
kindness.
But these fragments of companionship were not considered
enough by the botanists; and summer was the time when they
claimed Tante for their own, whether she liked it or not. But of
course she liked it; only she felt it to be her duty as a healthy human
being to have a permanent grievance.
Don't talk to me about giving up my grievances, she said. All
right-minded people ought to have them. Rise above them, indeed!
Thank you! I don't want to rise above anything!
However, after the usual formality of grumbling, Tante was
charmed at the prospect of having a change. Ejnar had set his heart
on going to the Gudbrandsdal to find a particular kind of shrub
which grew only in one district of that great valley. He was a gentle](https://image.slidesharecdn.com/5244432-250617135305-714262ca/85/Distributed-Realtime-Systems-Theory-And-Practice-1st-Ed-K-Erciyes-57-320.jpg)
![wine, followed on the next day by some corn-brandy, seemed to
indicate that a delightful acquaintanceship was ripening; and when
Mor Inga took her to the Stabur (the storehouse), that most sacred
precinct of every self-respecting Norwegian Gaard, and showed her
the treasures and mysteries of Norwegian housekeeping, every one
felt that Fröken Knudsgaard had arrived. Even the disagreeable old
magistrate (Sorenskriver)[D] from S——, one of the eight or ten
guests, admitted that.
She has seen the Stabur, he said, with a grim smile, and he
actually forgot to help himself first to cheese, but passed her a few
delicate shavings; a sure sign from him of even passing respect.
After an introduction to the Stabur, any other honour on earth
was easy of attainment; and no one was surprised to learn that
Ragnhild was going to put up her loom and teach the Danish lady to
weave. And Mor Inga fetched great-grandmother's old painted
spinning-wheel from the top room of the Stabur and put it in the
little balcony which overlooked the courtyard; and she brought some
fresh wool from the wool-room—another sacred spot—and sent for
old Kari, who was especially clever at carding the wool. And Tante
sat and knitted, whilst old Kari carded the wool and Mor Inga span.
This was Tante's first introduction to old Kari, eighty years old, and
full of fairy lore.
Ah, whispered Mor Inga to Tante, Kari can tell thee many
stories of the Gudbrandsdal if she likes. But it must be in secret,
when there is no young person near to laugh and disbelieve. One
day thou shalt give her a little coffee in a packet—all for herself—and
then thou wilt hear all sorts of things.
But to-day Kari only carded the wool, smiling amusedly at being
in the company of the big Danish lady, who spoke to her so kindly
and treated her as though she were a lady herself and not an old
parish-woman who had no home of her own. Ja, ja, that was very
nice, and Kari scratched her head, and smiled more and more, until
even the furrows on her grim old face were filled up with smiles, and
her eyes seemed almost young and very bright.
Ah, said Tante, with a friendly nod, I know some one who has
been very pretty. Oh, I have eyes—sharp, sharp eyes. I can see!](https://image.slidesharecdn.com/5244432-250617135305-714262ca/85/Distributed-Realtime-Systems-Theory-And-Practice-1st-Ed-K-Erciyes-63-320.jpg)
![hay-barns of various sizes and shapes, the most characteristic being
those with sloping bridges leading up to the top floor. And last, not
least, there was the great cowhouse, forsaken now except for five or
six cows which had not gone up to the Saeter. And Ingaros, the
most beautiful cow of all, christened after Mor Inga, was sulking
partly because she had not gone up to the Saeter, but chiefly
because she, the belle of the Gaard and the authorised leader of the
herd, had been deprived of her noble collar and bell. Some wretched
upstart of a creature was wearing it, so that she might be sure to
come home to her calves.
Ingaros had Tante's profound sympathy. She visited her in the
cowhouse at milking-time, and exchanged a few understanding
greetings with her. Old Kari was milking her and singing a soothing
little song, something about a saeter-girl who lost all her cows, and
she danced and they all came back again, and then she sang and
sang till they ran away again! Tante stood and listened delightedly to
the clear, sweet voice of the old woman.
Ja, ja, Kari, she said, I believe I have some coffee-berries in
my pocket. Such a song deserves a good cup of coffee.
Stakkar![E] said Kari, smiling with delight. Thou art a kind one,
although thou art not Norwegian. Thou shalt hear all the tunes I
know.
CHAPTER III.
It was a hot afternoon. Ejnar and Gerda had had a quarrel over
Salix. Ejnar's face wore the dynamite expression, and Gerda was
white with anger. Her glacier eyes looked like the eyes of a polar
bear, and she was moving her head to and fro in a manner which
always meant rebellion. On these occasions she longed for a divorce.
Give me a divorce at once! she cried tragically both to Ejnar and
Tante.
My dear one, remarked Tante soothingly, I don't keep divorces
ready in my pocket; and you know Ejnar never has even a
handkerchief in his pocket. You should have a divorce at once if we](https://image.slidesharecdn.com/5244432-250617135305-714262ca/85/Distributed-Realtime-Systems-Theory-And-Practice-1st-Ed-K-Erciyes-67-320.jpg)
![Obviously a person of discernment, Ejnar remarked several
times to Tante, who laughed secretly when she observed that the
impersonal botanist was beginning to show distinct signs of human
appreciation as well. He even left his study once or twice, and came
to sit with the ladies on the balcony, bringing his long pipe with him.
He did not speak much, of course, and when he did he never
touched on human affairs. But Katharine had seen these flowers,
and in an unscientific but vivid way she could tell him a little about
them, and a great deal about the botanists who had sent the
precious gift. Gerda and he listened with rapt attention while she
described to them the Colorado botanists' herbarium. She told them
that they were rich, but that they did not care for a grand house.
They lived in a small 'frame house,' and had built a princely
herbarium, which, together with their wonderful botanic garden, was
the chief feature of their property.
They do not care about human grandeur, Katharine said, in
conclusion.
That is as it ought to be, exclaimed Ejnar and Gerda
approvingly.
All the same, remarked Tante, I would prefer to inhabit that
herbarium, and put the stupid dried plants in the cottage. But then I
know I have a base human soul. Always have had—isn't it so, dear
ones?
Yes, yes, said Ejnar and Gerda. And you've always liked
comfort.
Yes, replied Tante—good English comfort. Give me good
English comfort and mange tak![F] Let me be base and comfortable,
like my darling, much-abused English people.
Are you really so fond of them, Fröken Knudsgaard? Katharine
said warmly; for every one feels a glow of pleasure at hearing one's
country praised in a foreign land.
Ja, I love them, Knutty replied, smiling at her; and I spend half
my time in fighting their battles. Even here I have several deadly
conflicts every day with a Norwegian magistrate and a fur-merchant
from the north. But now you've come, you can defend your own](https://image.slidesharecdn.com/5244432-250617135305-714262ca/85/Distributed-Realtime-Systems-Theory-And-Practice-1st-Ed-K-Erciyes-76-320.jpg)
![Then she was introduced to old Kari, whom they passed on their
way to Tante's favourite resting-place, an old black barn near a
group of mountain-ashes. Kari was standing outside the great
cowhouse; she looked at Katharine critically, seemed to approve of
her, and said:
She is nice looking, and strong too. She could do a good day's
work in the fields. And how many children has she got?
Well, I suppose she has not any, laughed wicked old Tante. She
is not married.
Perhaps she will find a husband here, said Kari reflectively.
Perhaps she will, laughed Tante; and she was passing on when
Kari came a little nearer to her and said mysteriously:
If thou wilt come into the cowhouse to-morrow, I think I can tell
thee something thou wilt like to hear—about the Huldre,[G] the
beautiful long-tailed one—but thou must come alone. And I will sing
to thee again very willingly, for thou art a kind one. And to-morrow
Mette makes Fladbröd.[H] If thou dost wish to see her make the
Fladbröd, thou shalt most certainly. Ja, and Mette can sing too. Thou
shalt hear her also.
Then she nodded and disappeared into the cowhouse. Tante and
Katharine paused for a moment to look at the picturesque winter-
house of the seventy cows, and its long, grass-grown roof, its two
bridges leading up to the top floor, where some of the hay was
stored, and its most curious gap in the centre of the upper floor,
through which one could see enclosed in a great oblong frame the
valley below, the rivers, and the distant mountains. Tante pointed
out this beautiful picture to Katharine and said:
You know, I really enjoy Nature very much, although I pretend
not to do so just to tease Ejnar and Gerda. Ah, they are dears, both
of them. It was good of you to come and bring them their parcel.
You do not know how eagerly you have been looked for—by them
and by me. Of course they wanted their parcel; but I had another
reason for being eager to receive you. May a wicked old woman tell
you something some day?
Tell me now, Katharine said, turning to her.](https://image.slidesharecdn.com/5244432-250617135305-714262ca/85/Distributed-Realtime-Systems-Theory-And-Practice-1st-Ed-K-Erciyes-79-320.jpg)
Distributed Realtime Systems Theory And Practice 1st Ed K Erciyes
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- 5. Computer Communications and Networks K. Erciyes Distributed Real-Time Systems Theory and Practice
- 6. Computer Communications and Networks Series Editors Jacek Rak, Department of Computer Communications, Faculty of Electronics, Telecommunications and Informatics, Gdansk University of Technology, Gdansk, Poland A. J. Sammes, Cyber Security Centre, Faculty of Technology, De Montfort University, Leicester, UK Editorial Board Burak Kantarci , School of Electrical Engineering and Computer Science, University of Ottawa, Ottawa, ON, Canada Eiji Oki, Graduate School of Informatics, Kyoto University, Kyoto, Japan Adrian Popescu, Department of Computer Science and Engineering, Blekinge Institute of Technology, Karlskrona, Sweden Gangxiang Shen, School of Electronic and Information Engineering, Soochow University, Suzhou, China
- 7. The Computer Communications and Networks series is a range of textbooks, monographs and handbooks. It sets out to provide students, researchers, and non-specialists alike with a sure grounding in current knowledge, together with comprehensible access to the latest developments in computer communications and networking. Emphasis is placed on clear and explanatory styles that support a tutorial approach, so that even the most complex of topics is presented in a lucid and intelligible manner. More information about this series at http://www.springer.com/series/4198
- 8. K. Erciyes Distributed Real-Time Systems Theory and Practice 123
- 9. K. Erciyes Department of Computer Engineering Üsküdar University Üsküdar, Istanbul, Turkey ISSN 1617-7975 ISSN 2197-8433 (electronic) Computer Communications and Networks ISBN 978-3-030-22569-8 ISBN 978-3-030-22570-4 (eBook) https://doi.org/10.1007/978-3-030-22570-4 © Springer Nature Switzerland AG 2019 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, expressed or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Switzerland AG The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland
- 10. To the memory of Professor Sinan Yılmaz who was a keen educator and a researcher on real-time systems, and to Professor Nevzat Tarhan for his strong belief and commitment in scientific research and the good things that naturally follow
- 11. Preface Distributed and embedded real-time systems are everywhere from factory floor to modern cars to avionics. A distributed real-time system is characterized by a number of computational nodes that are connected by a real-time network and cooperate to finish real-time tasks. A real-time task has a deadline and finishing of the task before its deadline is imperative in many applications. Recent techno- logical advancements have provided magnitudes of increase in the number of nodes of such distributed real-time systems which has resulted in a tremendous need for the software design of such systems. A distributed real-time system node has some computational capacity and is commonly interfaced to external world using sensors and actuators. Not all embedded systems are real time and we will use the term distributed real-time system to cover the distributed embedded systems that have real-time characteristics. This book is about the design and implementation of software for distributed real-time systems using a bottom-up approach. Having taught related courses at undergraduate and graduate levels for few decades, and being involved in large software projects associated with real-time systems, I have been able to observe the main bottlenecks for the designer and the implementer. First of all, the designer/implementer is often confronted with the challenge of interfacing the application with some commercial real-time operating system/middleware and sometimes writing patches to it. This requires an in-depth understanding of the hardware and operating system concepts related to real-time processing and we have a part related to system software for this reason. This part has three chapters in the first chapter of which we review basic real-time operating system concepts. We then construct an experimental distributed real-time operating system kernel (DRTK) from scratch in the second chapter by showing all necessary details. Consequently, we review distributed real-time operating system and middleware concepts and describe how to design network communications so that the real-time kernels can cooperate to have a distributed real-time system software frame in the last chapter. The experimental kernel is gradually transformed into a kernel of a distributed real-time operating system with associated middleware, showing all details of implementation in the proceeding parts of the book. The second challenge is of course scheduling of tasks so that all meet their deadlines. Tasks in a real-time system can be broadly classified as hard, soft, and vii
- 12. firm real-time tasks which can be periodic and aperiodic requiring different scheduling strategies. Moreover, they can be independent or dependent on each other necessitating means for inter-task synchronization in the latter. Yet, we need to provide end-to-end scheduling of tasks so that deadlines are met and load is distributed evenly to the nodes of the distributed real-time system. Another related problem is the management of resources over the network and all of these problems are investigated in Part II, always with implementation in mind. Finally, the designer is faced with the task of performing all of the steps of software engineering starting with specifying the requirements, then the high-level design, detailed design and coding. This process turns out to be where most diffi- culties are encountered. We provide a novel method to perform all of these steps simply and effectively. We have a chapter on high-level design and detailed design using finite-state machines which can be implemented using operating system threads. Fault tolerance is imperative in a real-time system to prevent catastrophic events and we have a chapter on this topic. We also review various real-time programming languages including C/POSIX, Ada, and Java. Finally, a real-time case study is presented in the final chapter by incorporating all of the methods we have developed and reviewed starting with high-level design followed by detailed design and then coding. In each chapter, we first review the concepts and then describe methods to design and implement the needed software by giving a brief survey of commercially available software. In the second part of a chapter where applicable, we show how to implement the described concepts in the experimental sample kernel by dis- playing the executable code. These parts are commonly called “DRTK Imple- mentation” in each chapter and can be skipped along with Chap. 5 which describes DRTK, when the book is used in a course with limited coverage of real-time systems. Finally, we provide review questions and then a summary of the chapter by emphasizing main points, give a contemporary review of the related literature, and show possible open research areas in the Chapter Notes section. About DRTK The main modules of DRTK described in detail in Chap. 5 are tested during teaching of various courses related to real-time processing. However, the parts related to distributed processing in the chapters that follow this chapter are not fully tested which means they may, or more likely, they would have some syntax or other implementation errors. I will keep a homepage of the book at http://akademik.ube. ege.edu.tr/*erciyes/DRTS for the code of DRTK, teaching slides and errata. Any modifications to the code of DRTK are welcome with the hope of making it a practical, experimental distributed real-time kernel that can be studied in related courses. viii Preface
- 13. The intended audience for this book are the senior undergraduate and graduate students and researchers of electrical and computer engineering, computer sci- ence, engineering in general, or any person with basic background in computer architecture and operating systems. The text contains considerable size of C code for the sample DRTK implementations and various examples. I would like to thank undergraduate and graduate students at various universities I have taught Real-time Systems, Embedded Systems, Advanced Operating Systems or similar courses including Ege University, Oregon State University, University of Cali- fornia Davis, California State University San Marcos, Izmir Institute of Tech- nology, Izmir University, and Üsküdar University in chronological order, for their valuable feedback when various parts of the material covered in the book were presented during lectures and the sample kernel was experimented in laboratory work. I would also like to thank Springer Senior Editor Wayne Wheeler and Associate Editor Simon Rees for their continuous support during the course of writing the book. Istanbul, Turkey K. Erciyes Preface ix
- 14. Contents Part I Introduction 1 Introduction to Real-Time Systems . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 What Is a Real-Time System . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 Basic Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 Characteristics of Real-Time Systems . . . . . . . . . . . . . . . . . . . 6 1.5 Classification of Real-Time Systems. . . . . . . . . . . . . . . . . . . . 7 1.6 An Example System: Bottling Plant . . . . . . . . . . . . . . . . . . . . 8 1.7 Outline of the Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.8 Review Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.9 Chapter Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 The Hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Processor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.1 Single Cycle Datapath. . . . . . . . . . . . . . . . . . . . . . . 13 2.2.2 Multi-cycle Datapath . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.3 Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.4 Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3.1 Interface to the Processor . . . . . . . . . . . . . . . . . . . . 25 2.3.2 Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.4 Input/Output Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.4.1 The Input Device Interface . . . . . . . . . . . . . . . . . . . 29 2.4.2 The Output Device Interface . . . . . . . . . . . . . . . . . . 30 2.4.3 Memory-Mapped and Isolated I/O . . . . . . . . . . . . . . 30 2.4.4 Software Interface to I/O . . . . . . . . . . . . . . . . . . . . . 31 2.5 Multicore Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.6 Multiprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.7 Review Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 xi
- 15. 2.8 Chapter Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.9 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3 Distributed Real-Time Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.2 Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.2.1 Time- and Event-Triggered Distributed Systems . . . . 42 3.2.2 Finite-State Machines . . . . . . . . . . . . . . . . . . . . . . . 43 3.3 Distributed Real-Time Operating Systems and The Middleware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3.1 The Middleware . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3.2 Distributed Scheduling . . . . . . . . . . . . . . . . . . . . . . 46 3.3.3 Dynamic Load Balancing . . . . . . . . . . . . . . . . . . . . 48 3.4 Real-Time Communication . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.4.1 Real-Time Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.4.2 Open Systems Interconnection Model . . . . . . . . . . . 50 3.4.3 Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.4.4 Real-Time Data Link Layer . . . . . . . . . . . . . . . . . . . 52 3.4.5 Controller Area Network Protocol . . . . . . . . . . . . . . 53 3.4.6 Time-Triggered Protocol . . . . . . . . . . . . . . . . . . . . . 54 3.4.7 Real-Time Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.4.8 Real-Time IEEE 802.11 . . . . . . . . . . . . . . . . . . . . . 56 3.5 Challenges in Distributed Real-Time Embedded Systems. . . . . 57 3.6 Examples of Distributed Real-Time Systems . . . . . . . . . . . . . . 57 3.6.1 A Modern Car . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.6.2 A Mobile Wireless Sensor Network . . . . . . . . . . . . . 58 3.7 Review Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.8 Chapter Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.9 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Part II System Software 4 Real-Time Operating Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.2 A General Operating System Versus a Real-Time Operating System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.3 Task Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.3.1 Task Management in UNIX . . . . . . . . . . . . . . . . . . 68 4.3.2 Inter-task Synchronization . . . . . . . . . . . . . . . . . . . . 70 4.3.3 Inter-task Communication . . . . . . . . . . . . . . . . . . . . 71 4.3.4 UNIX Interprocess Communications . . . . . . . . . . . . 73 xii Contents
- 16. 4.4 Threads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.4.1 Thread Management . . . . . . . . . . . . . . . . . . . . . . . . 75 4.4.2 POSIX Threads . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.5 Memory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.5.1 Static Memory Allocation . . . . . . . . . . . . . . . . . . . . 80 4.5.2 Dynamic Memory Allocation . . . . . . . . . . . . . . . . . 81 4.5.3 Virtual Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.5.4 Real-Time Memory Management . . . . . . . . . . . . . . . 81 4.6 Input/Output Management . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.6.1 Interrupt-Driven I/O . . . . . . . . . . . . . . . . . . . . . . . . 82 4.6.2 Device Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.7 A Survey of Real-Time Operating Systems. . . . . . . . . . . . . . . 84 4.7.1 FreeRTOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.7.2 VxWorks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.7.3 Real-Time Linux . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.8 Review Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.9 Chapter Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.10 Programming Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5 Design of an Experimental Distributed Real-Time Kernel . . . . . . . 89 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.2 Design Strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.3 Lower Level Kernel Functions . . . . . . . . . . . . . . . . . . . . . . . . 90 5.3.1 Data Structures and Queue Operations . . . . . . . . . . . 91 5.3.2 A Multi-queue Scheduler . . . . . . . . . . . . . . . . . . . . 95 5.3.3 Interrupt Handling and Time Management . . . . . . . . 98 5.3.4 Task State Management . . . . . . . . . . . . . . . . . . . . . 99 5.3.5 Input/Output Management . . . . . . . . . . . . . . . . . . . . 101 5.4 Higher Level Kernel Functions . . . . . . . . . . . . . . . . . . . . . . . 103 5.4.1 Task Synchronization . . . . . . . . . . . . . . . . . . . . . . . 104 5.4.2 Task Communication . . . . . . . . . . . . . . . . . . . . . . . 107 5.4.3 High Memory Management Using Pools . . . . . . . . . 110 5.4.4 Task Management. . . . . . . . . . . . . . . . . . . . . . . . . . 112 5.5 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 5.6 Testing DRTK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 5.7 Review Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 5.8 Chapter Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 5.9 Programming Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Contents xiii
- 17. 6 Distributed Real-Time Operating Systems and the Middleware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6.2 Distributed Real-Time Operating Systems. . . . . . . . . . . . . . . . 120 6.2.1 Transport Layer Interface . . . . . . . . . . . . . . . . . . . . 120 6.2.2 Data Link Layer Interface . . . . . . . . . . . . . . . . . . . . 122 6.3 Real-Time Middleware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3.1 Real-Time Task Groups . . . . . . . . . . . . . . . . . . . . . 124 6.3.2 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . 125 6.3.3 Election Algorithms . . . . . . . . . . . . . . . . . . . . . . . . 132 6.4 DRTK Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 6.4.1 Initializing the Network. . . . . . . . . . . . . . . . . . . . . . 134 6.4.2 Transport Layer Interface . . . . . . . . . . . . . . . . . . . . 136 6.4.3 Data Link Layer Interface Tasks . . . . . . . . . . . . . . . 139 6.4.4 Group Management . . . . . . . . . . . . . . . . . . . . . . . . 142 6.4.5 Clock Synchronization Algorithm . . . . . . . . . . . . . . 144 6.4.6 Leader Election in a Ring . . . . . . . . . . . . . . . . . . . . 145 6.5 Review Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 6.6 Chapter Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 6.7 Programming Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Part III Scheduling and Resource Sharing 7 Uniprocessor-Independent Task Scheduling . . . . . . . . . . . . . . . . . . 151 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 7.2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 7.2.1 Schedulability Test . . . . . . . . . . . . . . . . . . . . . . . . . 153 7.2.2 Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 7.3 Scheduling Policies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 7.3.1 Preemptive or Non-preemptive Scheduling . . . . . . . . 154 7.3.2 Static or Dynamic Scheduling . . . . . . . . . . . . . . . . . 155 7.3.3 Independent or Dependent Tasks . . . . . . . . . . . . . . . 156 7.4 A Taxonomy of Real-Time Scheduling Algorithms . . . . . . . . . 157 7.5 Clock-Driven Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 7.5.1 Table-Driven Scheduling . . . . . . . . . . . . . . . . . . . . . 158 7.5.2 Cyclic Executive. . . . . . . . . . . . . . . . . . . . . . . . . . . 160 7.6 Priority-Based Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 7.6.1 Rate Monotonic Scheduling. . . . . . . . . . . . . . . . . . . 162 7.6.2 Earliest Deadline First Scheduling . . . . . . . . . . . . . . 164 7.6.3 Least Laxity First Algorithm . . . . . . . . . . . . . . . . . . 167 7.6.4 Response Time Analysis . . . . . . . . . . . . . . . . . . . . . 167 xiv Contents
- 18. 7.7 Aperiodic Task Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . 169 7.7.1 Basic Approaches . . . . . . . . . . . . . . . . . . . . . . . . . . 170 7.7.2 Periodic Servers . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 7.8 Sporadic Task Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 7.9 DRTK Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 7.9.1 The Rate Monotonic Scheduler . . . . . . . . . . . . . . . . 175 7.9.2 Earliest Deadline First Scheduler . . . . . . . . . . . . . . . 176 7.9.3 The Least Laxity First Scheduler . . . . . . . . . . . . . . . 177 7.9.4 Polling Server. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 7.10 Review Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 7.11 Chapter Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 7.12 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 8 Uniprocessor-Dependent Task Scheduling . . . . . . . . . . . . . . . . . . . . 183 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 8.2 Dependent Task Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . 183 8.2.1 Latest Deadline First Algorithm . . . . . . . . . . . . . . . . 184 8.2.2 Modified Earliest Deadline First Algorithm . . . . . . . 184 8.3 Scheduling of Resource Sharing Tasks . . . . . . . . . . . . . . . . . . 187 8.3.1 The Case of Mars Pathfinder . . . . . . . . . . . . . . . . . . 189 8.3.2 Basic Priority Inheritance Protocol . . . . . . . . . . . . . . 190 8.3.3 Priority Ceiling Protocol . . . . . . . . . . . . . . . . . . . . . 194 8.4 DRTK Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 8.4.1 LDF-Dependent Task Scheduling . . . . . . . . . . . . . . 196 8.4.2 Priority Inheritance Protocol . . . . . . . . . . . . . . . . . . 197 8.5 Review Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 8.6 Chapter Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 8.7 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 9 Multiprocessor and Distributed Real-Time Scheduling . . . . . . . . . . 203 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 9.2 Multiprocessor Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 9.2.1 Partitioned Scheduling . . . . . . . . . . . . . . . . . . . . . . 204 9.2.2 Global Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . 210 9.3 Distributed Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 9.3.1 Load Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 9.3.2 Focused Addressing and Bidding Method . . . . . . . . 214 9.3.3 Buddy Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . 216 9.3.4 Message Scheduling . . . . . . . . . . . . . . . . . . . . . . . . 216 9.4 DRTK Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 9.4.1 Central Load Balancing Tasks . . . . . . . . . . . . . . . . . 218 9.4.2 Distributed Load Balancing Task . . . . . . . . . . . . . . . 220 Contents xv
- 19. 9.5 Review Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 9.6 Chapter Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 9.7 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Part IV Application Design 10 Software Engineering of Real-Time Systems . . . . . . . . . . . . . . . . . . 227 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 10.2 Software Development Life Cycle . . . . . . . . . . . . . . . . . . . . . 228 10.2.1 The Incremental Waterfall Model . . . . . . . . . . . . . . 228 10.2.2 V-Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 10.2.3 Spiral Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 10.3 Software Design of Real-Time Systems . . . . . . . . . . . . . . . . . 231 10.4 Requirement Analysis and Specification . . . . . . . . . . . . . . . . . 232 10.5 Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 10.6 Structured Design with Data Flow Diagrams . . . . . . . . . . . . . 233 10.7 Object-Oriented Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 10.8 Real-Time Implementation Methods . . . . . . . . . . . . . . . . . . . . 236 10.8.1 Finite State Machines Re-visited . . . . . . . . . . . . . . . 236 10.8.2 Timed Automata . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 10.8.3 Petri Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 10.9 Real-Time Unified Modeling Language . . . . . . . . . . . . . . . . . 243 10.9.1 UML Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 10.9.2 Real-Time Features . . . . . . . . . . . . . . . . . . . . . . . . . 246 10.10 A Practical Design and Implementation Method . . . . . . . . . . . 246 10.11 Review Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 10.12 Chapter Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 10.13 Programming Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 11 Real-Time Programming Languages . . . . . . . . . . . . . . . . . . . . . . . . 251 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 11.2 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 11.3 A Real-Time Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 11.4 C/Real-Time POSIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 11.4.1 Data Encapsulation and Module Management. . . . . . 254 11.4.2 POSIX Thread Management . . . . . . . . . . . . . . . . . . 255 11.4.3 Exception Handling and Low-Level Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 11.4.4 C/Real-Time POSIX Process Control Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 11.5 Ada . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 11.5.1 Concurrency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 xvi Contents
- 20. 11.5.2 Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . 267 11.5.3 Ada Process Control Implementation . . . . . . . . . . . . 268 11.6 Java . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 11.6.1 Java Threads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 11.6.2 Thread Synchronization. . . . . . . . . . . . . . . . . . . . . . 271 11.6.3 Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . 273 11.7 Review Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 11.8 Chapter Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 11.9 Programming Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 12 Fault Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 12.2 Concepts and Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . 278 12.3 Fault Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 12.4 Redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 12.4.1 Hardware Redundancy . . . . . . . . . . . . . . . . . . . . . . 280 12.4.2 Information Redundancy . . . . . . . . . . . . . . . . . . . . . 281 12.4.3 Time Redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . 283 12.4.4 Software Redundancy . . . . . . . . . . . . . . . . . . . . . . . 284 12.5 Fault-Tolerant Real-Time Systems . . . . . . . . . . . . . . . . . . . . . 286 12.5.1 Static Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . 287 12.5.2 Dynamic Scheduling . . . . . . . . . . . . . . . . . . . . . . . . 287 12.6 Fault Tolerance in Distributed Real-Time Systems . . . . . . . . . 288 12.6.1 Failure Classification . . . . . . . . . . . . . . . . . . . . . . . . 288 12.6.2 Task Groups Revisited . . . . . . . . . . . . . . . . . . . . . . 289 12.7 DRTK Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 12.8 Review Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 12.9 Chapter Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 12.10 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 13 Case Study: Environment Monitoring by a Wireless Sensor Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 13.2 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 13.3 Requirement Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 300 13.4 Timing Analysis and Functional Specifications . . . . . . . . . . . . 301 13.5 Spanning Tree and Clustering . . . . . . . . . . . . . . . . . . . . . . . . 302 13.6 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 13.7 Leaf Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 13.7.1 High-Level Design . . . . . . . . . . . . . . . . . . . . . . . . . 307 13.7.2 Detailed Design and Implementation . . . . . . . . . . . . 309 Contents xvii
- 21. 13.8 Intermediate Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 13.8.1 High-Level Design . . . . . . . . . . . . . . . . . . . . . . . . . 315 13.8.2 Detailed Design and Implementation . . . . . . . . . . . . 316 13.9 Clusterhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 13.9.1 High-Level Design . . . . . . . . . . . . . . . . . . . . . . . . . 321 13.9.2 Detailed Design and Implementation . . . . . . . . . . . . 321 13.10 The Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 13.10.1 High-Level Design . . . . . . . . . . . . . . . . . . . . . . . . . 324 13.11 Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 13.12 Alternative Implementation with POSIX Threads . . . . . . . . . . 327 13.13 Chapter Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 13.14 Programming Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 Appendix A: Pseudocode Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 Appendix B: Lower Kernel Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 xviii Contents
- 23. 1 Introduction to Real-Time Systems 1.1 Introduction Real-time systems are everywhere, from cars and cell phones to avionics to nuclear plantcontrol.Areal-timesystemischaracterizedbyitstimelinessinresponsetosome input. Failure to respond in a specified time may result in catastrophic failures in these systems. The correctness of a real-time system depends both on the correctness of the results and the time these are produced which are termed logical correctness and temporal correctness consecutively. In an embedded real-time system, the real- time computing element is embedded in the system to be controlled and most of the real-time systems fall into this category. There are many types of real-time systems; a real-time process control system receives input data from sensors, performs some operation on this data, and pro- duces output to control various system functions such as turning switches on and off, activating alarms if necessary, and display system data. An aircraft is a real-time system with strict time constraints to be met whereas failing to meet the time con- straints of a multimedia system will generally result in poor performance only. Other examples of real-time systems include robotic systems, nuclear power plants, and mobile phones. We review basic concepts related to real-time systems in this chapter starting with definitions, types of real-time systems, and properties of these systems. We then describe the operation of exemplary real-time systems and conclude by outlining the contents of the book. © Springer Nature Switzerland AG 2019 K. Erciyes, Distributed Real-Time Systems, Computer Communications and Networks, https://doi.org/10.1007/978-3-030-22570-4_1 3
- 24. 4 1 Introduction to Real-Time Systems 1.2 What Is a Real-Time System A real-time system operates with a time constraint, where the time that the output produced is significant. In other words, producing the output at some other time than the required time may be meaningless. Alternatively, a real-time system is a data processing system which responds to external inputs within a finite specified time called deadline. Failure to respond to the input within a deadline may cause harm to lives and property. A real-time system is designed according to the dynamics of the physical processes it has to control. A real-time computing system consists of hardware and software working with time constraints. The real-time software embodies the following components in general: • A Real-time Operating System: An operating system has two main functions: pro- viding convenient access to the hardware and efficient management of resources. For this purpose, it provides process (task) management, memory management, and input/output management in general. A real-time operating system still has these tasks to perform but with strict time constraints. A real-time operating system is typically small in size to be easily accommodated in embedded systems and it has to be fast with minimum operating system overheads. • A Real-time Programming Language: A real-time programming language pro- vides basic schemes such as inter-task communication and synchronization, error handling, and scheduling for real-time tasks. Note that these functions are also provided by the real-time operating system. Hence, a real-time programming lan- guage can be used alternatively to a real-time operating system to achieve real-time processing. At the lowest level, an assembler can be used to access registers and other hardware of the processor. However, an assembler language is error prone and is not portable to another processor. The C language is widely used in real- time systems as it provides access to hardware and has very simple input/output interface. However, various other languages such as Ada and real-time Java are developed for real-time systems to ease their programming. • A Real-time Network: A computer network provides transfer of data between var- ious computing devices. A real-time network should provide a reliable delivery of messages within specified time limits. Key to the operation of a real-time net- work is the reliable and timely transfer of messages. A real-time communication protocol provides timely and guaranteed delivery of messages over the network. At this point, it may be right to distinguish a real-time system from a system that looks real time but in fact does not conform to what is generally accepted as real time. For example, an online system interfaced to a user is not considered real time since tasks have no defined deadlines. Also, a system that has to react fast does not necessarily mean it is real time. An embedded system is characterized by the computing element being an element contained in the system. Embedded systems are not general computing systems where the computer may be programmed dynamically to achieve different tasks. On the contrary, they are built for a special purpose such as a microwave oven. An
- 25. 1.2 What Is a Real-Time System 5 embedded system is tightly coupled to the external physical world. Home and per- sonal appliances that are used to assist living are examples of embedded systems. In fact, embedded systems constitute majority of computer-based systems. An embed- ded system may be real time or not depending on the application. A non-real-time embedded system has no time bounds, for example, an MP3 player is a non-real-time embedded system. However, we find significant percentage of real-time applications is embedded. An embedded real-time system is designed for a specific function and works with real-time constraints. Our terminology in this book refers to real-time systems in general, including real-time embedded systems. Real-time systems can be classified using various approaches; one main arrange- ment is based on the synchronization and interaction among various components of the system. Consecutively, a real-time system may be time driven in which each activity has a specific time assigned to it; event driven where external inputs deter- mine the behavior of the system or interactive where the user may change the mode of the operation. In many cases, a real-time system works as a combination of all of these modes. 1.3 Basic Architecture A real-time system consists of the following components in hardware as shown in Fig.1.1, which is detailed as follows: • Sensors: A sensor converts a physical parameter into an electrical signal to be processed. For example, a thermocouple is a heat sensor that converts heat to an electrical signal. • Processing Element (PE): The real-time processing element or the real-time com- puter receives digital data as provided by the input interface unit, processes data, and decides on some output function to perform. • Actuators: An actuator inputs the electrical signal from the output interface of the processing element and actuates a physical action. A relay is an example of an actuator that opens/closes a switch when activated by a signal. • Input Interface: The input interface to the real-time computer processes and con- verts the electrical signal to digital form to be processed. Sensors may have the needed converters embedded in them. • Output Interface: The binary output from the real-time computer is processed and converted to the form of signal needed by the actuator or other output devices in the output interface.
- 26. 6 1 Introduction to Real-Time Systems Fig.1.1 Architecture of a typical real-time system User Interface Real-time Application ... S A Output Input Interface Interface Processing Element S A Sensor Actuator 1.4 Characteristics of Real-Time Systems Common characteristics of real-time systems are as follows: • Meeting Deadlines: Deadlines of all hard real-time tasks must be met to prevent loss of lives and property. • Large Size: Real-time systems are commonly large and complex in terms of hard- wareoccasionallybutmostlyinthesizeofthesoftwareused.Evenasmallreal-time system may have hundreds of thousands of lines of code to run. • Predictability: We need to be able to predict the worst-case response times and whether the deadlines of all tasks will be met prior to the execution of tasks in a real-time system. Predictability commonly involves proving theoretically that all deadlines will be met in a hard real-time system. • Safety and Reliability: Real-time systems operate and control environments such as nuclear plants and process control, where safety and reliability are of utmost concern. Unsafe and unreliable systems are prone to errors which may result in loss and damage to lives and property. • Fault Tolerance: A fault is said to occur when a component of hardware or soft- ware of a computer system fails and the system does not behave according to its specification anymore. A failure is the result of a fault, which may cause loss of lives and property in a real-time system. A fault may be permanent causing the system to fail permanently or transient, which may disappear after some time. Fault tolerance is the ability of a system to resist faults and continue functioning correctly in the presence of faults.
- 27. 1.4 Characteristics of Real-Time Systems 7 0 Deadline Gain 100% Response Time 0 Deadline Gain 100% Response Time (a) (b) Fig.1.2 Utilization values of a hard and firm real-time systems, b soft real-time system • Concurrency: The physical environment to be controlled by the real-time com- puter commonly exhibits parallel execution of events. The real-time computer must be able to cope with this parallel operation using concurrent system software capabilities or distributed hardware. 1.5 Classification of Real-Time Systems We can specify the types of real-time systems in terms of the input received, on timing constraints, and the type of processes in the system. We can have the following classification when deadlines are considered: • Hard Real time: Missing a hard deadline may cause catastrophic results, which may result in the loss of property or lives. Aircraft maneuvering systems, chemical plants, and nuclear power stations are examples of such systems. All deadlines of tasks are hard in a hard real-time system. The gain or the utilization of the system when a deadline is missed is zero in such a system as depicted in Fig.1.2a. • Soft Real time: Missing a soft deadline is not critical, however, system quality of service degrades when this happens. A soft real-time system has tasks with soft deadlines. Multimedia systems and airline reservation systems are examples of soft real-time systems. The gain or the utilization of the system when a deadline is missed degrades but does not go to zero immediately as shown in Fig.1.2b. • Firm Real time: These systems are basically soft real-time systems in which there is no gain when a firm deadline is missed. The utility of the system goes down to zero immediately in these systems as shown in Fig.1.2a but the system tolerates these deadline misses. A real-time system may have a mixture of tasks that are hard, soft, and firm real time. The processes in the system may be static with deterministic characteristics known beforehand whereas characteristics in a dynamic real-time system vary with time. Another distinction is about how processing is performed as below.
- 28. 8 1 Introduction to Real-Time Systems • Event-driven Real-time Systems: External events dictate when and how real-time processing is performed in these systems. An event-driven system handles asyn- chronous inputs activated by events. • Time-driven Real-time Systems: Processing is performed in a well-defined time base and the actions to be taken are done in strict time points. A time-driven real-time system has synchronous inputs. For example, a humidity monitoring of air with a sensor measuring the humidity every t time units is a time-driven system, whereas a system that is activated by an asynchronousexternaleventisanevent-drivensystem.Commonly,wehaveamixture of these modes in a typical real-time system. For example, temperature control of an oven can be performed by measuring the temperature at regular intervals (time driven) and turning the heater off when door of the oven is opened (event driven). A distributed system consists of autonomous computers each of which has the capability to function alone. These computers are connected by a network and coop- erate to perform global tasks and share resources. A distributed real-time system is a distributed computing system that works with time constraints. Distributed systems provide efficient resource sharing and redundancy. Also, dis- tribution of computation across a number of nodes is convenient since fast local processing is possible. Yet another reason to employ a distributed real-time system is that various subsystems by different producers can be interfaced using standard communication protocols. A car is a distributed real-time system since data read from many sensors is transferred over a real-time network to various nodes to be processed. Another advantage gained in using a distributed real-time systems is increased reli- ability since the failure of a node may not affect the operation of the whole system significantly when precautions are taken in advance. 1.6 An Example System: Bottling Plant Let us look at a very simple real-time process control system where milk is bottled. The milk bottles move over a conveyor belt and there are three machines; a washer to wash the bottles, a filler that fills milk, and a capper to put the cap on the filled bottle as shown in Fig.1.3. Each machine is interfaced to the real-time computer system with sensors and actuators. The computer system has to perform three tasks in sequence as follows: 1. Washing: The arrival of a dirty bottle over the conveyor belt is signaled by a sensor. The belt is stopped and the washer is activated for tw seconds and then the belt is activated. We see here an event-based (sensing the coming of bottle) operation. 2. Filling: The coming of bottle is sensed and the filling begins by activating the filler. The level of milk is monitored by a sensor and it stops when the desired level is reached.
- 29. 1.6 An Example System:Bottling Plant 9 Fig.1.3 Architecture of a typical real-time system REAL-TIME COMPUTER SYSTEM SENSORS AND ACTUATORS WASHER FILLER CAPPER CONVEYOR BELT 3. Capping: When bottle arrives under this machine, a cap is placed on top of it and the bottle is ready to be packed. We see dominantly event-driven processing here. However, with careful timing, the whole process can be performed time driven by periodically performing the washing, filling, and capping processes assuming there are always empty bottles to process. Note that the whole process is slow leaving considerable idle time for the computer to do other processing. 1.7 Outline of the Book We have four sections in the book as follows: 1. Introduction: This part serves as an introduction to real-time systems with chap- ters on real-time architecture and distributed real-time systems. 2. System Software: The real-time operating system is the focus of this part where we describe the basic concepts such as task, memory, and input/output man- agement. We also provide a detailed step-by-step construction of a real-time operating system kernel which is used to test various higher level implementa- tions in the proceeding chapters. 3. Scheduling and Resource Management: Scheduling of tasks so that deadlines are met is a fundamental function of any real-time system. We first describe independent periodic and aperiodic scheduling and then dependent scheduling with resource management and distributed scheduling in this part.
- 30. 10 1 Introduction to Real-Time Systems 4. Application Design: This part is fundamental to aid designers of real-time system software. We describe the design procedure from high-level design methods to low-level design and implementation. We also provide a survey of real-time programming languages and fault tolerance techniques. This part ends with a detailed case study in which we show the implementation of the methods reviewed in a real-life application. 1.8 Review Questions 1. What is the relationship between a real-time system and an embedded system? Are all embedded systems real time? Discuss by giving examples. 2. What are the main components of a real-time system? 3. What is a sensor and an actuator in a real-time system? Give an example of each. 4. What type of hardware do you expect to be in the input interface of a real-time computer system? 5. What is hard real-time, soft real-time, and a firm real-time system? 6. Give an example each of event-driven and time-driven real-time system. 7. What are the main characteristics of a distributed real-time system? 1.9 Chapter Notes We have looked at the main components of a real-time computer system, its basic architecture, and different classifications of these systems. Real-time systems can have hard, soft, and firm deadline tasks when tasks are considered. On the other hand, the processing can be handled as event driven and time driven. A real-time computer can be embedded in the environment it has to control in an embedded system and it can be distributed over a real-time network. Generally, a real-time system has a combination of these properties. General concepts about real-time systems are described in [2] and real-time programming languages are contained in [1]. References 1. Burns A, Wellings A (2001) Real time systems and programming languages: Ada 95, Real-time Java and real-time C/POSIX, 3rd edn. Addison-Wesley 2. Laplante PA, Ovaska SJ (2011) Real-time systems design and analysis: tools for the practitioner, 4th edn. Wiley
- 31. 2 The Hardware 2.1 Introduction Most of the real-time computing systems employ general-purpose hardware com- ponents such as the processor, memory, and input/output units. An embedded real- time system may have special input/output interface units dedicated for the appli- cation. The main difference between a non-real-time system and a real-time system at hardware-specific software level is the structure of the low-level software such as handling of the interrupts and time management. In order to fully understand the operation of this software and operating system interface to it, we need to look at the hardware characteristics. In this chapter, we review the hardware of a real-time system node at component level by deferring the review of the architecture and basic software structure of a dis- tributed real-time system to the next chapter. We start with the basic interface units: sensors and actuators and review characteristics of the common types of these com- ponents. The processor is where the actual processing is performed and single cycle, multi-cycle, and pipelined datapaths are discussed next. Memory and input/output units are other main parts of a real-time system as we will see. We will use the MIPS processor [1] to describe the hardware-related concepts as this processor is widely used in embedded systems and yet simple enough to display operation. 2.2 Processor Architecture The Von Neumann model of computation is based on stored program computer concept where instruction and data are stored in the same memory. This architecture is the basis of most of the contemporary processors. The processor consists of a control unit, arithmetic logic unit (ALU), and registers in this model of computing © Springer Nature Switzerland AG 2019 K. Erciyes, Distributed Real-Time Systems, Computer Communications and Networks, https://doi.org/10.1007/978-3-030-22570-4_2 11
- 32. 12 2 The Hardware Fig.2.1 Architecture of a processor INPUT UNIT CONTROL UNIT ALU REGISTER FILE MEMORY UNIT OUTPUT as shown in Fig.2.1. The ALU, the register file that contains all of the registers and the interfacing circuitry is commonly called the datapath. A processor first fetches an instruction from the memory and decodes it to decide on which action to perform. It then finds any data needed and finally executes the instruction and writes the produced output to the memory if needed. The instruction set architecture (ISA) is an abstraction to form the interface between the software and the hardware. The ISA comprises basically the assembly language of the processor and provides instructions such as add, sub, and and to perform operations on the processor. In other words, the ISA is the programmer’s view of the hardware and specifies the memory organization, temporary memory locations within the CPU called the registers and the instruction set. Two types of ISA-based computing are in common use: complex instruction set computing (CISC) and reduced instruction set computing (RISC). A CISC processor uses as few lines of assembly programming as possible and hence is closer to a high- level language than the RISC processor which executes simple instructions typically in one clock cycle. For example, multiplication of two numbers can be performed by a simple MULT M1, M2, M3 instruction in CISC computing which multiplies two values in memory locations M1 and M2 and stores the result in memory M3. The same multiplication needs to be broken down into several RISC instructions such as loading values from memory to two registers, adding the values in the registers inside a loop and storing the result in memory. At first glance, a RISC processor seems to be executing more lines of assembly lines than a CISC processor. Also, the compiler does less work in converting a high-level language statement to assembly language in CISC computing requiring less storage for RAM to store assembly lines. However, a CISC processor may need to work few clock cycles for an instruction whereas a RISC processor commonly finishes a line of assembly code in one clock cycle making the design of a RISC processor simpler than a CISC processor. The mode of operation of datapath can be single cycle, multi-cycle, or pipelined as described in the next sections.
- 33. 2.2 Processor Architecture 13 2.2.1 Single Cycle Datapath We will briefly describe the microprocessor without interlocked pipeline stages (MIPS) 32-bit processor datapath and its control unit as an example of a single cycle datapath. MIPS is a RISC commonly used in embedded systems and yet is simple to display the main functions of a processor. MIPS has 32 registers each with 32-bit length; hence, a 5-bit address is needed to select a register. We will first review the ISA of MIPS which has three modes: R-type, I-type, and J-type. An R-type (register type) considers the instruction word to consist of the fields shown in Fig.2.2a. The fields in the instruction are as follows: • opcode: This 6-bit field is used to decode the instruction operation. It is the main input to the control unit that generates required control signals for the instruction. • rs: 5-bit address of the first source register. • rt: 5-bit address of the second source register. • rd: 5-bit address of the destination register. • shamt: 5-bit shift amount. • funct: 6-bit function code. This field is used to perform a subfunction such as addition of an R-type instruction. It can be used as an input to the ALU. For example, the instruction add $7, $14, $10 R-type 31 26 25 21 20 16 15 11 10 6 5 0 op rs rt rd shamt func 31 26 25 21 20 16 15 0 offset/immediate J-type 31 26 25 0 destination op rs rt op I-type (a) (b) (c) Fig.2.2 MIPS instruction modes
- 34. 14 2 The Hardware Read reg1 Read reg2 Write reg Write data RegWrite ALU ALUOp Instruction . . Instruction Memory Read address [25-21] [20-16] [15-11] [31-0] Read data1 data2 Read Fig.2.3 MIPS datapath for R-type instruction in binary and hexadecimal notation would be op rs rt rd shamt func ----- ------ ------ ------ ------ ------- 00 0000 0 1110 0 1010 0 0111 0 0000 10 0000 The 32-bit instruction would then be 0 x 01CA:3820 in hexadecimal notation. Let us take a closer look at how this instruction is executed in the simple datapath of Fig.2.3. 1. The read address is provided to the instruction memory and the 32-bit instruction word (01CA:3820) is fetched. 2. The instruction word is at the output of the instruction memory and its 11–25 bits are fed to the register file to select the read registers and the write register. 3. The contents of the read registers 14 and 10 appear at read data outputs of the register file and at the inputs of ALU. 4. The add operation is selected in ALU by the ALUOp. 5. The sum of contents of registers 14 and 10 appears at the output of ALU and at Write data input of the register file. 6. Activating RegWrite signal provides writing of the sum to the contents of register 7. The task of the control unit is to provide the control signals ALUOp and RegWrite by the value present in the opcode field of the instruction word. Providing these signalsintheabove-describedsequenceisdifficultandnotnecessary.Wecanhavethe control signals present throughout a whole cycle and if the cycle is long enough, the produced output will be correctly settled in the single cycle datapath implementation. Determining the length of the cycle is crucial in this design method and it should be as long as the longest instruction.
- 35. 2.2 Processor Architecture 15 Read reg1 Read reg2 Write reg Write data RegWrite ALU ALUOp Instruction Instruction Memory Read address [25-21] [20-16] [15-11] [31-0] Data Memory MemWrite MemRead . . 0 1 0 1 Read address Write address Write data Sign data1 Read Read data2 extend Mux Mux 0 1 Read data . . . . RegDst MemToReg ALUSrc [15-0] Fig.2.4 MIPS datapath with data memory We need to write the generated output to external data memory instead of a destination register commonly. The I-type of addressing with the format shown in Fig.2.2 is used for this purpose and MIPS has two instructions to store data to and remove data from data memory as follows: lw $2, 12($1) sw $2, 12($1) In this example, the load word (lw) instruction loads a 32-bit word from the data memory location at the address pointed by the contents of register $1+12 into register $2 and the store word (sw) does the opposite by storing the contents of the register $2 at data memory address $1+12. We will now extend the datapath to include I-type of instructions as shown in Fig.2.4. There are three additional 2:1 multiplexers to be able to distinguish the instruction modes. In I-type instruction, the second register field contains the write address now, so we need to pick bits (20–16) as this value for this mode by activating RegDest control of the first multiplexer. There is a sign-extend circuit to extend the 16-bit value in the lower half of the instruction word for addition of the first register value to the contents of the address contained in the register plus the offset value. The second multiplexer selects the R-type or I-type operation by its ALUSrc input. Lastly, the third multiplexer selects whether the contents of the data memory location (I-type) or the results of the ALU operation (R-type) are to be written to the register file by the MemToReg control signal or not. Loading from or writing to data memory is selected by MemWrite or MemRead signals. Let us list the control signals needed for the lw 2, 12($1) instruction. We only need to supply the address of the instruction to the instruction memory without the need for a read signal since all write operations are controlled by the control unit. The opcode for this instruction which is 100011 is fed to the control unit which outputs the following signal values:
- 36. 16 2 The Hardware • RegDest = 0 since we want to interpret the bits (20–16) of the instruction word as the write reg address as this is an I-type instruction. • RegWrite = 1 since we need to write to register file the contents of the data memory location. • ALUSrc = 1 since we want to add the sign extended bits (15–0) of the instruction word to the value in register 1. • ALUOp = 010 in binary for add operation. • MemRead = 1 and MemWrite = 0 to allow reading the value contained in the location calculated by the ALU. • MemToReg = 1 provides writing of the output value from the data memory to the register 2 in the register file. Maintaining these values throughout the whole cycle by the control unit provides the correct operation for this instruction. The J-type of instruction is used for diverting from the normal flow of the program to a new instruction address. The branch instruction is basically used to translate an if statement in a high-level language and has the following format: beq $1, $2, offset The values in registers 1 and 2 are compared by subtracting their values in the ALU and the address calculated by the instruction pointer (IP) value + 4 + (4 × offset) is loaded to IP if the result is 0. If these values are not equal or the instruction is not a branch, the value of IP is incremented by 4 to read the next location from the instruction memory. We now have two adders to be able to proceed in parallel with the ALU comparison of two input registers 1 and 2; one to calculate IP+4, and another one to calculate the branch address as shown in Fig.2.5. Note that branch address is calculated in any case but we simply do not select it by not activating PCSrc signal if the branch comparison fails or we have an R-type instruction. Control Unit The control unit has 6-bit opcode, 6-bit function field of the instruction, and 1-bit zero output of the ALU as its inputs and it has to generate all required signals for each instruction. It can be realized by a simple combinational circuit that has the 13-bit input that provides the required control signals. Control signals for some example MIPS instructions are shown in Table2.1. Performance The load word instruction is the longest time taking instruction in MIPS as it reads from instruction memory, then reads from register file, performs ALU add operation, reads from data memory, and then writes this data to register file. Each of these except the ALU operation are read and write operations resulting in memory delays. The ALU operation also takes time and the sum of these delays gives an idea on the length of the clock cycle needed. For example, assuming each of the five steps of the load word instruction takes 2 ns, and the multiplexers with zero delays, we have a clock
- 37. 2.2 Processor Architecture 17 Read reg1 Read reg2 Write reg Write data RegWrite ALU ALUOp Instruction Instruction Memory Readaddress [25-21] [20-16] [15-11] [31-0] Data Memory MemWrite MemRead . . 0 1 0 1 Read address Write address Write data Sign data1 Read Read data2 extend Mux Mux 0 1 Read data . . . . RegDst MemToReg ALUSrc 0 1 Mux 4 Add Add PC Shift left 2 . . . PCSrc [15-0] Fig.2.5 Final MIPS single cycle datapath Table 2.1 MIPS control signals for sample instructions Operation RegDest RegWrite ALUSrc ALUOp MemWrite MemRead MemToReg add 1 1 0 010 0 0 0 and 1 1 0 000 0 0 0 lw 0 1 1 010 0 1 1 sw X 0 1 010 1 0 X beq X 0 0 110 0 0 X with 10 ns cycle time and 100 MHz frequency. However, many MIPS instructions require less time, for example, R-type instructions do not use data memory and hence execute in four steps requiring a clock cycle of 8 ns. In reality, accessing external data memory is much slower and hence the single cycle datapath has poor performance. 2.2.2 Multi-cycle Datapath Single cycle datapath is not efficient as it uses the same length clock for all instruc- tions. Our aim in improving the single cycle implementation is to have variable length
- 38. 18 2 The Hardware Table 2.2 MIPS pipelining stages Stage Abbrev. Description Instruction fetch IF Instruction is fetched from memory Instruction decode ID The opcode in instruction is decoded Execute EX Instruction is executed in ALU Memory MEM Memory for read or write operation is accessed Write back WB The read data from memory is written to register file Memory address [15-11] PC . ALU ALUout Read reg1 Read reg2 Write reg Write data 0 1 Sign data1 Read Read data2 extend 4 Shift left 2 . 2 3 A B 0 1 Write Data Register File 0 1 . [25-21] [20-16] 0 1 . . . . Inst/Data . IR MDR 0 1 . . . Fig.2.6 MIPS multi-cycle datapath without the control signals of execution time for each instruction. We will start by dividing the instruction in MIPS into the stages of Table2.2 which each stage taking one clock cycle. The instructions now take multiple cycles, branches and jumps take three cycles, register instructions take four cycles, and only the load word instruction uses all five steps above. Some components of the datapath need to be reused necessitating rearrangement of the hardware. Extra registers are needed now to hold intermediate results between cycles. Instruction and data memory can be merged and we can have a single ALU that will also handle branch and jump instructions simply because the processor cannot use these hardware components simultaneously as these are employed at different cycles. The new multi-cycle datapath without control signals is depicted in Fig.2.6. The newly introduced registers are the instruction register (IR), memory data register (MDR), two registers A and B at the output of the register file, and the ALUout register to hold the value obtained from the ALU to write back to data memory.
- 39. 2.2 Processor Architecture 19 The control unit of a multi-cycle may be realized using a finite state machine (FSM) which consists of a finite number of states and transitions between the states. Informally, an FSM receives inputs in a state and based on its current state and the inputs, it produces output and may change state. We can have each multi-cycle stage represented by a state of the FSM and the control signals needed in that stage will be output by the FSM [1]. Although multi-cycle datapath results in a better performance than the single cycle one, the pipelining described next improves performance better and is the basis of modern processors. 2.2.3 Pipelining Pipelining is commonly employed in real life to improve performance. Consider a washing system that has three machines; a washer (W), a drier (D), and a folder (F). We will assume a person needs to use these machines in sequence as washer, drier, and folder. Let us further assume the washer, the drier, and folder take 20min each. Allocating all of these machines to a person X as shown in Fig.2.7a is not sensible since the washer, for example, can be used by another person Y at the drying stage of person X . Pipelining shown in Fig.2.7b allows the unused machines to be used by the next person and reduces the completion of the laundry process for three persons W D F W D F W D F W D F P1 P1 P2 P3 t=100 minutes t=180 minutes W D F P2 W D F P3 (a) (b) Fig. 2.7 Pipelining example. Three machines in a laundrette are used without pipelining in (a) to result in a total time of 180min. Pipelining reduces the completion time to 100min as shown in (b)
- 40. 20 2 The Hardware to 100min. Note that pipelining does not reduce the time for each person as we still have 60min of processing each, but it reduces the overall completion times for tasks. One important finding of the above example is that we need to clearly specify parts of the task to be performed in sequence to be able to employ pipelining. These stages were washing, drying, and folding for the laundry of each person. In computational terms, the instruction is to be executed in a pipelined processor and we need to separate the execution into a number of distinct phases. The theoretical speedup obtained by a pipelined processor can be determined as follows: • Let k be the total number of pipeline stages, ts is the time of processing at each stage, and n is the total number of tasks presented to the pipeline. • The first instruction takes kts time to complete. • We have an instruction coming out of the pipeline at each cycle for the remaining (n − 1) tasks resulting in a total (n − 1)ts time to finish the remaining tasks. • Total time for (n − 1) tasks is then kts + (n − 1)ts = (k + n − 1)ts • The speedup S obtained is the ratio of the sequential time without a pipeline to the pipeline processing time of n instructions as follows: S = nkts (k + n − 1)ts When n → ∞, S approaches the following value: S = kts ts = k It is possible to have a relatively larger number of stages as seen in some modern processors, by delicately separating intermediate results. We will use MIPS archi- tecture to demonstrate how pipelining can be implemented in a processor. We have five stages: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory (MEM), and Write Back (WB). The instruction lw takes all of the five steps shown in Table2.2 and this is the maximum number of stages we can have. Let us see how a short assembly program segment in MIPS can run with pipelining as shown in Fig.2.8. We simply load words from two consecutive memory locations, add them, and store the result in the third consecutive location. Inthefirstsimpleimplementation,wewillusetemporaryregistersthatwillbeused to buffer the results obtained by a previous instruction. These registers are named IF/ID, ID/EX, EX/MEM, and MEM/WB to show what stages they stand in between as shown in Fig.2.9. This diagram is very similar to the single cycle MIPS with minor modifications. For example, calculation of the branch (beq) instruction can be performed in parallel with the ALU computation, and calculating the next address is performed while fetching the instruction since we have the address information in
- 41. 2.2 Processor Architecture 21 IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB lw $2, 12($8) sw $4, 16($8) lw $3, 14($8) add $5, $9, $12 Fig.2.8 Pipelining in MIPS assembly language program Instruction Instruction Memory Readaddress [31-0] PC . Read reg1 Read reg2 Write reg Write data RegWrite [25-21] [20-16] . Sign data1 Read Read data2 extend . . . 0 1 4 Add PCSrc . [15-0] [20-16] [15-11] ALU ALUOp 0 1 Mux 0 1 RegDst ALUSrc Add Shift left 2 . . Z R Registers Data Memory MemWrite MemRead 0 1 address Write data Read MemToReg data IF/ID ID/EX EX/MEM MEM/WB Fig.2.9 Pipelining in MIPS the first stage. A data value required in a later stage must be forwarded between the pipeline registers. For example, the write register address is carried all through the stages since this is needed in the last stage in the case of store word (sw) instruction. Note that an instruction goes through one stage at each cycle requiring five cycles for a whole instruction. Control Signals Controlsignalsneededfortheinstructionshouldbetransferredalongwiththeinstruc- tionusingthepipelineregisters.Therearedistinctcontrolsignalsneededateachstage and once the instruction passes through a stage, control signals needed for that stage can be abandoned resulting in fewer signals to be propagated as the instruction goes through the stages as shown in Fig.2.10.
- 42. 22 2 The Hardware Control Unit Instruction Instruction Memory Readaddress [31-0] PC . Read reg1 Read reg2 Write reg Write data RegWrite [25-21] [20-16] . Sign data1 Read Read data2 extend . . . 0 1 4 Add PCSrc . [15-0] [20-16] [15-11] ALU ALUOp 0 1 Mux 0 1 RegDst ALUSrc Add Shift left 2 . . Z R Registers Data Memory MemWrite MemRead 0 1 address Write data Read MemToReg data IF/ID ID/EX EX/MEM MEM/WB EX WB MEM MEM WB WB WB Fig.2.10 Pipelining in MIPS with the control signals 2.2.3.1 Hazards The pipelined structure of a processor improves efficiency; however, we have assumed the instructions that are fed to the pipeline stages one after the other are independent. The instructions that follow each other may be dependent meaning the value of a register produced is used in one of the following instructions which cause hazards. Data Hazards Consider the following lines of MIPS code: lw $3, 10($2) First example of a data hazard and $4, $3, $5 add $3, $1, $2 Second example of a data hazard | sw $3, 12($4) The first instruction load word (lw) loads the value in data location ($2)+10 into register 3 which is done at the final and fifth write back (WB) stage. The following instruction however needs the value in register 3 in the third execute (EX) cycle.
- 43. 2.2 Processor Architecture 23 This situation is termed data hazard in a pipelined processor. A possible solution is forwarding the value of $3 which is fetched from memory in the fourth memory (MEM) stage of the load word instruction to the and instruction that needs this value in its second instruction decode (ID) stage. This type of forwarding results in handing over of the register value to two stages back. In order to accomplish correct operation, we need to stall the processor for one cycle between these two instructions. Stalling a processor means stopping its operation for one cycle by resetting the values in the required pipeline registers. In the second example above, the store word (sw) instruction needs the correct value of register 3 at the fourth MEM stage, and hence this value can be forwarded by the add instruction at its second EX stage without stalling the processor. When and where to forward register values can be handled by a forwarding unit which is a circuit which compares the destination register (rd) value at the end of the EX stage (EX/MEM pipeline register) and also at the end of the MEM stage (MEM/WB pipeline register) with the values of the first (rs) and second (rt) register values at the end of the ID stage (IF/ID pipeline register). Whenever a match is found the matched register value is forwarded one or two stages back depending on where the match is found. The comparisons to be performed at the forwarding unit are as follows. A detailed description of the forwarding operation in MIPS is given in [1]. • EX/MEM.rd = ID/EX.rs • EX/MEM.rd = ID/EX.rt • MEM/WB.rd = ID/EX.rs • MEM/WB.rd = ID/EX.rt The MIPS datapath with the forwarding unit is depicted in Fig.2.11. This unit basically compares the destination register (rd) identifier input to MEM stage with the input registers of the EX stage (rs and rt), and the destination register (rd) identifier input to WB stage with the input registers of the EX stage (rs and rt). If a match is found, the rd value is fetched back one or two stages. This carrying back of the rd value is accomplished by selecting the 1 (2 stages back) or 2 (1 stage back) inputs of the multiplexers now present at the input of the ALU. Control Hazards The sequence of instructions may divert to another location after the branch (beq) instruction which compares values in two registers and jumps to the location specified in the instruction if these values are the same. Instructions are fetched in the first stage (IF) and the branch decision is made at the third stage (EX). Consider the following MIPS code segment: beq $1, $2, 16($6) and $4, $3, $5 add $7, $8, $9
- 44. 24 2 The Hardware 0 1 2 0 1 2 Instruction Memory PC . . . . ALU . . Registers Data Memory 0 1 IF/ID ID/EX EX/MEM MEM/WB 1 0 . . . Forwarding Unit . . EX/MEM.rd MEM/WB.rd ID/EX.rs . ID/EX.rt rs rt rd Fig.2.11 MIPS forwarding unit The branch may or may not be taken depending on the values in registers 1 and 2 and this is decided in the EX stage by the ALU operation which would subtract the values in these registers and the zero flag being set at the end of this operation means the instruction address should be changed. If the branch is taken, the and and add instructions which are at stages ID and IF stages, respectively, should be abandoned. Flushing of these stages by resetting the IF/ID and ID/EX pipeline registers is one solution to this problem at the expense of lost CPU cycles. Main solutions to the control hazards for pipelined processors are as follows: • Stalling the Processor: Stop the pipeline until the outcome of the branch operation is known. • Branch Delay Slots: The few instructions that follow the branch instruction are always taken. The compiler or the programmer puts useful instructions or no operations (NOPs) in these slots. For processors with a large number of pipelines, this solution is not convenient. • Branch Prediction: The outcome of the branch instruction is predicted using some heuristics. Static branch prediction can be implemented by always taking the branch or not. An improvement is achieved by the backward taken/forward not taken principle assuming backward offsets are likely loop jumps that will be taken most of the time and forward jumps are rarely taken. Dynamic branch prediction uses current status to decide to take the branch or not.
- 45. 2.2 Processor Architecture 25 2.2.4 Microcontrollers A microcontroller has the processor, memory, and I/O interface in a single chip. Microcontrollers are commonly used for low-power and small-sized embedded applications. A field-programmable gate array (FPGA) is a type of dynamically reconfigurable microcontroller. The application developer can construct the hard- ware required for the real-time system using the FPGA. These processors are com- monly used in communication systems and image processing. Digital signal proces- sors (DSPs) are special purpose microprocessors used for signal processing which requires frequent arithmetic operations on large amounts of data. 2.3 Memory Memory, along with input/output is the main bottleneck that bounds the speed of data transfer in a computer. There is always a need for large and also fast storage and access of data. Large storage is needed in contemporary computers because data is available in unprecedented large amounts now and the size of available data increases in daily basis. On the other hand, if access to memory is not fast enough, we cannot exploit the full capabilities of a high-speed processor. A static random access memory (SRAM) is fast and expensive whereas a dynamic RAM (DRAM) of the same size is more than a magnitude cheaper than SRAM but much slower. An SRAM 1-bit cell consists of two gates, whereas a 1-bit value is stored as a charge on a capacitor in a DRAM. An erasable programmable memory (EPROM) retains program code and data when power is switched off. A hard disk can hold data in the order of terabytes but access to it is very slow although it is the cheapest in memory hierarchy. We need ways to incorporate efficient, fast memory access. 2.3.1 Interface to the Processor The communication medium between the processor and the memory consists of three buses; the address bus to locate the address of data, data bus to transfer data, and control bus for control operations. Typical control signals for a RAM memory are read (RD) and write (WR) lines which enable read and write operations from and to the memory, respectively, as displayed in Fig.2.12. EPROM needs only RD signal since it cannot be written during normal operation. For n-bit address and m-bit data lines, the processor can address 2n memory locations each of which is m-bits long. The high-order bits of the address bus is commonly used to select the memory and the device that is interfaced to the bus. For example, a 10-bit address bus (A9−A0) and an 8-bit data bus allow 1024 memory locations to be addressed. Consider dividing this space into 512 bytes of EPROM and 512 bytes of RAM, we can use the bit A9 as the chip select input to the memories. In this case, data in the address range
- 46. 26 2 The Hardware PROCESSOR EPROM RAM RD WR Address Bus Data Bus . . . / / n m . CS CS _ A9 A9 A0-A8 A0-A8 . Fig.2.12 Memory interface to the processor 0–511 is in EPROM and data in 512–1023 addresses resides in the RAM. Note that the chip select input of the EPROM is active low (CS) to enable it when A9 = 0. Contemporary processors are commonly interfaced in hierarchical bus structures to the memory blocks and to the I/O interfaces. 2.3.2 Caches A cache is a static RAM of small size, placed between the processor and the dynamic RAM to provide fast access to instructions or data. The idea of the cash is to keep the most frequently used data there so that retrieving it from a closer location is faster than transferring it from the DRAM. The principle of temporal locality assumes an accessed address will be accessed by the processor again with high probability in near future as in the case of loops. On the other hand, the spatial locality principle assumes that the neighbor addresses of already accessed locations have a high chance of being accessed which is a valid argument since a program executes sequentially most of the time. Note that a loop also has spatial locality since the loop line sequence is executed repeatedly until the loop terminates. A cache hit is the situation when the cash contains the data we are searching and a cache miss occurs otherwise. Cache performance is measured by the hit rate which is the percentage of cache hits over total memory accesses. The time taken for data to be sent from cache to the processor is the hit time and the time needed to transfer data from the main memory to the cache when miss occurs is the miss penalty. The percentage of misses is the miss rate and based on these parameters, the average memory access time for a computer with a cache is equal to the hit time + (miss rate × miss penalty). Spatial locality principle can be exploited by copying a block of data that contains theneighborlocationsaswellastherequiredlocationtothecache.Withthisprinciple, data is read and written to a cache in blocks each having an index. Assuming a cache has 2k blocks, we need a k-bit long index to address a block. Whenever a memory location addr is addressed, the lower k bits of addr can be used to find the corresponding block in cash. Moreover, we need to check whether the searched address corresponds exactly to the cash address. A block contains a tag value to match the remaining address bits; hence, if the tag value of the block equals to the
- 47. 2.3 Memory 27 Offset Tag Index (4) (6) (2) Index 0 63 1 Valid Tag Data 2 3 0 1 34 = . . . . . . . Mux 0 1 2 3 . . . . . Memory Address Hit Data (1) (4) (8) (8) (8) (8) / 8 / 6 / 4 4:1 Fig.2.13 Cache interface remaining higher order bits of the address, we have a hit. We also have a valid bit for each cache block to indicate there is valid data in the block or it is empty. For example, let us consider a main memory of 12-bit addresses which is divided into 4-byte blocks giving a total of 4 KB memory. Each block can be addressed by 6 bits; therefore, a cash with 6-bit index value and a 4-bit tag value is needed as shown in Fig.2.13. Since each block has 4 bytes, the lower 2 bits of the memory address is used as the offset within the block to access the correct byte. The operation of the cache is shown in pseudocode in Algorithm 2.1. Algorithm 2.1 Cache 1: Upon generation of a memory address addr by the processor 2: if valid bit of the block pointed by the addr index bits = 1 then 3: if tag of addr = tag of cache block then 4: output data from cache at base location of the block + offset of the memory address 5: else get data from external memory and hand it to the processor 6: write data to cache by removing an unused entry 7: end if 8: else get data from external memory and hand it to the processor 9: write data to cache in the empty location 10: end if
- 48. 28 2 The Hardware In reality, we do not have to run an algorithm for every memory access as this pro- cess can be handled by an electronic circuit called the cache controller which consists of an k-bit comparator for a k-bit tag, an and gate, and a 4:1 multiplexer as depicted in Fig.2.13. The cache we have described up to now is called a direct-mapped cache in which every main memory location maps to exactly one cache block location of which can be calculated from the physical memory address. Data transferred from the memory can be written to any unused location in a fully associative cache. This type of cache requires checking all of the locations of the cache in parallel using many comparators and hence is expensive to construct. A set-associative cache is a solution between the direct-mapped cache and the fully associative cache. The cache now consists of groups of blocks called sets and each memory location is mapped to one such set but the location of data within a set is variable. The placement of data in a block is like the fully associative cache allowing data search in smaller cache area. A set-associative set is named k-way associative cache if it has k blocks in a set. Another issue of concern is the selection of the data to be removed from the cache when a new data from the memory is fetched and the cache is full. The data which has stayed in cache longest without being used is selected as the data to be removed in the least recently used (LRU) method. A doubly linked list may be used to keep track of data usage in cache. A newly referenced data is put in front of the list and the data to be removed is taken from the back of the list. Various other policies such as first-in-first-out and last-in-first-out can also be employed to decide on the data to be removed as the first and last accessed blocks, respectively. When a processor writes data to cache, it must also write the data to the main mem- ory for consistency. The write policy determines how this procedure is performed as follows: • Write Through: The cache and the storage are written synchronously. • Write Back: The cache is written first and writing to memory is delayed until the modified data in cache is replaced by another cache block. 2.4 Input/Output Access The processor communicates with the external devices using input and output ports which are basically data buffers to interface to the processor data bus. Input/Output (I/O) devices come in many forms, from keyboards to printers. I/O devices are many orders of magnitude slower compared to the processor and to memory. Disks and networks are the two main I/O systems that communicate frequently with the proces- sor. In order to increase the speed of data transfers from/to I/O devices, parallelism in hardware can be employed. For example, redundant array of inexpensive disk (RAID) systems provides parallel access to a number of hard disks at the same time, and memory can be divided into banks that are accessed in parallel. We will first review common interface to I/O devices in real-time systems and then describe methods of I/O interface in hardware and software in this section.
- 49. 2.4 Input/Output Access 29 SENSOR S & H A/D CONVERTER AMP COMPUTER PHYSICAL ENTITY INPUT PORT Fig.2.14 Input interface of a real-time system 2.4.1 The Input Device Interface Two types of I/O devices are prevalent in real-time systems: sensors and actuators. A sensor is an input device capable of sensing an external physical parameter and producing an electric signal representing this parameter. There are many sensor types such as temperature, humidity, acceleration, and pressure sensors. Typical parameters for a sensor are its operating temperature, error specifications, and range of the values it can sense. The input interface to the processor contains electrical circuitry to convert the sig- nal from a sensor to a form suitable to be processed by the real-time computer. The output from the sensors is commonly small in magnitude in the range of millivolts needing analog signal amplification and then employing an analog-to-digital (A/D) converter which transforms the electrical signal to digital data. Sensors may have the needed converters embedded in them. The structure of a typical input interface employing A/D converter is displayed in Fig.2.14 where an amplifier (AMP) mag- nifies the voltage level obtained from a sensor which would typically be in millivolts range, and a sample and hold (S & H) circuit provides discrete instants of the input signal to the A/D converter so that the converter has a stable input during conversion. The number of bits output by the A/D converter shows the precision of the input signal. A 32-bit A/D converter produces digital data in the range of 0–65535 for a typical 0–5 volt analog input range. A detailed typical interface of an A/D converter to the processor is depicted in Fig.2.15. The processor initiates conversion by the start pulse when it needs to input sensor data. This pulse may be active high or active low, or sometimes just a transition between high and low levels depending on the A/D device characteristics. Generating a pulse by the processor is simply performed by writing a 0, and then 1 and finally 0 to start bit by the output port. A delay after each write is needed to form a pulse. The width of the pulse must be greater than the minimum pulse width needed by the A/D converter and this parameter can be adjusted by the length of the delay, which is commonly done by loading a register with a value and decrementing it until it reaches 0. The output from the converter is available when end-of-conversion (EOC) bit is set. This signal can be connected to the input port of the processor which can be checked by polling this line continuously or it may be used to interrupt the processor.
- 50. 30 2 The Hardware Fig.2.15 A/D interface START EOC DATA INPUT PORT OUTPUT PORT A/D CONVERTER PROCESSOR 2.4.2 The Output Device Interface An actuator works in opposite way to a sensor by converting the electric signal to some form of physical parameter such as sound, heat, or motion. For example, a solenoid is an actuator which produces a magnetic field when current runs through it. In order to start an actuator, the binary output data is first converted to an analog signal by the use of a digital-to-analog (D/A) converter. This signal may be transferred to a convenient form by a signal conditioning circuit to activate an actuator as shown in Fig.2.16. The signal conditioning may include an amplifier and circuitry to limit the value of the analog signal. Its operating temperature and the range of outputs it can produce are the main characteristics of an actuator. 2.4.3 Memory-Mapped and Isolated I/O Communication between the processor and the I/O peripherals can be performed using two fundamental methods: Memory-mapped I/O and isolated I/O. In memory- mapped I/O, the address space is divided into memory locations and I/O peripherals. An I/O unit is accessed just like a physical memory address of memory with I/O units connected to a common bus. The processor sends address of the I/O unit and data over the common bus and an I/O peripheral listening over the bus reacts when D/A CONVERTER SIGNAL CONDITIONING ACT PHYSICAL ACTION COMPUTER OUTPUT PORT Fig.2.16 Output interface of a real-time system
- 51. 2.4 Input/Output Access 31 PROCESSOR RD WR Address Bus Data Bus . . . / / n m MEMORY I/O UNIT IO/M _ CE CE Fig.2.17 Isolated I/O interface to the processor it is addressed as shown in Fig.2.17. The isolated I/O approach provides distinct I/O instructions that may use the same address space as the memory. In this case, the processor should supply a separate control signal that shows whether the intended operation is a memory or an I/O operation. Isolated I/O can be convenient when there are numerous I/O peripherals to be addressed since the same address space can be used for I/O operations. On the other hand, memory-mapped I/O is flexible since all of the instructions used for memory operations can be used for I/O operations. A typical control signal used in isolated I/O is the IO/M signal by Intel line of processors which shows I/O instruction when activated and memory, otherwise, as shown in Fig.2.17. 2.4.4 Software Interface to I/O Having discussed how I/O peripherals can be interfaced to the processor in hardware, we can now review basic software methods to access the I/O units. The processor reads some data from an input device and writes to an output device which are slow. Two main methods of software interface to I/O devices are the polling and interrupt-driven I/O methods. 2.4.4.1 Polling Polling is a basic software interface method to an I/O device in which the processor makes a request to the device and checks continuously whether the request is fulfilled. A typical writing of a file by the processor to the hard drive using this method is shown in Algorithm 2.2. The CPU sends a write request to the disk and the disk raises a control signal when it is ready with the disk head in the right sector, etc. This signal is continuously checked by the processor and when found active the transfer of the file is initiated. An obvious disadvantage of this method is the wasted CPU cycles while waiting for a slow device.
- 52. 32 2 The Hardware Algorithm 2.2 Writing to Disk 1: send write request to disk 2: while disk is not ready do 3: wait 4: end while 5: while NOT end of file do 6: transfer a file block from memory to disk 7: end while 2.4.4.2 Interrupt-Driven I/O An interrupt is initiated by an external source and the processor halts its current processing when this happens. It serves the interrupt and then continues with the task it has stopped processing. This type of operation is analogous to an everyday example in which the doorbell rings while a person in the house is reading a book. The person would place a marker in the book (save current environment), respond to the visitor (serve the interrupt), and then continue with reading. The handling of an interrupt by the processor is similar to the described example; the current running environment which consists of register values, data, file pointers, etc. are saved; the action requested by the interrupt is performed, and then the environment is restored and processing is continued from the position (address) it was stopped. All of this processing is commonly handled by the operating system. Returning to the disk example, the processor makes the write request as before but continues with its other processing until an interrupt by the disk showing it ready is received. The interrupt is then serviced by writing to the disk and when this process is over, the stopped task is continued. An interrupt service routine may or may not be interrupted. All steps of this operation is under the control of the real-time operating system and it is possible to have variations such as having a multi-layered interrupt service routine (ISR) with a high and a low priority sections of code in which the high priority part is served first. A processor typically has an interrupt activation pin (commonly labeled as INT or INT) which may be activated by an external device. This line is checked during every instruction of the processor and when found active, a service routine at a predefined location is activated. Generally, a processor has more than one interrupt pin one of which is designated as the non-maskable interrupt and another that can be disabled by the software called maskable interrupt. Serving an interrupt can be achieved using different approaches. In the interrupt polling method, all of the device interrupt requests are wire-ORed to the processor INT input and when this line is activated, the processor may either read status register of each device over a common bus or more commonly can check an input port to find the source of the interrupt as shown in Fig.2.18. We have three devices connected to the processor and a device requesting service will activate its REQ line and place a 1 on the input port line of the processor it is connected. The processor detects the active port line upon the INT line becoming active as shown in Algorithm 2.3 and goes to the memory location where the ISR for
- 53. 2.4 Input/Output Access 33 PROCESSOR DEVICE 1 DEVICE 2 DEVICE 3 INT REQ1 REQ2 REQ3 INPUT PORT I0 I1 I2 Fig.2.18 Interrupt polling that device is kept. If there are more than one interrupts occurring simultaneously, a priority method may be used. Algorithm 2.3 Polling ISR 1: 2: upon activation of INT 3: input port1 to reg1 4: count ← 0 5: load 1 to reg2 6: while count < 3 do 7: and reg1 with reg2, store result in reg3 8: if reg3 = 0 then 9: goto ISR location base + count 10: exit 11: end if 12: shift reg2 left once 13: count ← count + 1 14: end while 15: A different and a faster approach is the vector interrupt method in which the interrupt source activates the INT input and places the address of its ISR on the input port or data bus of the processor. Note that the task of serving the interrupt is simpler in this case by simply loading the new instruction address from the bus contents by the processor. In a more practical approach, a device requesting service puts its offset from a common interrupt table base resulting in a simpler interface to the processor. For example, 5 input bits will be adequate for 32 devices. 2.4.4.3 Direct Memory Access Devices such as disks and networks operate at faster rates than devices like keyboards and they require transfer of large blocks of data. Direct memory access (DMA)
- 54. 34 2 The Hardware method allows transfer of large blocks of data to such devices at the speed they operate. The DMA controller is an interface processor between the processor and the device and communicates with the processor for data transfers. Typically, the processor provides a starting memory address, number of bytes to be transferred, and the direction of the transfer. The processor will have to refrain from any external operations when buses are busy with the transfer. In cycle stealing DMA mode, the DMA controller takes over the buses for each byte transfer when the buses are idle. Conversely, the buses are exclusively controlled by the DMA controller until the data transfer is completed in the burst mode. 2.4.4.4 Exceptions Exceptions are internal interrupts which are detected by the processor. Illegal instruc- tions, attempting to divide by 0 and arithmetic overflow are the common causes of exceptions. In the most basic form, the program that caused the exception will be stopped and removed from memory by the operating system; however, there are cases when recovery is possible. Commonly, the operating system takes over when an exception is detected with the processor notifying the cause of exception and the instruction that caused it. The MIPS processor has the exception program counter (EPC) which contains the address of the instruction that was being executed when exception occurred. The Cause register has bits that help to identify the cause of the exception. When an interrupt or an exception happens in MIPS, the following are performed: 1. Current program counter is transferred to EPC. 2. The cause of exception is stored in Cause register. 3. Exceptions and interrupts are disabled by modifying the status register. 4. Branch to the exception/interrupt handler address is taken. Upon returning from the handler, the contents of the EPC register is moved to the program counter and interrupts and exceptions are enabled by modifying the status register. 2.4.4.5 Timers A timer is commonly used in a real-time system to measure a time interval. It is loaded with a value corresponding to the interval and at a certain number of clock ticks, the counter is decremented. When the value of the timer reaches zero, an interrupt to the processor is generated to indicate that time has elapsed. A timer can also be configured to count from 0 value upward and when its value reaches the value for the interval, an overflow bit generated by the timer can be used to activate the interrupt line of the processor. This type of timer interrupt is convenient in a real-time system in which the main concern is to have the tasks meet their deadlines. The timers in embedded systems are commonly called watchdog timers and are used to reset or start a recovery process
- 55. Exploring the Variety of Random Documents with Different Content
- 56. Tonedale, his beautiful features illuminated by love and loss, might well have stood for the portrait of a man with a broken spirit. And whilst he was passing through his hour of sadness, Katharine was reading a letter from the Danish botanists, Ejnar and Gerda Ebbesen, Knutty's nephew and niece. They wrote in answer to her letter to say that they had left Denmark and were spending their holidays at a Norwegian farm. They suggested that she might be inclined to bring the botanical parcel to them there. Their aunt was with them, and she was most interested to hear that Miss Frensham had made the acquaintance of her Englishman and his boy. I shall go, Katharine said. There is nothing to prevent me. I shall see the old Dane whom he loves, she said, with a glow of warmth in her heart. In a few days she packed up and went to Norway.
- 57. PART II. IN NORWAY. CHAPTER I.[C] Fröken Knudsgaard pretended to grumble a good deal at having to leave Copenhagen and go to Norway with Gerda and Ejnar. But there was no help for it. It was a time-honoured custom that she spent the whole summer with her nephew and niece. It was true that they saw each other constantly all through the year, for Tante lived opposite the Orstedpark, and the botanists, who lived at Frederiksberg, passed that way every time they went to the Botanic Museum and Library, and would never have neglected to run in for a chat. Sometimes, also, they lunched with her in her cosy little home, where, in the spring, she saw the limes of the Boulevard unfold their tender leaves, and where in summer she watched the sun disappear in the north-west behind the trees. It was indeed a pretty little home, made, so she said, wickedly comfortable by her Clifford's kindness. But these fragments of companionship were not considered enough by the botanists; and summer was the time when they claimed Tante for their own, whether she liked it or not. But of course she liked it; only she felt it to be her duty as a healthy human being to have a permanent grievance. Don't talk to me about giving up my grievances, she said. All right-minded people ought to have them. Rise above them, indeed! Thank you! I don't want to rise above anything! However, after the usual formality of grumbling, Tante was charmed at the prospect of having a change. Ejnar had set his heart on going to the Gudbrandsdal to find a particular kind of shrub which grew only in one district of that great valley. He was a gentle
- 58. fellow, except where his botanical investigations were concerned. But if any one thwarted him over his work, he became quite violent. Tante Knudsgaard used to look at him sometimes when he was angry, and say in her quaint way: Kjaere, one would think you were an anarchist instead of a harmless botanist. One would think you spent your days with dynamite instead of with innocent flowers and mosses, which don't explode. Gerda, also a botanist, and just as clever and distinguished as her husband, wished specially to go up to Tromsö, to find some particular kind of saxifrage, growing nowhere in Europe except on the Tromsdalstind. But Tante struck. No, she said. You don't get me to go up there within the Arctic circle. I've had quite enough of icebergs this spring with my two poor icebergs in England. Poor darlings! I suppose they have reached America by now. I ought to be hearing soon. I cannot imagine why you made them go so far, Gerda said. When people are in trouble they must always go a long way, said Tante. Even if they come back the next moment. You might have sent them to Tromsö, Gerda remarked, with a grim smile. That is almost as far. And then we could all have gone and found the saxifrage. You would have been willing enough to go if you had had your Englishman with you. Perhaps; who knows? replied Tante. The human heart is a wayward thing. I think you have never heard me say otherwise. But why not go to Tromsö by yourself, dear one? You won't feel at all lonely if you have the companionship of the saxifrage. You won't miss Ejnar and me in the least. You won't want to come back the next moment after you have left us. Oh, no! You won't miss us. No, answered Gerda, giving her a hug. But you would miss me. And Ejnar would be wretched if he hadn't me to quarrel with. Yes, you must have your quarrels, said Tante gravely. All well- conducted botanists would go to perdition without two or three quarrels a-week. You must stay, Gerda, if only for the sake of science. Only, give in without a mortal battle this time, and let us go
- 59. peacefully to the Gudbrandsdal. Ejnar has the dynamite-look on his face. He has set his heart on that shrub. Heaven and St Olaf help us! We must get it!—even if we have to scale mountains. Imagine me scaling mountains, dear one. Have pity on me, and come and help! Gerda gave way; a mortal battle was avoided, the dynamite-look disappeared from Ejnar's gentle face, and all three started off for Norway in good spirits and admirable tempers. Ejnar was a tall man, thin, and dark for a Dane. He looked rather 'comatose,' as Tante called him, except when his botanical emotions were aroused. Then he sprang into life and became an inspired being, with all the sublime beauty of intelligence on his face. He only cared for botany, Gerda, and Tante Knudsgaard. He did not positively dislike music, and did not always go out of the room when Gerda sang. He was a silent fellow, and scarcely ever laughed, except over his work, and then sometimes he would give forth peals of hearty laughter most refreshing to hear and quite boyish. That was when he had done some satisfactory bit of difficult classification. Gerda, being musical as well as botanical, was rather more human. She was of middle height, slight, and wonderfully fair, with an abundance of fair hair, and a pair of glacier-blue eyes. She sang gloriously in a wild, untrained manner which thrilled through every one except Ejnar. He had, however, the greatest and most generous admiration of her knowledge as a botanist, and was most particular that every paper with which she had helped him, should bear her name as well as his. In fact, in his way he loved her dearly. Their quarrels were entirely scientific, never human. In their simple way they led an almost ideal life, for they were free to work in an untrammelled fashion at the subjects they loved, Ejnar holding no official position in connection with his work, but being sleeping partner in his brother's glove- factory in Christianhavn. They were very happy together, and although Gerda had a restless theory that it was ridiculous to be always together, she had been utterly miserable on the one occasion when she had gone off alone, and had returned the next day. Tante, remembering this, teased her continually, of course; and when the good ship brought them to Christiania, she said to her:
- 60. Are you quite sure you are not wanting to go off to Tromsö alone? You could come back the next minute, you know, quite easily. Nå, answered Gerda gaily. I prefer to stay and be teased! They saw the sights of Christiania, spending most of the time in the Botanical Department of the University; and then took the train up to the Gudbrandsdal, the largest and most fertile valley in Norway. They had engaged rooms for themselves at a large Gaard (farmhouse) owned by rich peasants of noble lineage, who in the summer months took a few guests into their spacious dwelling- place. The Gaard had a splendid situation, lying on the mountain- side, about two thousand feet above sea-level, and commanding a far-stretching view of the great valley, which was spread out generously below, dotted with hundreds of farms, and with two shining rivers flowing on separately, meeting each other, and then passing on together. Looking down on all those homesteads, one was reminded all the time of the words of the Norwegian poet, who sings of Norway, the land of a thousand homes. Red Gaards, being new buildings added to the original family-home of many generations: bright red, standing out boldly and picturesquely against the grain fields and the green of the firs and birches. Dark- brown, almost black Gaards, burnt to their deep dye by the ever- working hand of Time. Fine old Gaards, not built of puny slices of wood with which builders content themselves in these mean-spirited days; but fashioned of entire tree-trunks, grand old fellows of the giant forests of the past. Dense masses of firs and birches: down in the valley and advancing boldly up the mountain-sides, and lining the deep gorges of the side-valleys as well, and pressing on to a quite unreasonable height, from a conventional point of view, firs and birches contending all the time as to which should climb the higher. Waterfalls here and there, catching the sunlight and sending forth iridescent jewels of rarest worth. Hundreds of grass-grown roofs, some with flowers and some even with a fir or two amidst the grass. White bell-towers to every storehouse, with the bell to summon all the labourers to food and rest. Countless fields of grain of every kind: some of it cut and fixed on sticks at regular intervals,
- 61. so that a regiment would seem to be waiting the word of command: ready and immovable: a peaceful region of warfare. And a warfare in reality, too, a hard nature being the enemy. Then those wonderful rivers: one of them coming straight from a glacier and therefore unmistakable, even though the changing clouds might give to it varying shades of colour. Grey and glacier, blue and glacier, rose and glacier, black and glacier, white and glacier, golden and glacier. And the other river, not less beautiful because less complex. And the two together winding through the valley: now hidden from sight, now coming into view again, now glistening in the far distance, and now disappearing finally—no—one more glimpse if one strains the eye—one more greeting, and then, farewell—they have gone their way! And the snow mountains—not very near, and not very snowy just now; but, for all that, the glory of the country, the very desire of one's heart, the shrine of one's secret and mysterious longings. CHAPTER II. Both the botanists and Tante were delighted with the place. Tante, who adored limitless space, had not quite liked the idea of coming to a valley. You know I have always hated restraints of any kind, dear ones, she said. And even at the age of seventy, I desire to continue in the straight path of blessed uncontrol. Valleys make me shudder a little —like conventions! Bah! But even she was content when she saw the immense proportions of her prison. Well, she said, with a twinkle in her eye, there is space and freedom enough for me, for a little while. All is well with me, dear ones. Go and find your shrubs and be happy. It is true that you have brought your poor stout relation to a place on the mountain-side where she can neither go up nor down. Nothing could have been more cruel. But no matter. She will look at the view and try to feel chastened by patience and all the other dull virtues. And she will go
- 62. on knitting socks for the dear English soldiers. They will never get them, of course. Still, she will do her best for them, hoping that King Red Tape will allow them to be delivered. Yes, dear ones, hasten to your shrubs and have some stimulating quarrels over them. Tante is content for a minute or two. And she really was happy, and deeply interested in the owners of the Gaard, rich landowners, Bönder, aristocrats of Norway, direct descendants of kings and chieftains—Vikinger, in fact; proud and reserved: proud of their noble lineage, and reserved of feeling and in manner, and yet, when tactfully approached, capable of the greatest kindness and appreciative understanding: dignified in behaviour, and refined in form and feature, bearing on them, indeed, the royal seal of good birth and good breeding. The Solli family was one of the oldest and noblest in the valley, and had the most important and most highly decorated and carved pew in the old brown church. There were three girls: stately Ragnhild, lovely Ingeborg, and gentle little Helga, the pet of the family. And there were two sons, Karl and Jens. Karl, being the elder, would in time inherit the Gaard, paying his brothers and sisters a share, and giving to his father and mother mysterious dues called Föderaad. But as Solli and his wife were strong and active, and Karl was not even betrothed, there was no occasion for the older people to retire; and meanwhile an older couple still, the grandparents, were eking out their lives in the comfortable old black dower-house in the court of the Gaard. Grandmother (Bedstemor) had never wanted to retire, and bore on her face a settled look of disappointment which had been accentuated by the coming and going of twenty years. Grandfather (Bedstefar) had been ailing for many years. He lay in the big bedroom of the black house, and waited for the caressing hand of Death. Solli's wife, whose Christian name was Inga, and who in accordance with custom was called Mor (mother) Inga, was, in her stately way, greatly attracted to the old Danish lady, and told her many interesting details about the Gaard. Tante had such perfect tact, and was such a comfortable easy creature to be with, that she found herself soon en rapport with the family. A glass of gooseberry-
- 63. wine, followed on the next day by some corn-brandy, seemed to indicate that a delightful acquaintanceship was ripening; and when Mor Inga took her to the Stabur (the storehouse), that most sacred precinct of every self-respecting Norwegian Gaard, and showed her the treasures and mysteries of Norwegian housekeeping, every one felt that Fröken Knudsgaard had arrived. Even the disagreeable old magistrate (Sorenskriver)[D] from S——, one of the eight or ten guests, admitted that. She has seen the Stabur, he said, with a grim smile, and he actually forgot to help himself first to cheese, but passed her a few delicate shavings; a sure sign from him of even passing respect. After an introduction to the Stabur, any other honour on earth was easy of attainment; and no one was surprised to learn that Ragnhild was going to put up her loom and teach the Danish lady to weave. And Mor Inga fetched great-grandmother's old painted spinning-wheel from the top room of the Stabur and put it in the little balcony which overlooked the courtyard; and she brought some fresh wool from the wool-room—another sacred spot—and sent for old Kari, who was especially clever at carding the wool. And Tante sat and knitted, whilst old Kari carded the wool and Mor Inga span. This was Tante's first introduction to old Kari, eighty years old, and full of fairy lore. Ah, whispered Mor Inga to Tante, Kari can tell thee many stories of the Gudbrandsdal if she likes. But it must be in secret, when there is no young person near to laugh and disbelieve. One day thou shalt give her a little coffee in a packet—all for herself—and then thou wilt hear all sorts of things. But to-day Kari only carded the wool, smiling amusedly at being in the company of the big Danish lady, who spoke to her so kindly and treated her as though she were a lady herself and not an old parish-woman who had no home of her own. Ja, ja, that was very nice, and Kari scratched her head, and smiled more and more, until even the furrows on her grim old face were filled up with smiles, and her eyes seemed almost young and very bright. Ah, said Tante, with a friendly nod, I know some one who has been very pretty. Oh, I have eyes—sharp, sharp eyes. I can see!
- 64. And Mor Inga laughed and said: Kari was beautiful, and she could dance too. They say that in the old days no one could dance the spring-dance like Kari. Nei, nei! said Kari, smiling more and more still. And her thoughts wandered back to her Ole—dead these twenty years and more. He had always said that no one could dance like Kari. All this kept Fröken Knudsgaard busy; and indeed her distractions increased as the days went on. Sometimes she sat in the balcony which looked over the splendid view, and, seized by a sudden enthusiasm for nature, watched the ever-changing colours of the rivers, and the shadows on the hillsides, and listened to the music of the waterfall down below in the Vinstra gorge. But she did not pretend to be able to live on Nature's great wonders alone. She was delightfully candid about it. No, my dear ones, she said to Ejnar and Gerda, I am the wicked product of a beautifully wicked world. I need my fellow- sinners. It would never have contented me to lie flat on my stomach looking for flowers and grasses, and so forth. Nor would it have been desirable for me. I should never have got up! Nevertheless, when her botanists came back from their wanderings, with their green tin wallets full of mystic treasures unguessed at by the uninitiated, she was eagerness itself to know whether they had had good hunting. And when Gerda said: Wicked old Tante, you know you are interested in these things, she answered gaily: No, no; but I have accepted my fate. Since my best beloved ones are all scientific sillies, I have to appear to be interested in what they do. She felt it to be her duty to secure, on behalf of science, a big study for her botanists, and Mor Inga let her have a vast room in one of the out-buildings. They must have plenty of room to quarrel in, she explained to Mor Inga. Everything goes so much more easily if there is generous space. And, she added to herself, it is my experience that scientific people are safer caged up in their laboratories and studies. You
- 65. know they are all right then. When they are wandering about, they might get lost; but when they are shut up, they are comparatively safe, barring brain fever and explosions, of course. So she caged her botanists, and felt herself free to amuse herself with human nature whilst they were immersed in the study of nature. Well, then, good-bye for the moment, she said, when she shut them up for the first time. I will now go and have a few disagreeable words with that horrid Sorenskriver, who dislikes my belovèd English. I will go and sit quite near him, and knit my stockings for the dear English soldiers. That annoys him beyond everything. What a delight to see his irritation! Poor Sorenskriver! He suffers, and I enjoy. That is the way in life, and very amusing too. My poor dear ones, what a pity you cannot have a little fun too. Well, I suppose you do get it through your microscopes. But they had a great deal of fun in a quiet way. No one could be long with Tante without catching a little of her gaiety; and even Ejnar was heard to laugh sometimes over matters which had nothing to do with his work. And Gerda left her cage and went singing in the birchwoods above the Gaard, and along the mountain paths. She was content, too, and had forgotten about the saxifrage. And Tante attempted short little strolls along the easiest road, and always stopped by the black hay-barn near the group of mountain-ashes, which rejoiced her eyes. Here she sat down and took out her opera- glasses, really to observe the clouds, though she pretended always to be looking at the numberless Gaards and barns which covered the hillsides and mountain-slopes. But once she forgot her rôle of indifference to nature, and cried enthusiastically to Gerda: By St Olaf! I never saw such soft clouds in my life, nor such colours! And just look at the reflection in the rivers, Gerda. Sapristi, how beautiful! What is this I hear? cried Gerda. Tante admiring nature! Oh, that's a big Gaard—that yonder, said Tante, correcting herself with a twinkle in her eye. I wonder what the name is, and how many cotters they have, and how many children, how many cows up at the Saeter, how many goats, how many cheeses they
- 66. make, how many sheep they have; whether Bedstefar and Bedstemor are alive, and whether they have as comfortable quarters as our Bedstefar and Bedstemor. Ah, and that reminds me that I am drinking coffee with Bedstemor this afternoon. Help me up, Gerda, and don't stand staring at that cloud as though you had never seen one in your life before. So Tante drank coffee with picturesque old Bedstemor in the old dower-house of the Gaard. The principal dwelling-place of the Gaard had been considerably added to in modern times. The old part was in the middle, and new wings had been built on either side, a whole new storey with a slate roof added, and a new balcony and porch. So that the Gaard proper, in which Mor Inga reigned, was a curious mixture of the old and the new: the new part being painted pink, and the old part keeping its ancient glory intact. But Bedstemor's house was untouched by modern hands; in fact, all the houses which formed part of the settlement were just as they had been for two or three hundred years. Bedstemor's house was the largest of them all. There were about eight or nine others, all black or dark brown, all with their roofs covered with long grass, amongst which grew poppies, corn- flowers, and forget-me-nots. They were grouped together round the courtyard, as quaint and picturesque a sight as one might see anywhere. The Stabur stood somewhat apart from the other buildings, and was raised above the ground by tree-trunks which looked like elephants' legs. The Stabur had a conceited, self- contained look after the manner of all true Staburs. It seemed to be saying all the time, Behold me, I am the Stabur! The possession of a white bell-tower on its grass-grown roof, and of an old carved door, encouraged its self-importance, and gave it an air of distinction not enjoyed by the other houses. Still, they had their tall white chimneys; and it is obvious that one cannot have everything in life. And some of them also had a more picturesque situation than the Stabur: creeping up the hill, indeed, as though they were thinking of climbing up into the woods, but had stopped to rest by a mountain- ash, or by a graceful birch; whilst others, mounting higher, came to a standstill at last and were used for storing wood. Then there were
- 67. hay-barns of various sizes and shapes, the most characteristic being those with sloping bridges leading up to the top floor. And last, not least, there was the great cowhouse, forsaken now except for five or six cows which had not gone up to the Saeter. And Ingaros, the most beautiful cow of all, christened after Mor Inga, was sulking partly because she had not gone up to the Saeter, but chiefly because she, the belle of the Gaard and the authorised leader of the herd, had been deprived of her noble collar and bell. Some wretched upstart of a creature was wearing it, so that she might be sure to come home to her calves. Ingaros had Tante's profound sympathy. She visited her in the cowhouse at milking-time, and exchanged a few understanding greetings with her. Old Kari was milking her and singing a soothing little song, something about a saeter-girl who lost all her cows, and she danced and they all came back again, and then she sang and sang till they ran away again! Tante stood and listened delightedly to the clear, sweet voice of the old woman. Ja, ja, Kari, she said, I believe I have some coffee-berries in my pocket. Such a song deserves a good cup of coffee. Stakkar![E] said Kari, smiling with delight. Thou art a kind one, although thou art not Norwegian. Thou shalt hear all the tunes I know. CHAPTER III. It was a hot afternoon. Ejnar and Gerda had had a quarrel over Salix. Ejnar's face wore the dynamite expression, and Gerda was white with anger. Her glacier eyes looked like the eyes of a polar bear, and she was moving her head to and fro in a manner which always meant rebellion. On these occasions she longed for a divorce. Give me a divorce at once! she cried tragically both to Ejnar and Tante. My dear one, remarked Tante soothingly, I don't keep divorces ready in my pocket; and you know Ejnar never has even a handkerchief in his pocket. You should have a divorce at once if we
- 68. had one handy. Be reasonable. Have I ever denied you anything in this world? Of course you should have one instantly. Ejnar was silent; but his expression was quite enough to blow up all the royal palaces and personages in the universe. Tante herself did not feel too amiable that afternoon. She had had an angry discussion with the Sorenskriver and another man, a Norwegian fur- merchant, about England; and she was shocked to hear them say things against the English which she knew to be not only untrue, but venomously unjust. Why, she said, flourishing her knitting-needles, even the greatest criminal has some redeeming features. And as with criminals, so with countries. But you leave England no virtues: not one. The men shrugged their shoulders. It was so obvious to them that England had no virtues. It was so obvious to them that they, who had never been to that detestable country, knew far more about the character of the people than this ridiculous old Danish woman who had spent about twenty years amongst the barbarians. Tante was ruffled. And Ejnar, being in a disagreeable mood, had chimed in too against this much-abused nation. Ja, he said in his quiet way, it is a barbarous country, this England. I know nothing about politics, thank heaven, nothing about wars and so forth. But this I can tell you: that England is the only country which refused to exchange botanical specimens with our Botanical Museum. The barbarian director wrote a rude letter. I've told you a dozen times, Ejnar, that it was all probably owing to Red Tape, replied Tante angrily. She could have shaken Ejnar. And pray what is this Red Tape? asked the Sorenskriver contemptuously. It is an invisible thread which no one has been able to cut, so far, said Tante. Every one knows it is there and deplores its presence. If it could once be cut, it would shrivel away, and one of England's dangers would be gone. Then you admit she has dangers? asked the fur-merchant, triumphantly rubbing his hands.
- 69. Ja, ja, said Tante Knudsgaard; but the greatest of them is Red Tape. She suffers from it in everything—both in war and in peace. But she will overcome all her difficulties and emerge. Never, never! said the Sorenskriver and fur-merchant joyfully together. Her day is gone. Then her twilight and her night will be like the glorious midnight sunlight of your north, said Tante, turning to the fur-merchant who came from the north. Pyt! said the fur-merchant scornfully, and went away. Sniksnak! said the Sorenskriver impatiently. Tante made no reply, but went on knitting; and in a few minutes finished a sock, which she spread on her knee, and then added it to a great pile beside her on the seat of the courtyard verandah, where every one was awaiting the arrival of the letters. That makes twelve pairs for those brave English soldiers, she said, half to herself. And the Sorenskriver moved nearer to the horrid spectacle, attracted to the spot against his own wishes. Tante laughed silently; but, all the same, she was ruffled. Every one was more or less cross. Solli was worried about the crops, for there had been no rain for a long time, and both corn and potatoes threatened to fail. Also, there was a shortage of water, and that made him anxious about fire. Also, Bedstefar was more ailing than usual, and the doctor had been sent for. Bedstemor came over from her house, sat near Tante, and grumbled a little because Bedstefar was so obstinate about the doctor. But she cheered up when a Swedish lady, an artist, one of the guests, praised her quaint, old-fashioned head-gear, and wanted to take a photograph of her pretty old face. Ah, said Bedstemor, many people have wanted to take a picture of me. And then every one laughed, and said: Ja, Bedstemor, we can well believe it! That seemed to put every one in better spirits again; and soon beautiful Ragnhild came out of the kitchen with a bundle of letters and papers, and was the centre of an eager circle. Ejnar stood apart, near the Stabur, not being concerned with human affairs. But
- 70. Ragnhild had a letter even for him, and took it to him herself. She and all the peasants had a great respect for scholarship. There is a letter for the professor. Will he care to have it? she said gently. She handed it to him in her own charming way, and even Ejnar was pleased; for Ragnhild was the object of great admiration amongst the men, although she kept them at a distance. And all the women, too, admired her, and were glad when she came amongst them. Tante gave her a good hug when she dropped several letters and papers into her lap, and got in return an affectionate pat of approval on the back. Thou hast more than thy share of letters to-day, she said. I shall give thee none to-morrow. I don't want any more! cried Tante, who had just glanced at one of her letters. Only think, Ragnhild, some dear friends of mine are coming here. I should like to dance the Halling dance. Help me up, kjaere. I want to dance over to the Botaniker. No use calling to him. He never hears human sounds. Then gaily the pretty girl and the old Danish woman went arm-in- arm to the Stabur, near which Ejnar and Gerda were standing, their heads buried in a letter. They looked up when they saw her, and cried: Such news! such news! It has come from America. She will bring it to us at once. We have only to write and say where we are. And I, too, have something coming from America, cried Tante. My Clifford and his boy! Only think, Tante, that valuable botanical parcel at last! cried Gerda wildly. Only think, my poor icebergs home again! cried Tante, putting her arm round each of them. What could be more delightful! Your dried-up flowers and my frozen-up human beings! Let us all be friends again and have some aqua vitæ. I feel at peace even with that wretched old magistrate! Oh, Gerda, said Ejnar, what joys are before us! Just think of it —the Mariposa lilies and the Romney poppy at last!
- 71. When they had all calmed down a little, Tante read Katharine Frensham's letter, and learned that she wished to bring the botanical parcel as soon as she knew whether Herr and Frue Ebbesen could receive her. She had heard from Professor Thornton that they were perhaps going to Norway. If they had already gone, she could just as easily come there. She added: It is curious that I, who knew nothing about Professor Thornton a few weeks ago, should all the time have been in communication with the nephew and niece of his dear Danish friend. Ja, said Tante, waves—waves—wireless telegraphy, as always. There was a sentence in Clifford's letter which struck Tante as being a remarkable thing for him to have written. I have become acquainted with a Miss Frensham, he wrote, to whom I have given a letter of introduction to you—though she will scarcely need it, being, as she is, on a botanical errand to Ejnar and Gerda, and therefore to you. But I desired not to be left out in the cold where she is concerned. Well, reflected Tante, that is a remarkable thing for an iceberg to say. And she read the sentence several times in order to make sure that she had caught the meaning. The rest of the letter ran thus:— Dear Old Knutty,—Alan and I are coming back, and we shall come and find you somewhere and somehow. We have not been happy together. There is a shadow between us—that shadow which I always feared,—and he has something against me in his young heart which makes easy and close companionship impossible. We have both suffered. There was a man of my own age with his son, a boy of Alan's age, on board. I used to look at them with hungry eyes. They had such a good understanding between them; there were no shadows there. He was a great traveller, an ornithologist. And his boy thought he was the finest hero on earth, and worshipped him. I would not wish that; but I would only ask that Alan should believe in me again, as in the old days before—before Marianne's death. It will be good to hear your voice again, even if you do scold me for
- 72. throwing over Japan. But, under present conditions, it is waste of money and waste of heart-fibre. Alan will be happier without me. Perhaps you won't scold me after all, Knutty. You are such a wise old Knutty; and I still think you were wise to send us in spite of everything. Of course I was wise to send you, my poor Clifford, Knutty said, as she read the letter over and over again in the quiet of her beautiful big bedroom, with its lovely views of the valley, the wood, and the grass-roofed houses. Of course I was wise to send you— even if you came back the next moment. That doesn't matter. It is the starting-off which counts. My poor boy, I won't scold you. My good, gentle-hearted Clifford. You ought to have had a heart as tough as Knutty's. You would not have wanted to gnaw it then; no temptation then. My poor boy! She rubbed two or three tears away from her cheeks, and tapped the floor impatiently with her foot. Bah! she said; that Marianne, I never could bear her! And then something prompted her to turn once more to his letter, and she read the words, But I desired not to be left out in the cold where she is concerned. A faint smile came over Knutty's face. It disappeared, came again, stayed, deepened and deepened. By St Olaf, I believe I see daylight! she cried. CHAPTER IV. So Katharine started off to Norway, taking the boat from the London Docks. By a curious chance Mrs Stanhope was on board too, and the presence of this bigot, Marianne's friend, Clifford Thornton's enemy, stirred Katharine to her depths. They had bowed stiffly, and then had contented themselves with glaring at each other. It was a rough passage, and they were the only two women who did not retreat to their cabins. They sat side by side, in silence, in a sheltered part of the boat, having no choice to go elsewhere.
- 73. But although no words were spoken between them, an active warfare went on unceasingly: encounter after encounter, and the victory to neither. The voyage came to an end, Christiania was reached, and the two women went, each her own way; each thankful to be free of the other. But Mrs Stanhope, without knowing it, had sown fresh seeds of love and protection in Katharine's heart for Clifford Thornton. More than ever her thoughts turned to him. More than ever she found herself weaving a fancy fabric of happiness and love. Then she rent it in pieces and began it over again. She had to begin it again each time she had destroyed it, and each time some new beauty was added. And thus busy with her work of destroying and restoring, the train bore her past beautiful Lake Mjösen, the biggest lake in Norway, and into the Gudbrandsdal, where she at once made the acquaintance of the river Laagen, the glacier river which Knutty, Ejnar, and Gerda were learning to love in their upland Gaard. She thought of them as old friends. It seemed to be quite natural that she was coming to them. She longed to see Knutty. She knew that she would not have one minute's shyness with Clifford's old Dane. But she had not any idea how eagerly she was awaited. Tante was most impatient to see her, and kept on murmuring to herself, By St Olaf, I see daylight through a leper's squint! And when asked to explain these mysterious words, she only said: Keep to your own department, botanists. Don't interfere with the section marked human nature. And Ejnar and Gerda were wild with delight, and even spoke soft words together about Salix. Of course they only looked upon Katharine as the bringer of the parcel: having no value in herself, being, as it were, only a base instrument. It made no difference to them whether she was fair or dark, tall or short, agreeable or disagreeable, electric or soporific, with an attractive aura or an antipathetic personality. What on earth does it matter so long as she brings the parcel safely? said Ejnar, in answer to Tante's repeated, I wonder
- 74. whether. That sort of thing matters very much to people who are alive, replied Tante sternly. Of course to people who are prematurely dead, like botanists, nothing matters except the parcel. My belovèd Ejnar, I am delighted to see you so happy; but I must entreat you not to sing. You are frightening the horse; he looked round then to see whether an ostrich was driving him. And you observe we are on the most dangerous part of the cliff. Don't let us have an accident until we have embraced the parcel and received the bringer of it with indulgence.—And do remember to thank her, Gerda. And don't let Ejnar ask for the parcel the minute he sees her. Let us show the English barbarian woman that we know how to behave.—Ah, here we are on the level. Now, Ejnar, you can sing as much as you please. What a curious voice—not human! The sort of voice you would expect a decaying plant to have. But how happy you must be! You don't often sing, I think. Ja, I am very happy, said Ejnar, smiling radiantly. I only sang once before in my life, after Gerda accepted me, when I was alone in the woods. A good thing she didn't hear you, or else she might have changed her mind, remarked Tante. Dear ones, dear ones, said Gerda, here is the train. Oh, Ejnar, how I hope we shall not quarrel over the parcel. I know we shall, though. They hurried out of the carriage, all of them in a state of great excitement, and Tante, very red and hot, but her face beaming with kindness and pleasant expectancy. She looked up and saw Katharine standing at the window. That is Miss Frensham, she said. How do you know? said Gerda and Ejnar. You've never seen her. Instinct, stupid ones! answered Knutty breathlessly. Of course it is Miss Frensham. Come along now, and remember to say nothing about the parcel, Ejnar. Then she pressed forward, and just as Katharine was stepping out of the train, she put out her hand and said: Welcome, Miss
- 75. Frensham. I am Fröken Knudsgaard, and these are my botanists— your friends. We are so glad to see you. Ja, ja! cried Ejnar and Gerda. And I to see you, Katharine answered. It is like coming to see old friends. And I have the parcel quite safely here in my little travelling-box. I put it there so that there might not be one moment's delay. For, of course, you must be feeling impatient. I am sure I should. With those simple but magic words Katharine immediately won her way into the botanical hearts of the botanists; and Knutty, looking at her dear frank face and delightful appearance, felt a glow of pleasure such as she had not been conscious of for many long years. Then the clever Norwegian ponies, those yellow little fellows, full of mountain-wisdom and resource, drew the carriage slowly up the winding road which led to the Solli Gaard. Like all true Norwegians, they did exactly what they wished: rested when they wished, and went on when they wished: went very near the edge when they felt so inclined, or paused to drink of the brook running into the hollow tree-trunk placed there for their benefit. As Knutty said, they allowed plenty of time to look at the graceful birches which crept up from the valley, lined the hillside, were shimmering in the sunlight, trembling in the breezes, and sending out their own delicious fragrance laden with subtle sweetness. Ja, ja, said Knutty, the birches are at their best to-day, to welcome the Englishwoman to beautiful Norway! CHAPTER V. The contents of the parcel exceeded the botanists' wildest expectations. They were radiantly happy over it, and delighted with Katharine. She had stamped herself on their minds as a woman of sense, who had understood that the parcel had been the entity and herself the non-entity.
- 76. Obviously a person of discernment, Ejnar remarked several times to Tante, who laughed secretly when she observed that the impersonal botanist was beginning to show distinct signs of human appreciation as well. He even left his study once or twice, and came to sit with the ladies on the balcony, bringing his long pipe with him. He did not speak much, of course, and when he did he never touched on human affairs. But Katharine had seen these flowers, and in an unscientific but vivid way she could tell him a little about them, and a great deal about the botanists who had sent the precious gift. Gerda and he listened with rapt attention while she described to them the Colorado botanists' herbarium. She told them that they were rich, but that they did not care for a grand house. They lived in a small 'frame house,' and had built a princely herbarium, which, together with their wonderful botanic garden, was the chief feature of their property. They do not care about human grandeur, Katharine said, in conclusion. That is as it ought to be, exclaimed Ejnar and Gerda approvingly. All the same, remarked Tante, I would prefer to inhabit that herbarium, and put the stupid dried plants in the cottage. But then I know I have a base human soul. Always have had—isn't it so, dear ones? Yes, yes, said Ejnar and Gerda. And you've always liked comfort. Yes, replied Tante—good English comfort. Give me good English comfort and mange tak![F] Let me be base and comfortable, like my darling, much-abused English people. Are you really so fond of them, Fröken Knudsgaard? Katharine said warmly; for every one feels a glow of pleasure at hearing one's country praised in a foreign land. Ja, I love them, Knutty replied, smiling at her; and I spend half my time in fighting their battles. Even here I have several deadly conflicts every day with a Norwegian magistrate and a fur-merchant from the north. But now you've come, you can defend your own
- 77. country much better than I can. But I shall always be delighted to help. Ja, she loves them, said Gerda. And that Englishman of hers is the only person for whom she cares in the whole world. Ejnar and I have been jealous of that Englishman ever since I can remember. I have told you hundreds of times that it is absurd to be jealous of an iceberg, Knutty said, with a twinkle in her eye.—You know, Miss Frensham, they are speaking of my dear Clifford Thornton, whom I've known and loved ever since he was seven years old. There is no one like him on earth—— Ak, said Gerda, if she begins to talk to you about her Englishman, all is lost. Don't encourage her, Fröken. Take my advice. Tell us something more about the Colorado botanists and their garden. Moreover, the Englishman is soon coming himself. That will make her happy. He is coming, Katharine said eagerly, turning to Tante; he is coming here? Yes, said Tante, nodding at her. And the quick old Dane glanced at her and saw how the light of a great happiness had come into her eyes. Yes, Tante said; he has given up the journey to Japan, and I suppose he and his boy will be here in a week or so. In a week or so? Katharine repeated, as though she could scarcely believe it. Then, with a gaiety which delighted them all, she turned impulsively to the botanists and continued telling them all the details she could remember of that wonderful garden and the interesting collection of cactuses, and the different kinds of pepper-trees. And Gerda and Ejnar, entranced, kept on saying: Ja, and what more? And Tante kept on thinking: Surely I see daylight! But, good heavens, what can we do to get rid of these botanists? Wretched creatures! Why don't they go back to their study provided so thoughtfully by me? And what a darling she is, and how delightful to look upon, and with a fine temperament. Simple and easy as a child. Built on a big scale, mind and body. Like the Gaard itself. Ja, ja. And then to think of that
- 78. Marianne! Ak, what a brute I am! Never mind. Let me remain a brute! Oh, those botanists! If only they would go to their study and quarrel about the Mariposa lily, or cactuses, or salix, or something. And just look at Ejnar! He is becoming human. He is leaving the vegetable and entering the animal kingdom. By St Olaf, he has picked up her handkerchief! Ah, and here is Ragnhild coming to the Stabur to ring the bell for dinner. Nå, after dinner, we can have a talk about my Clifford. So after dinner Tante took entire possession of Katharine, but much against the botanists' wishes. And Gerda said privately: Well, at least, don't bore her by talking about your Englishman all the time. You yourself saw how glad she was to get away from a subject which could not possibly interest her, and to continue to talk to us about Arizona and Colorado. In answer Tante had a mysterious attack of laughter, and gave Gerda a specially affectionate hug; and, having assured her that she would use moderation, walked off with Katharine to show her, so she said, the principal sights of the Gaard, and to introduce her to some of her intimate friends, all of whom were interested in the arrival of the Englishwoman, the first English person they had ever seen. Knutty was proud that Katharine had such a fine appearance and such a charming way with every one. The Sollis, Johann himself, and Mor Inga, in their grave, reserved fashion, were kindly to her; and Karl, a most unemotional creature, was quite excited when she spoke some German to him. Bedstemor arrived on the scene, having heard that an English guest had come to the Gaard; and when Katharine was presented to her, she greeted her with great dignity, and said to Tante: She is nice looking, this Englishwoman. But thou shouldst have seen me when I was young. This was translated to Katharine, who said to Tante: Tell her that I can see her in my mind's eye as a beautiful young girl; but she has not forgotten how to be beautiful in her old age. Bedstemor was gratified, patted her on the back, and told her that she might come one day and drink coffee with her and see her wedding-cap.
- 79. Then she was introduced to old Kari, whom they passed on their way to Tante's favourite resting-place, an old black barn near a group of mountain-ashes. Kari was standing outside the great cowhouse; she looked at Katharine critically, seemed to approve of her, and said: She is nice looking, and strong too. She could do a good day's work in the fields. And how many children has she got? Well, I suppose she has not any, laughed wicked old Tante. She is not married. Perhaps she will find a husband here, said Kari reflectively. Perhaps she will, laughed Tante; and she was passing on when Kari came a little nearer to her and said mysteriously: If thou wilt come into the cowhouse to-morrow, I think I can tell thee something thou wilt like to hear—about the Huldre,[G] the beautiful long-tailed one—but thou must come alone. And I will sing to thee again very willingly, for thou art a kind one. And to-morrow Mette makes Fladbröd.[H] If thou dost wish to see her make the Fladbröd, thou shalt most certainly. Ja, and Mette can sing too. Thou shalt hear her also. Then she nodded and disappeared into the cowhouse. Tante and Katharine paused for a moment to look at the picturesque winter- house of the seventy cows, and its long, grass-grown roof, its two bridges leading up to the top floor, where some of the hay was stored, and its most curious gap in the centre of the upper floor, through which one could see enclosed in a great oblong frame the valley below, the rivers, and the distant mountains. Tante pointed out this beautiful picture to Katharine and said: You know, I really enjoy Nature very much, although I pretend not to do so just to tease Ejnar and Gerda. Ah, they are dears, both of them. It was good of you to come and bring them their parcel. You do not know how eagerly you have been looked for—by them and by me. Of course they wanted their parcel; but I had another reason for being eager to receive you. May a wicked old woman tell you something some day? Tell me now, Katharine said, turning to her.
- 80. Well, said Tante recklessly, it may be only an old woman's fancy; but he said in his letter that you did not really need a letter of introduction to me, since you were coming to see Ejnar and Gerda, and therefore me. But he felt that he could not be left out in the cold where you were concerned. Did he say that? asked Katharine, with a tremor in her voice. Yes, answered Tante; and they strolled on together in silence until they came to the hay-barn on the hillside, near the mountain- ashes, Tante's terminus. There they sat, still in silence, but with their hearts and thoughts charged with the remembrance of Clifford Thornton. It was a long silence, probably the longest which Knutty had ever endured without impatience; for an instinctive comradeship had sprung up between her and this Englishwoman in whose eyes the light of love had come when Clifford Thornton's name was spoken. They were both glad to be together, and they knew it. At last Knutty said: My dear, since we are both thinking of him all the time, shall we not speak of him? And Katharine looked up and answered simply: Yes, let us speak of him. So they spoke of him: Knutty with warm affection and pity; Katharine with sympathetic interest. That was all. She spoke of him as one traveller might speak of another traveller, both of them having met on some mountain-path in a distant land, spoken some words of greeting, and then passed on. That was all the personal part she thought she put into it. But Knutty listened, and heard distinct unspoken words. CHAPTER VI. Katharine spoke a fair amount of German, and some of the guests at the Gaard spoke a little English. The fur-merchant from Tromsö spoke English well; but he scorned at first to show any sign of friendliness to any one from such an abominable country; and the
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