ECE 368 Lab Project 1
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The lab project aims to design and analyze different 16-bit adders including a full adder, ripple carry adder (RCA), 2's complement adder/subtractor, and linear carry select adder. The RCA uses 16 full adders in series and has the largest propagation delay. The 2's complement adder/subtractor performs addition and subtraction by taking the 2's complement of one input. A behavioral model of the adder/subtractor has lower delay than the gate-level model. The carry select adder splits the inputs into blocks and generates carry signals in parallel to reduce delay compared to the RCA, but it has more logic gates.
ECE 368 Lab Project 1
- 1. LAB PROJECT 1 NAME: LAKSHMI YASASWI KAMIREDDY UIN: 651771619 Problem Description: The aim of the project is to design 16 bit addersusing different addersand design styles and to understand how these parameters effect the gate count, propagation delay and the RTL view of the design. The components designed are a Full Adder (gate level), a RCA 16-bit adder, a 2’s compliment adder/subtractor (gate level and behavioral level) and a Linear Carry Select Adder. Full Adder – Gate Level Design The functionality of a Full Adder is to calculate sum and carry when a sum of two input bits and a carry in is performed. Truth Table: Schematic: RTL View: The RTL View shows that the Full adder design matches the Schematic.
- 2. Code: 16 bit RCA: It is designed by connecting 16 full adders as shown in the schematic. A and B are 16 bit input vectors, Cin is the carry in, Sum is the 16 bit output vector and Cout is the carry out. This adder will have large delay because of its worst case path (shown in the schematic) going through all the full adders which will be 16*delay of FA. Schematic: Code: Gate Level Description
- 3. Test Bench: RTL View: RTL Simulation Waveform: The waveform shows the functionality of the RCA.
- 4. Gate Level Simulation Waveform in slow model (with a sample delay): Number of combinational functions: Maximum propagation delay:
- 5. 2’s compliment Adder/Subtractor: Using the RCA built an adder/subtractor is designed as shown in the Schematic. An XOR is for the input B and Add/Sub bit because when subtraction has to be done 2’compliment needs to be calculated. The XOR with 1 gives the 1’s compliment and through Cin which is the add/sub input, a 1 is added with gives the 2’compliment result. Worst case delay will be delay of the RCA + 2*XOR delay. Schematic: Code:
- 6. Test Bench: RTL View: To check if the B is negative andperform 2’s compliment
- 7. RTL Simulation Waveform Unsigned: RTL Simulation Signed: Gate Level Simulation Slow mode Unsigned: Gate Level Simulation Slow mode signed:
- 8. Number of combinational functions: Maximum Propagation Delay:
- 9. Adder/Subtractor Behavioral In this case if the add/sub bit is 1 i.e, Cin=1 then we do X-Y else we do X+Y using behavioral statements. Code: Testbench Behavioral statements
- 10. RTL View RTL Simulation - Unsigned RTL Simulation – Signed Gate Level Simulation - Unsigned Gate Level Simulation - Signed
- 11. Number of combinational functions: Maximum Propagation delay: Note that the delaydecreasedwhen comparedto the gate level model butthe numberof combinational functions increased.
- 12. Linear Carry Select Adder: Schematic: Code: Carry select 4 bit Carry Select 16 bit Behavioral Structural
- 13. Test Bench: RTL View: CSA 4 bit
- 14. CSA 16 bit RTL Simulation Gate Level Simulation Number of Combinational functions:
- 15. Maximum Propagation Delay Design Number of Combinational Functions Maximum Propagation delay RCA 16 bit gate level 38 18.968 Adder/Subtractor RCA gate level 33 23.185 Adder/Subtractor behavioral 34 14.642 Carry Select Adder 60 16.996 The table above shows that if an efficient gate level design can be done then we can reduce the number of combinational functions but a behavioral design is very efficient in reducing the delay. It can also be seen that CSA performs better in terms of delay but has a high number of combinational functions. Higher the number of combinational functional higher will be the number of gates in the circuit. Propagationdelay reducesas comparedto RCA but the numberof combinational functionsalmost doubles. Both cases Delay decreases Huge increase in numbermeans CSA has very higharea Almost equal