ECE 467 Final Project
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This project report describes the design of a 4-bit synchronous arithmetic logic unit (ALU) using a 250 nm silicon-on-insulator technology. The ALU can perform 4-bit addition, 2's complement, 1's complement, add-traction, NAND, and NOR operations based on operation codes. The schematic and layout designs of the ALU and its components were created in Cadence. Simulations of the ALU performing each operation were conducted to verify its functionality. In conclusion, the report presents the successful generation of schematic and layout designs for a 4-bit synchronous ALU along with simulation results.
ECE 467 Final Project
- 1. Project Report On 4 bit synchronous ALU (Arithmetic Logic Unit) using 250 nm SOI technology Team: 1. Bhavana Byreddy (UIN-657869795) 2. LakshmiYasaswiKamireddy 3. Sai Chinmayananda Korlimarla 4. Shashikala Kodandaraman
- 2. ProblemDescription: To Design (Both Schematic & Layout) a 4 bit synchronous ALU (Arithmetic Logic Unit) using 250 nm SOI technology that will be able to perform the following functions based on provided operation codes (op. codes). The function is selected throughcontrollines s2,s1,s0, theinputis evaluated usingthe respectivefunction. The output is stored in a 4-bitoutput register which is implemented using a D -flip- flop design. The functions and their op-codes arementioned below. 4 bit Addition (op. code 000) 2's Complement of A (op. code 001) 4 bit Add-traction (op. code 010) 4 input NAND operation using a NAND gate (op. code 011) 4 input NOR operation using a NOR gate (op. code 100) 1's Complement of B (op. code 101)
- 3. ALU An arithmetic logic unit (ALU) is a digital electronic circuit that performs arithmetic and bitwise logical operations on integer binary numbers. In this project, a 4-bit ALU is designed, implemented and simulated using Cadence. The ALU supports 4 bit addition, 2’s complement, 1’s complement, add-traction, NAND and NOR operations. The operations are selected using the select lines S0, S1, S2 as follows S0 S1 S2 OPERATION 0 0 0 Addition 0 0 1 2’s compliment 0 1 0 Add-traction 0 1 1 NAND 1 0 0 NOR 1 0 1 1’s compliment
- 5. LAYOUT: The placement of the components in the layout is as follows
- 6. Layout :
- 7. DRC check for layout: DRC is performed for layout and ensured that there are no errors. Layoutis designed in such a way that area is minimized.
- 9. SIMULATIONS: Addition: When the select lines S0 S1 S2 were set at 000, the operation selected was addition, the transientanalysis of the ALU was as follows
- 10. 2’s comp When the select lines S0 S1 S2 were set at 001, the operation selected is 2’s compliment, the transient analysis of the ALU was as follows
- 11. Addtraction When the select lines S0 S1 S2 were set at 010, the operation selected was addtraction, the transient analysis of the ALU was as follows
- 12. NAND: When the select lines S0 S1 S2 were set at 011, the operation selected was NAND, the transientanalysis of the ALU was as follows
- 13. NOR: When the select lines S0 S1 S2 were set at 100, the operation selected was NOR, the transientanalysis of the ALU was as follow
- 14. 1’s Complement When the select lines S0 S1 S2 were set at 101, the operation selected was 1’s compliment, the transientanalysis of the ALU was as follows
- 15. All the schematic and layout designs and simulation of the functionalunits that were used in ALU are shown below 2’s Compliment Schematic: Layout :
- 16. LVS Check: 1. FULL ADDER: Schematic:
- 22. LVS Check: 5. 1’s Compliment: Schematic
- 25. LVS Check: 7. 4 – Bit Register Schematic:
- 27. Without Parasitics Final ALUsimulations: NOR: Net 63 to 69 ---A0 to A3 Net 71 to 77 ---B0 to B3 Net 79 -clk Net 81 to 85 ---S0 to S2 Net 106 to 103 ---OPs
- 28. 2’s compliment:
- 29. WithParasitics:
- 30. Conclusion: Thus, schematic and layoutof 4 bit synchronous ALU(Arithmetic Logic Unit) using 250 nm SOI technology aregenerated and simulations are performed by obtaining transient analysis.