VLSI Final Design Project

The University of Texas at Dallas
EECT 6325- VLSI DESIGN
Fall 2018
16-bit ALU (Arithmetic Logic Unit)
by
Vignesh Ganesan – VXG170004
Jayashree Jayabalan – JXJ180012
Franson Joshua J – FXJ180000
Final Design Project

Introduction:
An arithmetic logic unit (ALU) is a digital circuit used to perform arithmetic and logic
operations. It represents the fundamental building block of the central processing unit (CPU)
of a computer.
An ALU performs basic arithmetic and logic operations. Examples of arithmetic operations are
addition, subtraction, multiplication, and division. Examples of logic operations are
comparisons of values such as NOT, AND, and OR. In this project 16bit ALU where two 16bit
inputs are given and the output obtained will be a 32bit one.

Design constraints:
The main fix in the design of cells is that size is always inversely proportional to delay. In the
design of these cells we used Wp/Wn ratio close to 2.22. Though the value of 3 is most desired
to obtain minimum delay, the size parameter is also considered during the design. Hence the
size and delay parameters are compromised during this design.
Hence we fixed the width of pfet as 2.4um and nfet as 1.08um. Hence the Wp/Wn ratio is 2.22
The Complete Process:
• We designed layout and schematics for 9 cells such as Inverter, NAND2, NOR2, XOR2,
OAI21, OAI211, flipflop, Mux 2:1 and AOI22.
• Using cadence tool, the layout was designed without any errors and was matched with
the schematics respectively.
• All the cells were made to have the same height(10.66um) throughout the design to
eliminate spacing errors during later part of the process in automatic placement and
routing.
• The pins were kept at same axis with equal spacing of 0.48*n. The space between
boundary and pin was maintained at 0.72um(0.24+0.48*n)
• The operation of these cells was tested using the HSpice software and was ensured the
cells were working.
• The abstract view of the cells was generated which were used for generation of LEF and
ASCII files.
• Create library using the Siliconsmart software mentioning the operation of each cell and
their specifications.
• Now using the generated library file create mapped netlist for the actual Verilog code.
• Using modelsim software compare the waveforms of both the codes. They should
exactly match.
• Using the Encounter tool, automatic placement and routing process was done. The
encounter tool requires the LEF files and the mapped netlist Verilog code.
• Once the routing is done add the vias and export the DEF file to the cadence location.
• Now the layout and schematic for the overall Verilog file would be generated.
• Run DRC and LVS for the same as done for the cells designed above.
• Using the generated library file, mapped netlist Verilog file and the design constraints
generate the power timing analysis using Primetime software.

Verilog code:
module alu(
input [15:0] A,B, // ALU 16-bit Inputs
input [3:0] ALU_Sel,// ALU Selection
output [31:0] Y, // ALU 32-bit Output
output CarryOut, // Carry Out Flag
input clk,
input reset
);
reg q;
reg [31:0] ALU_Result;
wire [16:0] tmp;
assign Y = ALU_Result; // ALU out
assign tmp = {1'b0,A} + {1'b0,B};
assign CarryOut = tmp[16]; // Carryout flag
always @(*)
begin
case(ALU_Sel)
4'b0000: // Addition
ALU_Result = A + B ;
4'b0001: // Subtraction
ALU_Result = A - B ;

4'b0010: // Multiplication
ALU_Result = A * B;
4'b0011: // Division
ALU_Result = A/B;
4'b0100: // Logical shift left
ALU_Result = B<<1;
4'b0101: // Logical shift right
ALU_Result = B>>1;
4'b0110: // Rotate left
ALU_Result = {B[14:0],B[15]};
4'b0111: // Rotate right
ALU_Result = {B[0],B[15:1]};
4'b1000: // Logical and
ALU_Result = A & B;
4'b1001: // Logical or
ALU_Result = A | B;
4'b1010: // Logical xor
ALU_Result = A ^ B;
4'b1011: // Logical nor
ALU_Result = ~(A | B);
4'b1100: // Logical nand
ALU_Result = ~(A & B);
4'b1101: // Logical xnor
ALU_Result = ~(A ^ B);
4'b1110: // Greater comparison
ALU_Result = (A>B)?16'd1:16'd0 ;
4'b1111: // Equal comparison

ALU_Result = (A==B)?16'd1:16'd0 ;
default: ALU_Result = A + B ;
endcase
end
always @ ( posedge clk)
if (reset==1)
begin
q <= 1'b0;
end else if(reset==0) begin
q <= ALU_Result;
end
endmodule
Test bench:
`timescale 1ns / 1ps
module tb_alu;
//Inputs
reg[15:0] A,B;
reg[3:0] ALU_Sel;
//Outputs
wire[31:0] ALU_Result;
wire CarryOut;
// Verilog code for ALU
integer i;

alu test_unit(
A,B, // ALU 8-bit Inputs
ALU_Sel,// ALU Selection
ALU_Out, // ALU 8-bit Output
CarryOut // Carry Out Flag
);
initial begin
// hold reset state for 100 ns.
A = 16'h0A;
B = 8'h02;
ALU_Sel = 4'h0;
for (i=0;i<=31;i=i+1)
begin
ALU_Sel = ALU_Sel + 16'h01;
#10;
end
A = 16'hF6;
B = 16'h0A;
end
endmodule

Modelsim Waveforms:
1) Actual Verilog file and testbench
2) Mapped netlist and testbench

Layout of cells with uniform height
1) AOI22
2) MUX 2:1

DRC(Design Rule Checker):
LVS(Layout VS Schematic):

VLSI Final Design Project

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