8 Bit A L U
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This document outlines the design and implementation of an 8-bit ALU (arithmetic logic unit). Basic logic gates like NOR and NAND were created first. D flip-flops and multiplexers were used to store and select data. An XOR gate, 1-bit full adder, 1-bit full subtractor, and 1-bit ALU were designed and tested. Finally, an 8-bit ALU was implemented and tested for minimum size and maximum speed.
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8 Bit A L U
- 1. 8-bit ALU (AND, OR, ADD, SUB)
- 2. Basic Building Blocks To initiate the project, we needed to create the basic building blocks: AND, NAND, OR, and NOR gates. Since a NOR gate and NAND gate input with A not and B not are a AND gate and a OR gate, respectively, we need only design a NOR and NAND.
- 3. NOR Layout
- 5. NAND Layout
- 7. Data Holding and Selection To store data, we used D flip-flops at data input and data output. Usage of the D flip-flops also gave our team access to the A not and B not needed for the AND and OR gates. For data selection at the output, we used 4-1 MUX’s for each bit.
- 11. Mux Layout
- 12. XOR (used in Adder/Subtractor) XOR Layout XOR Transient
- 13. 1-bit Full Adder
- 14. Schematic
- 15. Transient
- 16. Layout
- 18. Schematic
- 19. Transient
- 20. Layout
- 21. 1-bit ALU
- 22. 1-bit ALU
- 23. 1-bit ALU
- 24. 8-bit AND
- 25. 8-bit OR
- 26. 8-bit ALU Layout
- 27. Conclusion This project was successful due to teamwork and dedication. My team and I were able to design, test, and build an 8-bit ALU with emphasis on minimum chip size and maximum speed.