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Design and implementation of low power

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Surendra Bommavarapu

The document summarizes the design and implementation of a low power reversible arithmetic logic unit (ALU) using parity preserving logic gates. Key points: 1. The ALU design uses parity preserving reversible logic gates to make it fault tolerant and reduce power dissipation. 2. A new 4x4 parity preserving gate is proposed and used in the design along with existing parity preserving gates to reduce gate count and garbage outputs. 3. Simulation results show the proposed ALU can perform 16 logical and 16 arithmetic operations with a gate count of 13, garbage outputs of 28, and constant inputs of 23. This is an improvement over previous designs.

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DESIGNAND IMPLEMENTATION OFLOWPOWER REVERSIBLE ALU USING PARITYPRESERVING LOGIC Under the Guidance of Dr. Y.SYAMALA Associate Professor Department of Electronics and Communication Engineering Gudlavalleru Engineering College By G.VENKATA LATHA 13481D5507 M.Tech - Embedded Systems
OUTLINE
DesignofArithmeticLogicUnit BasedonParity PreservingReversibleLogicGates Where Ai, Bi are input operands, S0-S3 are selection lines, Ci-1 is input carry, M is mode control bit and Fi is output of ALU. Xi= S3AiBi+S2AiBi Yi = Ai+S0Bi+S1Bi Ci = Cin+M i=0 Y0 + X0Cin + M i = 1 Yi + XiCi−1 + M i ≥ 2 and 𝐹𝑖 = 𝑋𝑖 ⊕ 𝑌𝑖 ⊕ 𝐶𝑖
INTERNALSTRUCTURE OF FUNCTION GENERATOR Gate Count=8 Garbage Output=16 Constant Inputs=14
SIMULATION RESULTS OF FUNCTIONGENERATOR
RTL SCHEMATIC OF FUNCTION GENERATOR MODULE Xi MODULE Yi
INTERNALSTRUCTURE OF MODECONTROLUNIT Gate Count=4 Garbage Output=8 Constant Inputs=8
SIMULATION RESULTS OF MODECONTROLUNIT
RTL SCHEMATIC OFMODECONTROLUNIT
FUNCTION CONTROLLER Gate Count=1 Garbage Output=3 Constant Inputs=1
SimulationResultsof1-bitArithmeticLogicUnit
RTLSchematic of1-bit ArithmeticLogicUnit
NEW 4X4 PARITY PRESERVING GATE  It is a 4X4 reversible gate.  It works as either reversible Full adder or a Full sub tractor.
1-May-15 INPUTS EX-OR of inputs OUTPUTS EX-OR of outputs A B C D P Q R S 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 1 0 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 1 1 0 1 0 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 0 1 1 1 1 0 0 1 0 1 1 0 0 0 1 1 1 0 1 1 1 0 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 0 1 0 1 1 1 1 0 0 0 1 1 1 0 0 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 0 NEW 4X4 PARITY PRESERVING GATE(Cond…)  EX-OR of inputs=Ex-OR of outputs. So, it is a “Parity Preserving Gate” 14
NEW 4X4 GATE IMPLEMENTED AS A FULLADDER
NEW 4X4 GATE IMPLEMENTED AS A FULLSUBTRACTOR
Design and implementation of low power
INTERNALSTRUCTURE OF FUNCTION GENERATOR Gate Count=10 Garbage Output=19 Constant Inputs=17
SIMULATION RESULTS OF FUNCTIONGENERATOR
RTL SCHEMATIC OF FUNCTIONGENERATOR MODULE Xi MODULE Yi
INTERNALSTRUCTURE OF MODECONTROLUNIT Gate Count=6 Garbage Output=15 Constant Inputs=15
SIMULATION RESULTS OF MODECONTROLUNIT
RTL SCHEMATIC OFMODECONTROLUNIT
FUNCTION CONTROLLER Gate Count=1 Garbage Output=3 Constant Inputs=1
SimulationResultsof1-bitArithmeticLogicUnit
RTLSchematic of1-bit ArithmeticLogicUnit
COMPARISONOFPERFORMANCE PARAMETERS Authors Title of the paper/Year Parity preserving Gate count per 1-bit ALU) Garbage Outputs Constant Inputs Observed Result Proposed ALU Design and Implementation of LowPower Reversible ALU Using Parity Preserving Logic Yes 13 28 23 16logical and 16arithmetic operations. Shefali Mamataj An Optimized realization of ALU for 12-Operations by using a Control Unit of reversible gates, 2014 (J). No 8 10 3 3 logical and 9arithmetic operations. (Base Paper) Rakshith T.R Parity Preserving Logic based Fault Tolerant Reversible ALU, 2013 (C). Yes 17 37 33 16logical and 16arithmetic operations. Rozhin Bashiri Designing a Novel Nanometric Parity Preserving Reversible ALU,2013(J). Yes 22 28 19 4 logical and 4 arithmetic operations.
TOOLS REQUIRED Tools Required: Front end Design Tools.(XILINX ISE) Language Required: HDL programming language. 1-May-15 13
PLAN OFACTION S.NO ACTIVITY Number of Weeks required (40) 1 Literature survey 4 2 Study and implementation of base paper 4 3 Implementation of Conventional ALU. 4 4 Implementation of proposed gate 5 5 Implementation of Reversible ALU 6 6 Power Analysis of Proposed ALU and Conventional ALU +Literature survey 7 7 Paper publication work +Literature survey 5 8 Project documentation work +Literature survey 5 1-May-15 14
CONCLUSION 1-May-15 15 The ALU is the most prominent component of any processor. Thus designing of ALU using parity preserving reversible logic gates will make the ALU fault tolerant and reduce the power dissipation.  In this work along with the existing parity preserving gates, a new gate will be used in designing to reduce gate count and garbage outputs.
REFERENCES [1] T.R.Rakshith and R. Saligram, “Parity preserving logic based fault tolarent reversible ALU,” IEEE conference on Information and communication Technologies (ICT), pp.485-490, April 2013. [2] Soghra shoaei and majid Haghparast, “Novel design of nanometric parity preserving reversible compressor,” Springer science,Business Media Newyark, pp.1701-1714, May 2014. [3] Zhijin Guan,Wenjuan Li, Weiping and Yueqin hang, “An Arithmetic Logic Uniit design based on reversible logic gate,” IEEE conference on Communications,Computers and Signal processing, pp.925-931, August 2011. [4] S.Anusha, M.Manoher Rao, and N.Swetha Reddy, “Design, Analysis, Implementation and Synthesis of 16 bit Reversible ALU by using Xilinx 12.2,” International Journal of Engineering Research and Applications, pp.86-91, April 2014. [5] Rekha K.James,Shahana T.K and K.Poulose Jacob,“Fault Tolerant Error Coding and Detection using Reversible Gates,” IEEE Region 10 Conference TENCON, pp.1-4, October 2007. 1-May-15 16
REFERENCES (contd….) [6] Mahammand and Kamakoti Veezhinathan, “Constructing online Testing Circuits using Reversible Logic” IEEE Transactions on Instrumentation and Measurement, pp 101-109, January 2010. [7] Xuemei Qi, Fulong Chen, Kaizhong Zuo, Liangmin Guo, Yonglong Luo and Min Hu, “Design of fast fault tolerant reversible signed multiplier,” International Journal of the Physical Sciences, pp. 2506 - 2514, 23 April 2012. [8] Raghava Garipelly, P.Madhu Kiran and A.Santhosh Kumar “ A Review on Reversible Logic Gates and their Implementation,” International Journal of Emerging Technology and Advanced Engineering, vol 3, pp.417-423, March 2013. [9] Himanshu Thapliyal, Apeksha Bhatt and Nagarajan Ranganathan,“A New CRL Gates as super class of Fredkin Gate to Design Reversible Quantum Circuits,” IEEE 56th Inrnational Midwest Symposium on Circuits and Systems (MWSCAS), pp.1067-1070, August 2013. [10] B. Parhami, "Fault tolerant reversible circuits", Asimolar Conference on Signal, systems and computer, pp.1726-1729, October 2006. 1-May-15 17
THANK YOU ALL

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Design and implementation of low power

  • 1. DESIGNAND IMPLEMENTATION OFLOWPOWER REVERSIBLE ALU USING PARITYPRESERVING LOGIC Under the Guidance of Dr. Y.SYAMALA Associate Professor Department of Electronics and Communication Engineering Gudlavalleru Engineering College By G.VENKATA LATHA 13481D5507 M.Tech - Embedded Systems
  • 3. DesignofArithmeticLogicUnit BasedonParity PreservingReversibleLogicGates Where Ai, Bi are input operands, S0-S3 are selection lines, Ci-1 is input carry, M is mode control bit and Fi is output of ALU. Xi= S3AiBi+S2AiBi Yi = Ai+S0Bi+S1Bi Ci = Cin+M i=0 Y0 + X0Cin + M i = 1 Yi + XiCi−1 + M i ≥ 2 and 𝐹𝑖 = 𝑋𝑖 ⊕ 𝑌𝑖 ⊕ 𝐶𝑖
  • 4. INTERNALSTRUCTURE OF FUNCTION GENERATOR Gate Count=8 Garbage Output=16 Constant Inputs=14
  • 5. SIMULATION RESULTS OF FUNCTIONGENERATOR
  • 6. RTL SCHEMATIC OF FUNCTION GENERATOR MODULE Xi MODULE Yi
  • 7. INTERNALSTRUCTURE OF MODECONTROLUNIT Gate Count=4 Garbage Output=8 Constant Inputs=8
  • 8. SIMULATION RESULTS OF MODECONTROLUNIT
  • 10. FUNCTION CONTROLLER Gate Count=1 Garbage Output=3 Constant Inputs=1
  • 13. NEW 4X4 PARITY PRESERVING GATE  It is a 4X4 reversible gate.  It works as either reversible Full adder or a Full sub tractor.
  • 14. 1-May-15 INPUTS EX-OR of inputs OUTPUTS EX-OR of outputs A B C D P Q R S 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 1 0 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 1 1 0 1 0 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 0 1 1 1 1 0 0 1 0 1 1 0 0 0 1 1 1 0 1 1 1 0 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 0 1 0 1 1 1 1 0 0 0 1 1 1 0 0 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 0 NEW 4X4 PARITY PRESERVING GATE(Cond…)  EX-OR of inputs=Ex-OR of outputs. So, it is a “Parity Preserving Gate” 14
  • 15. NEW 4X4 GATE IMPLEMENTED AS A FULLADDER
  • 16. NEW 4X4 GATE IMPLEMENTED AS A FULLSUBTRACTOR
  • 18. INTERNALSTRUCTURE OF FUNCTION GENERATOR Gate Count=10 Garbage Output=19 Constant Inputs=17
  • 19. SIMULATION RESULTS OF FUNCTIONGENERATOR
  • 20. RTL SCHEMATIC OF FUNCTIONGENERATOR MODULE Xi MODULE Yi
  • 21. INTERNALSTRUCTURE OF MODECONTROLUNIT Gate Count=6 Garbage Output=15 Constant Inputs=15
  • 22. SIMULATION RESULTS OF MODECONTROLUNIT
  • 24. FUNCTION CONTROLLER Gate Count=1 Garbage Output=3 Constant Inputs=1
  • 27. COMPARISONOFPERFORMANCE PARAMETERS Authors Title of the paper/Year Parity preserving Gate count per 1-bit ALU) Garbage Outputs Constant Inputs Observed Result Proposed ALU Design and Implementation of LowPower Reversible ALU Using Parity Preserving Logic Yes 13 28 23 16logical and 16arithmetic operations. Shefali Mamataj An Optimized realization of ALU for 12-Operations by using a Control Unit of reversible gates, 2014 (J). No 8 10 3 3 logical and 9arithmetic operations. (Base Paper) Rakshith T.R Parity Preserving Logic based Fault Tolerant Reversible ALU, 2013 (C). Yes 17 37 33 16logical and 16arithmetic operations. Rozhin Bashiri Designing a Novel Nanometric Parity Preserving Reversible ALU,2013(J). Yes 22 28 19 4 logical and 4 arithmetic operations.
  • 28. TOOLS REQUIRED Tools Required: Front end Design Tools.(XILINX ISE) Language Required: HDL programming language. 1-May-15 13
  • 29. PLAN OFACTION S.NO ACTIVITY Number of Weeks required (40) 1 Literature survey 4 2 Study and implementation of base paper 4 3 Implementation of Conventional ALU. 4 4 Implementation of proposed gate 5 5 Implementation of Reversible ALU 6 6 Power Analysis of Proposed ALU and Conventional ALU +Literature survey 7 7 Paper publication work +Literature survey 5 8 Project documentation work +Literature survey 5 1-May-15 14
  • 30. CONCLUSION 1-May-15 15 The ALU is the most prominent component of any processor. Thus designing of ALU using parity preserving reversible logic gates will make the ALU fault tolerant and reduce the power dissipation.  In this work along with the existing parity preserving gates, a new gate will be used in designing to reduce gate count and garbage outputs.
  • 31. REFERENCES [1] T.R.Rakshith and R. Saligram, “Parity preserving logic based fault tolarent reversible ALU,” IEEE conference on Information and communication Technologies (ICT), pp.485-490, April 2013. [2] Soghra shoaei and majid Haghparast, “Novel design of nanometric parity preserving reversible compressor,” Springer science,Business Media Newyark, pp.1701-1714, May 2014. [3] Zhijin Guan,Wenjuan Li, Weiping and Yueqin hang, “An Arithmetic Logic Uniit design based on reversible logic gate,” IEEE conference on Communications,Computers and Signal processing, pp.925-931, August 2011. [4] S.Anusha, M.Manoher Rao, and N.Swetha Reddy, “Design, Analysis, Implementation and Synthesis of 16 bit Reversible ALU by using Xilinx 12.2,” International Journal of Engineering Research and Applications, pp.86-91, April 2014. [5] Rekha K.James,Shahana T.K and K.Poulose Jacob,“Fault Tolerant Error Coding and Detection using Reversible Gates,” IEEE Region 10 Conference TENCON, pp.1-4, October 2007. 1-May-15 16
  • 32. REFERENCES (contd….) [6] Mahammand and Kamakoti Veezhinathan, “Constructing online Testing Circuits using Reversible Logic” IEEE Transactions on Instrumentation and Measurement, pp 101-109, January 2010. [7] Xuemei Qi, Fulong Chen, Kaizhong Zuo, Liangmin Guo, Yonglong Luo and Min Hu, “Design of fast fault tolerant reversible signed multiplier,” International Journal of the Physical Sciences, pp. 2506 - 2514, 23 April 2012. [8] Raghava Garipelly, P.Madhu Kiran and A.Santhosh Kumar “ A Review on Reversible Logic Gates and their Implementation,” International Journal of Emerging Technology and Advanced Engineering, vol 3, pp.417-423, March 2013. [9] Himanshu Thapliyal, Apeksha Bhatt and Nagarajan Ranganathan,“A New CRL Gates as super class of Fredkin Gate to Design Reversible Quantum Circuits,” IEEE 56th Inrnational Midwest Symposium on Circuits and Systems (MWSCAS), pp.1067-1070, August 2013. [10] B. Parhami, "Fault tolerant reversible circuits", Asimolar Conference on Signal, systems and computer, pp.1726-1729, October 2006. 1-May-15 17