Edc unit 7

EDC-UNITVII Question&answer
GRIET-ECE G.Surekha Page 1
UNIT-VII FET AMPLIFIERS
1. With the help of a neat schematic, explain the functioning of a common source
amplifier.
Common Source JFET Amplifier
small signal amplifiers can also be made using Field Effect Transistors or FET's .
These devices have the advantage over bipolar transistors of having extremely high input
impedance along with a low noise output making them ideal for use in amplifier circuits
that have very small input signals. The design of an amplifier circuit based around a
junction field effect transistor or "JFET", (n-channel FET) or even a metal oxide silicon
FET or "MOSFET" is exactly the same principle as that for the bipolar transistor circuit.
Firstly, a suitable quiescent point or "Q-point" needs to be found for the correct biasing of
the JFET amplifier circuit with single amplifier configurations of Common-source (CS),
Common-drain (CD) or Source-follower (SF) and the Common-gate (CG) available for
most FET devices. These three JFET amplifier configurations correspond to the common-
emitter, emitter-follower and the common-base configurations using bipolar transistors.
The Common Source JFET Amplifier as this is the most widely used JFET amplifier
design. The common source JFET amplifier circuit is shown below.
The amplifier circuit consists of an N-channel JFET, connected in a common source
configuration. The JFET gate voltage Vg is biased through the potential divider network
set up by resistors R1 and R2 and is biased to operate within its saturation region which is
equivalent to the active region of the bipolar junction transistor. Unlike a bipolar
transistor circuit, the junction FET takes virtually no input gate current allowing the gate
to be treated as an open circuit. Then no input characteristics curves are required. Since
the N-Channel JFET is a depletion mode device and is normally "ON", a negative gate
voltage with respect to the source is required to modulate or control the drain current.
This negative voltage can be provided by biasing from a separate power supply voltage or
by a self biasing arrangement as long as a steady current flow through the JFET even
when there is no input signal present and Vg maintains a reverse bias of the gate-source
pn junction. In this example the biasing is provided from a potential divider network
allowing the input signal to produce a voltage fall at the gate as well as voltage rise at the
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gate with a sinusoidal signal. Any suitable pair of resistor values in the correct
proportions would produce the correct biasing voltage so the DC gate biasing voltage Vg
is given as:
The input signal, (Vin) of the common source JFET amplifier is applied between the Gate
terminal and the zero volts rail, (0v). With a constant value of gate voltage Vg applied the
JFET operates within its "Ohmic region" acting like a linear resistive device. The drain
circuit contains the load resistor, Rd. The output voltage, Vout is developed across this
load resistance. The efficiency of the common source JFET amplifier can be improved by
the addition of a resistor, Rs included in the source lead with the same drain current
flowing through this resistor. Resistor, Rs is also used to set the JFET amplifiers "Q-
point".
When the JFET is switched fully "ON" a voltage drop equal to Rs x Id is developed
across this resistor raising the potential of the source terminal above 0v or ground level.
This voltage drop across Rs due to the drain current provides the necessary reverse
biasing condition across the gate resistor, R2 effectively generating negative feedback. In
order to keep the gate-source junction reverse biased, the source voltage, Vs needs to be
higher than the gate voltage, Vg. This source voltage is therefore given as:
Then the Drain current, Id is also equal to the Source current, Is as "No Current" enters
the Gate terminal and this can be given as:
This potential divider biasing circuit improves the stability of the common source JFET
amplifier circuit when being fed from a single DC supply compared to that of a fixed
voltage biasing circuit. Both resistor, Rs and the source by-pass capacitor, Cs serve
basically the same function as the emitter resistor and capacitor in the common emitter
bipolar transistor amplifier circuit, namely to provide good stability and prevent a
reduction in the loss of the voltage gain. However, the price paid for a stabilized
quiescent gate voltage is that more of the supply voltage is dropped across Rs.
The basic circuit and characteristics of a Common Source JFET Amplifier are very
similar to that of the common emitter amplifier. A DC load line is constructed by joining
the two points relating to the drain current, Id and the supply voltage, Vdd remembering
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that when Id = 0: ( Vdd = Vds ) and when Vds = 0: ( Id = Vdd/RL ). The load line is
therefore the intersection of the curves at the Q-point as follows.
Common Source JFET Amplifier Characteristics Curves
As with the common emitter bipolar circuit, the DC load line for the common source
JFET amplifier produces a straight line equation whose gradient is given as: -1/(Rd + Rs)
and that it crosses the vertical Id axis at point A equal to Vdd/(Rd + Rs). The other end of
the load line crosses the horizontal axis at point B which is equal to the supply voltage,
Vdd. The actual position of the Q-point on the DC load line is generally positioned at the
mid centre point of the load line (for class-A operation) and is determined by the mean
value of Vg which is biased negatively as the JFET is a depletion-mode device. Like the
bipolar common emitter amplifier the output of the Common Source JFET Amplifier is
180o
out of phase with the input signal.
One of the main disadvantages of using Depletion-mode JFET is that they need to be
negatively biased. Should this bias fail for any reason the gate-source voltage may rise
and become positive causing an increase in drain current resulting in failure of the drain
voltage, Vd. Also the high channel resistance, Rds(on) of the junction FET, coupled with
high quiescent steady state drain current makes these devices run hot so additional
heatsink is required. However, most of the problems associated with using JFET's can be
greatly reduced by using enhancement-mode MOSFET devices instead.
MOSFETs or Metal Oxide Semiconductor FET's have much higher input impedances and
low channel resistances compared to the equivalent JFET. Also the biasing arrangements
for MOSFETs are different and unless we bias them positively for N-channel devices and
negatively for P-channel devices no drain current will flow.
2. Explain Common Gate amplifier.
A common-gate amplifier is one of three basic single-stage field-effect transistor
(FET) amplifier topologies, typically used as a current buffer or voltage amplifier. In this
circuit the source terminal of the transistor serves as the input, the drain is the output and
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the gate is common to both, hence its name. The analogous bipolar junction transistor
circuit is the common-base amplifier.
Figure 1: Basic N-channel common-gate circuit (neglecting biasing details); current
source ID represents an active load; signal is applied at node Vin and output is taken from
node Vout; output can be current or voltage
Figure 2: Hybrid pi model with test source ix at output to find output resistance
The amplifier characteristics are summarized below in Table 1. The approximate
expressions use the assumptions (usually accurate) rO >> RL and gmrO >> 1.
Table 1 Definition Expression
Approximate
expression
Short-circuit
current gain
Open-circuit
voltage gain
Input resistance
Output resistance
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In general the overall voltage/current gain may be substantially less than the open/short
circuit gains listed above (depending on the source and load resistances) due to the
loading effect.
Closed circuit voltage gain
Taking input and output loading into consideration, the closed circuit voltage gain (that
is, the gain with load RL and source with resistance RS both attached) of the common gate
can be written as:
,
Which has the simple limiting forms
,
Depending upon whether gmRS is much larger or much smaller than one.
In the second case RS << 1/gm and the Thévenin representation of the source is useful,
producing the second form for the gain, typical of voltage amplifiers. Because the input
impedance of the common-gate amplifier is very low, the cascode amplifier often is used
instead. The cascode places a common-source amplifier between the voltage driver and
the common-gate circuit to permit voltage amplification using a driver with RS >> 1/gm.
3. Explain about Common Drain amplifier or Source Follower.
A common-drain amplifier, also known as a source follower, is one of three basic
single-stage field effect transistor (FET) amplifier topologies, typically used as a voltage
buffer. In this circuit the gate terminal of the transistor serves as the input, the source is
the output, and the drain is common to both (input and output), hence its name. The
analogous bipolar junction transistor circuit is the common-collector amplifier. This
circuit is used to transform impedances.
Basic N-channel JFET source follower circuit (neglecting biasing details).
At low frequencies, the source follower has the following small signal characteristics.
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Voltage gain:
Current gain:
Input impedance:
Output impedance:
The variable gm that is not listed in Figure 1 is the trans conductance of the device
(usually given in units of Siemens.
4. Explain about FET Biasing methods.
Unlike BJTs, thermal runaway does not occur with FETs. However, the wide
differences in maximum and minimum transfer characteristics make ID levels
unpredictable with simple fixed-gate bias voltage. To obtain reasonable limits on
quiescent drain currents ID and drain-source voltage VDS, source resistor and potential
divider bias techniques must be used. With few exceptions, MOSFET bias circuits are
similar to those used for JFETs. Various FET biasing circuits are discussed below
Fixed Bias.
DC bias of a FET device needs setting of gate-source voltage VGS to give desired drain
current ID . For a JFET drain current is limited by the saturation current IDS. Since the
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FET has such a high input impedance that no gate current flows and the dc voltage of the
gate set by a voltage divider or a fixed battery voltage is not affected or loaded by the
FET.
Fixed dc bias is obtained using a battery VQG. This battery ensures that the gate is always
negative with respect to source and no current flows through resistor RG and gate
terminal that is IG =0. The battery provides a voltage VGS to bias the N-channel JFET, but
no resulting current is drawn from the battery VGG. Resistor RG is included to allow any
ac signal applied through capacitor C to develop across RG. While any ac signal will
develop across RG, the dc voltage drop across RG is equal to IG RG i.e. 0 volt.
The gate-source voltage VGS is then
VGS = - VG – VS = – VGG – 0 = – VGG
The drain -source current ID is then fixed by the gate-source voltage as determined by
equation.
This current then causes a voltage drop across the drain resistor RD and is given as VRD =
ID RD and output voltage, Vout = VDD – ID RD
Self-Bias.
This is the most common method for biasing a JFET. Self-bias circuit for N-channel
JFET is shown in figure.
Since no gate current flows through the reverse-biased gate-source, the gate current IG =
0 and, therefore,vG = iG RG = 0 With a drain current ID the voltage at the S is
Vs= ID Rs
The gate-source voltage is then
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VGs = VG - Vs = 0 – ID Rs = – ID Rs
So voltage drop across resistance Rs provides the biasing voltage VGg and no external
source is required for biasing and this is the reason that it is called self-biasing.
The operating point (i.e zero signal ID and VDS) can easily be determined from
equation and equation given below :
VDS = VDD – ID (RD + RS)
Thus dc conditions of JFET amplifier are fully specified. Self biasing of a JFET stabilizes
its quiescent operating point against any change in its parameters like trans conductance.
Let the given JFET be replaced by another JFET having the double conductance then
drain current will also try to be double but since any increase in voltage drop across Rs,
therefore, gate-source voltage, VGS becomes more negative and thus increase in drain
current is reduced.
Potential-Divider Biasing.
A slightly modified form of dc bias is provided by the circuit shown in figure. The
resistors RGl and RG2 form a potential divider across drain supply VDD. The voltage V2
across RG2 provides the necessary bias. The additional gate resistor RGl from gate to
supply voltage facilitates in larger adjustment of the dc bias point and permits use of
larger valued RS.
The gate is reverse biased so that IG = 0 and gate voltage
VG =V2 = (VDD/R G1 + R G2 ) *RG2
And
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VGS = VG – VS = VG - ID RS
The circuit is so designed that ID, Rs is greater than VD so that VGS is negative. This provides correct bias voltage.
The operating point can be determined as
ID = (V2 – VGS)/ RS
And
VDS = VDD – ID (RD + RS)
5. Explain FET as a voltage variable resistor(VVR).
FET AS A VOLTAGE –VARIABLE RESISTOR (VVR):
FET is operated in the constant current portion of its output characteristics for the linear
applications .In the region before pinch off , where Vds is small the drain to source
resistance rd can be controlled by the bias voltage Vgs.The FET is useful as a voltage
variable resistor (VVR) or Voltage Dependent resistor.
In JFET the drain source conductance gd = Id/Vds for small values of Vds which may be
expressed as gd = gdo [ 1-( VgsVp)1/2
] where gdo is the value of drain conductance
when the bias voltage Vgs is zero.Small signal FET drain resistance rd varies with
applied gate voltage Vgs and FET act like a VARIABLE PASSIVE RESISTOR.
When VDS < VP, Id VDS, when VGS is constant. i.e., FET acts as a resistor.In this region
FET is used as a Voltage controlled resistor. Or Voltage variable resistor. Or Voltage
dependant resistor.
6. List out the differences between BJT and FET
Differences between BJT and FET
1) FET is uni polar device – current ID is due to majority (Where as BJT is
Bipolar) charge carries only.
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2) FET is less noisy as there are no junctions(in conduction channel) FET
3) FET Input impedance is very high (100 M ) (due to reverse bias)
4) FET is voltage controlled device, BJT is current controlled device
5) FETs are easy to fabricate
6) FET performance does not change much with temperature. FET has –Ve
temp. Coefficient, BJT has +Ve temp. coefficient.
7) FET has higher switching speeds
8) FET is useful for small signal operation only
9) BJT is cheaper than FET.
7. Explain about Uni-Junction Transistor(UJT) with the help of characteristics.
A unijunction transistor (UJT) is an electronic semiconductor device that has only one
junction. The UJT has three terminals: an emitter (E) and two bases (B1 and B2). The
base is formed by lightly doped n-type bar of silicon. Two ohmic contacts B1 and B2 are
attached at its ends. The emitter is of p-type and it is heavily doped. The resistance
between B1 and B2, when the emitter is open-circuit is called interbase resistance.
The UJT is biased with a positive voltage between the two bases. This causes a potential
drop along the length of the device. When the emitter voltage is driven approximately
one diode voltage above the voltage at the point where the P diffusion (emitter) is, current
will begin to flow from the emitter into the base region. Because the base region is very
lightly doped, the additional current (actually charges in the base region) causes
conductivity modulation which reduces the resistance of the portion of the base between
the emitter junction and the B2 terminal. This reduction in resistance means that the
emitter junction is more forward biased, and so even more current is injected. Overall, the
effect is a negative resistance at the emitter terminal. This is what makes the UJT useful,
especially in simple oscillator circuits.
Construction: A unijunction transistor is composed of a bar of N-type silicon having a
P-type connection in the middle. Shown in Figure below(a). The connections at the ends
of the bar are known as bases B1 and B2; the P-type mid-point is the emitter. With the
emitter disconnected, the total resistance RBBO,is the sum of RB1 and RB2 as shown in
Figure below(b). The intrinsic standoff ratio η is the ratio of RB1 to RBBO. It varies from
0.4 to 0.8 for different devices. The schematic symbol is Figure below(c)
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Unijunction transistor: (a) Construction, (b) Model, (c) Symbol
The Uni-junction emitter current vs voltage characteristic curve (Figure below(a) ) shows
that as VE increases, current IE increases up IP at the peak point. Beyond the peak point,
current increases as voltage decreases in the negative resistance region. The voltage
reaches a minimum at the valley point. The resistance of RB1, the saturation resistance is
lowest at the valley point. VP is the voltage drop across RB1 plus a 0.7V diode drop; see
Figure below(b). VV is estimated to be approximately 10% of VBB.
8. Describe the application of UJT as a relaxation oscillator.
The relaxation oscillator in Figure below is an application of the unijunction oscillator.
RE charges CE until the peak point. The unijunction emitter terminal has no effect on the
capacitor until this point is reached. Once the capacitor voltage, VE, reaches the peak
voltage point VP, the lowered emitter-base1 E-B1 resistance quickly discharges the
capacitor. Once the capacitor discharges below the valley point VV, the E-RB1 resistance
reverts back to high resistance, and the capacitor is free to charge again.
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During capacitor discharge through the E-B1 saturation resistance, a pulse may be seen
on the external B1 and B2 load resistors, Figure above. The load resistor at B1 needs to
be low to not affect the discharge time. The external resistor at B2 is optional. It may be
replaced by a short circuit. The approximate frequency is given by 1/f = T = RC. A more
accurate expression for frequency is given in Figure above.
The charging resistor RE must fall within certain limits. It must be small enough to allow
IP to flow based on the VBB supply less VP. It must be large enough to supply IV based on
the VBB supply less VV.
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