Error Permissive Computing
1) The document explores a new concept called error permissive computing that improves computing capabilities and reduces power consumption by allowing and managing hardware errors through system software instead of eliminating errors through general purpose hardware error correction. 2) It describes several approaches for implementing error permissive computing including a software framework called BITFLEX that enables approximate computing, an FPGA-based memory emulator for evaluating new system software mechanisms, and techniques for sparse and topology-aware communication that can accelerate large-scale deep learning and reduce communication costs. 3) The goal is to take a holistic approach across hardware and software layers to perform lightweight error correction at the software level while eliminating general purpose error correction in hardware for improved efficiency.
![LogicNetwork Memory
③ System Software (BITFLEX, etc)
② Emulation/Simulation (RAMinate, mesmeric, etc)
Applications (Deep Learning, Graph Processing, etc)
① Error Modeling of Devices
Error Permissive Computing: a New Approach
for Post Moore’s Computer System Design
Abstract We are exploring a new concept of error permissive computing that improves the
capability and capacity while drastically reducing power consumption. More specifically, we
controllably allow hardware errors and develop system software to assure acceptable computational
results. For example, an error correction technique can result in increased latency and reduced
capacity. By taking a holistic approach across the layers from hardware to software, lightweight and
appropriate error correction is performed at the software layer while eliminating general purpose
error correction in hardware layer.
Ryousei Takano, Takahiro Hirofuchi, Mohamed Wahib,
Truong Thao Nguyen, Hiroki Kanezashi, Akram Ben Ahmed
National Institute of Advanced Industrial Science and Technology
The 2nd R-CCS International Symposium, Kobe, February 2020
References
[1] R. Barton, et al. “BITFLEX: A Dynamic Runtime Library for Bit-Level Precision Manipulation and Approximate Computing,” HPC Asia 2020.
[2] T. Hirofuchi, et al. “FPGAによる次世代メモリのエミュレーション機構の試作”, IPSJ SIGHPC171, 2019.
[3] T. Nguyen, et al. “Topology-aware Sparse Allreduce for Large-scale Deep Learning”, IEEE IPCCC 2019.
BITFLEX Full Stack
(OpenMP Extension)
ADAPT Case Study: Pi Accumulator
• We require an attractive means
of boosting performance and
maintaining accuracy in non-
deterministic applications.
• Solution: BITFLEX framework
incorporated in MCXX compiler.
• We propose an extension of
OpenMP as follows:
#pragma omp nondeter <parameters>
Analysis and modeling of bit-flip errors
in voltage-driven MRAM
• The write error ratio of each memory cell is different
due to the variation of magnetic anisotropy (σ).
FPGA-based new memory device emulator [2]
• Emulate the behavior of new memory devices (latency,
bandwidth, bit error ratio) with high accurate.
• Enable detailed performance evaluation of new system software
mechanisms.
BITFLEX: A framework to enable
error permissive computing [1]
Sparse communication
ü 100x-1000x compressed
ü Reduce communication time ~40% more
Topology-aware Allreduce
ü Reduce comm. time up to 45%
ü Reduce power consumption of comm. up to 23%
0
0.01
0.02
0.03
0.04
0.05
0.06
4 8 16 32 64
Comm.time/iter.(s)
Number of processes
Baseline (ring)
Topology-aware (ring-ring)
Topology-aware + Sparse
Simulated result with ABCI-system, 32MB-message,
0.78% sparcification
Accelerating communication for
large-scaler deep learning [3]
Reliable Unreliable Memory
Operating System
Object Analysis and Tracking
Low ß---- Bit-flip tolerance ---à High
Programming Runtime
…
Error
Mitigation
lowerisbetter](https://image.slidesharecdn.com/approx-200217155706/85/Error-Permissive-Computing-1-320.jpg)
Error Permissive Computing
- 1. LogicNetwork Memory ③ System Software (BITFLEX, etc) ② Emulation/Simulation (RAMinate, mesmeric, etc) Applications (Deep Learning, Graph Processing, etc) ① Error Modeling of Devices Error Permissive Computing: a New Approach for Post Moore’s Computer System Design Abstract We are exploring a new concept of error permissive computing that improves the capability and capacity while drastically reducing power consumption. More specifically, we controllably allow hardware errors and develop system software to assure acceptable computational results. For example, an error correction technique can result in increased latency and reduced capacity. By taking a holistic approach across the layers from hardware to software, lightweight and appropriate error correction is performed at the software layer while eliminating general purpose error correction in hardware layer. Ryousei Takano, Takahiro Hirofuchi, Mohamed Wahib, Truong Thao Nguyen, Hiroki Kanezashi, Akram Ben Ahmed National Institute of Advanced Industrial Science and Technology The 2nd R-CCS International Symposium, Kobe, February 2020 References [1] R. Barton, et al. “BITFLEX: A Dynamic Runtime Library for Bit-Level Precision Manipulation and Approximate Computing,” HPC Asia 2020. [2] T. Hirofuchi, et al. “FPGAによる次世代メモリのエミュレーション機構の試作”, IPSJ SIGHPC171, 2019. [3] T. Nguyen, et al. “Topology-aware Sparse Allreduce for Large-scale Deep Learning”, IEEE IPCCC 2019. BITFLEX Full Stack (OpenMP Extension) ADAPT Case Study: Pi Accumulator • We require an attractive means of boosting performance and maintaining accuracy in non- deterministic applications. • Solution: BITFLEX framework incorporated in MCXX compiler. • We propose an extension of OpenMP as follows: #pragma omp nondeter <parameters> Analysis and modeling of bit-flip errors in voltage-driven MRAM • The write error ratio of each memory cell is different due to the variation of magnetic anisotropy (σ). FPGA-based new memory device emulator [2] • Emulate the behavior of new memory devices (latency, bandwidth, bit error ratio) with high accurate. • Enable detailed performance evaluation of new system software mechanisms. BITFLEX: A framework to enable error permissive computing [1] Sparse communication ü 100x-1000x compressed ü Reduce communication time ~40% more Topology-aware Allreduce ü Reduce comm. time up to 45% ü Reduce power consumption of comm. up to 23% 0 0.01 0.02 0.03 0.04 0.05 0.06 4 8 16 32 64 Comm.time/iter.(s) Number of processes Baseline (ring) Topology-aware (ring-ring) Topology-aware + Sparse Simulated result with ABCI-system, 32MB-message, 0.78% sparcification Accelerating communication for large-scaler deep learning [3] Reliable Unreliable Memory Operating System Object Analysis and Tracking Low ß---- Bit-flip tolerance ---à High Programming Runtime … Error Mitigation lowerisbetter