Fault Modeling and Parametric Fault Detection in Analog VLSI Circuits using Discretization

International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
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Fault Modeling and Parametric Fault Detection in Analog VLSI Circuits
using Discretization
Baldev Raj1, G. M. Bhat2, Sandeep Thakur3
1 Associate Professor, Dept. Of Electronics & Communication Engineering, Government College of Engineering &
Technology, Jammu, J & K, India
2Professor,Institute of Engineering and Technology Safapora, USIC, University of Kashmir, J & K, India
3Assistant Professor, Dept. of Electronics & Communication Engineering, Mahatma Gandhi Mission’s College of
Engineering & Technology Kamothe, Maharashtra, India
---------------------------------------------------------------------***--------------------------------------------------------------------
Abstract - In this paper we proposed a method to detects
faults in analog VLSI circuits using discretization. The
area of fault modelling in analog VLSI circuit does not
achieve the same degree as compare to digital fault model.
So there is need of simple analog fault model which works
effectively. As we need more application on one chip the
circuitry of analog VLSI circuit becomes more complicated
so it is very difficult to analyses fault in that circuit. So we
give this method to analysis of fault in analog VLSI circuit.
The all simulation and algorithm are made with the help
of MATLAB/Simulink.
Key Words: Parametric faults, analog VLSI circuit,
discretization, MATLAB.
INTRODUCTION
In present scenario analog VLSI circuits are used in wide
number of application such as multimedia, cellular
communication, digital signal processing and data
acquisition. The testing of analog VLSI circuit is a major
task before designing and fabrication of any product. The
fault detection in analog VLSI circuits is very difficult
task due to complexity nature of analog circuits. There is
no simple fault model for analog VLSI circuits as present
in digital circuits. There are two types of fault model are
present in analog circuits. These are catastrophic fault
model and parametric fault model. In catastrophic, there
is large deviation at output due to large variation in
component values (due to short or open circuit). In
parametric, the component value will change from
nominal value to certain extent. The parametric fault
cause due to change in component value due time and
environment. The parametric fault sometimes cause the
change in output behavior of system sometimes not. But
catastrophic fault change the behavior of circuit
completely. The testing of analog circuits consume 30%
of total manufacturing cost of product [1]. The cost occur
in analog circuits testing due to functional testing
techniques, these require large number of
measurements for test. In this paper we present a analog
fault detector using discretization [2][3][4].
Basic Principle
A large number of analog VLSI circuits can be
represented by linear state variable equations [5][6][7].
For simplicity here we take single output state variable
circuit where the output of every block contain a
capacitor (memory element).The state equation for the
circuit is given by
(1)
is state vector
containing n variable.
Here is derivative with time. The output of the
system is given by y (t).
(2)
By taking Laplace transform we change state variable
equation from time domain to frequency s domain that is
given by
(3)
From these equation we can derive from signal flow
graph [8][9]. Here we taking example of Biquadratic
Filter circuit in Fig 1. & Fig 2. Shown the circuit diagram
and signal flow graph of biquadratic filter circuit. The
biquadratic filter circuit contain three op-amp. First
operational amplifier is inverting op-amp, second is
integrator and third is lossy integrator.

Figure 1: Circuit Diagram of Biquadratic filter
Figure 2: Signal flow graph of Biquadratic filter circuit
By using all the resistor value equal to R and all capacitor
value equal to C. then we have .From Fig. 2
we can write state equation
(4)
By applying bilinear transform we get z transform from s
domain. In bilinear transform
(5)
Here is sampling time.
By using equation (4) and (5) we get
(6)
(7)
So that we can write
(8)
Here is delay. This equation can be write in time
domain
(9)
Here u(t) is input for simulation of biquadratic filter
circuit. And sampling rate is 1/ . And sampling
frequency is .
In biquadratic filter circuit by using R=10k and C=0.02µF
and by using this we get and using
nyquist criterion =0.0001sec.By using these parameter
we find state equation in Z domain.
(10)
By applying sinusoidal input u(t)=0.1sin(2π.500t).We
simulate biquadratic filter circuit.
Modeling of Faults
For the measurement of different fault occur in circuit
one should have complete fault list. There are two types
of faults occur in analog VLSI circuits. These are
parametric fault and catastrophic fault.
Parametric faults occur in circuit due to some
manufacturing defects (change in some parameter like
due to doping level and due to oxide thickness). Due to
parametric faults in circuit the tolerance of component
will vary to certain value. In these types of faults the
circuit output may or may not be changed. Because the
value of component is increase or decrease to certain
value. These type of fault we can remove with the help of
knowing the tolerance of component (ie. If there is some
change in value then how much output of system is
changed).
Catastrophic faults are completely changed the output of
the circuit. These cause the short circuit or open circuit.
These are also called hard fault. Due to these type of fault
the behavior of system changed drastically. These are
random faults.

Figure 3: Biquadratic Filter simulation using MATLAB
Figure 4: Biquadratic filter in discrete form (using
Simulink)
Effects cause by single fault in circuit
When we simulate the circuit with fault the z domain
state equation is assumed as discrete network as shown
in Fig. 4. Here the coefficient of multiplier are
and . These are the elements from and .Single
fault is appears as with multiple faults in discrete circuit.
For example there is fault in . That is the value of is
changed from its original value. The original value of
=10k and due to fault the value is change to =1k.
This fault effect the entire matrices of s domain where
is present. Where as it effects both in z domain that is
and . The change in state equation due to fault occur
in circuit
By in z domain it is given as
Number of states changed due to single fault in circuit.
The major cause of circuit failure is parasitic capacitance.
For example here we consider capacitance effect
which is at negative terminal of operational amplifier
first and output terminal of operational amplifier. Due to
this capacitance faulty state is generated which will
increase the states. Here we represent it as faulty state
( ).
Figure 5: Signal flow graph with increased states
Due to the presence of presence of parasitic capcitance
the state equation is also changed and can be written as.
And in z domain are given below

Figure 6: Response of Biquadratic filter at f=500Hz.
Figure 7: Error between the good and faulty response of
Biquadratic filter circuit
Fault Simulation
Our approach work serially for analog VLSI not like
parallel approaches. Because is not possible to detected
all the faults in the circuit. Here we apply this approach
to the parametric fault occur in the analog VLSI circuit
that is if the value of the component is changes slightly
then the output response of the circuit is changed
completely. So it is very necessary to detect these fault.
Here in first case we assume fault in resistor in the
biquadratic filter. Then with the help of our approach we
detect the response of the good and faulty biquadratic
filter circuit. This approach is applicable to all types of
circuit which we can convert into the signal flow graph.
Our approach is simple and efficient approach as
compare to the methods used now a days.
Implementation of Algorithm
The algorithm for fault modelling and detection is
constructed with the help of MATLAB and Simulink [10].
The entire algorithm to compute fault in circuits is
shown in Fig. 8.With the help of given algorithm we can
easily detect the fault in analog VLSI circuit. In this paper
we applied our algorithm to two circuit first is
Biquadratic filter circuit and second circuit is leap frog
filter circuit both circuit are benchmark circuit. Before
the implementation of testing method, the method
should be applicable to these circuit [11].
Result and Discussion
In this paper fault simulation is done on two benchmark
circuit. In first circuit we consider two parametric fault
in biquadratic filter circuit where as in second circuit
contain only one parametric fault in Leapfrog filter
circuit, both the filter are simulate at different frequency
that is 500Hz for biquadratic filter and 1kHz for leapfrog
filter circuit. Fig. 7 show the response of biquadratic
filter circuit that is we use our algorithm to detect the
parametric fault occur in circuit[12].
Table: 1 Result for Biquadratic Filter Circuit
Sr.
No.
Compo-
nent
Original
Value
Faulty
Value
Freq.
(Hz)
Result
1. 10K 15K 1.00 Y
2. 10K 5K 1.00 Y
3. 10K 15K 1.00 N
4. 10K 5K 1.00 N
5. 10K 15K 1.00 Y
6. 10K 5K 1.00 Y
7. 10K 15K 1.00 N
8. 10K 5K 1.00 Y
9. 10K 15K 1.00 Y
10. 10K 5K 1.00 Y
11. 10K 15K 1.00 Y
12. 10K 5K 1.00 Y
13. 0.01µF 0.02 µF 1.00 N
14. 0.01µF 0.005 µF 1.00 N
15 0.01µF 0.02 µF 1.00 N
16. 0.01µF 0.005 µF 1.00 N
Second filter leapfrog filter is simulated with the help of
our approach by assuming the fault in resistor.in this
case we also assume the parametric fault in circuit. And
by simulation of algorithm at 1 KHz, we detect fault in
circuit.

Figure 8: Algorithm used for fault simulation
Figure 9: Leapfrog Filter circuit diagram
Figure 11: Response of Leapfrog Filter Circuit at f=
1000Hz
Conclusion
We proposed a new approach for fault detection in linear
analog VLSI circuit. This approach is done by discretizing
the circuit in z domain and sampling frequency is chosen
such that we get maximum accuracy. In this paper all the
simulation and calculation for transfer function ,state
equation in s domain as well as z domain are done with
the help of MATLAB and all model for algorithm are
construct with the help of SIMULINK. This approach is
very effective to linear analog VLSI and our proposed
algorithm is applicable to mostly all analog VLSI circuit.
ACKNOWLEDGEMENT
We express our gratitude & appreciation to Dr.
Bhopinder Singh, Dr. Subash Dubey, Dr. Sameru Sharma,
Dr. M. Tariq Banday, Dr. Sarbjeet Singh, Dr. Simmi Dutta,
Er Rouf Ahmed Khan, Er Bharat Mahajan, Er Major Singh,
Ms.Sharda Kumari, Er. Mohit Bharti, Mr. Abhiluv Bharti
and Ms.Kashish Bharti for their technical and moral
support. Last but not least we are thankful to our parents
for their encouragement.
References
[1] L. Milor and A.L. Sangiovanni-
Vincentelli,“Minimizing ProductionTest Time to
Detect Faults in Analog Circuits,” IEEETrans. on
Computer-Aided Design, Vol. 13, pp. 796–813,June
1994.
[2] L. Milor and V. Visvanathan, “Detection of
Catastrophic Faultsin Analog Integrated Circuits,”
IEEE Trans. on Computer-Aided Design,Vol. 8, pp.
114–130, Feb. 1989.

[3] N.B. Hamida and B. Kaminska, “Multiple Fault Analog
Circuit Testing by Sensitivity Analysis,” J. Electronic
Testing: Theoryand Applications, Vol. 4, pp. 331–
343, Nov. 1993.
[4] K.Maggard,P.Karunaratna,C.Stroud,"Built-InSelf Test
for analog circuits in Mixed Signal System,”
Proc.IEEE Southeast Regional Conf.,1999.
[5] A. Chatterjee. Concurrent Error Detection in Linear
Analog and switched-capacitor state variable
systems using continuous checksums. Pmc
IEEE Intl. Test ConI. pp.582-591, 1991.
[6] M.E. Van Valkenburg. Analog Filter Design. Holt,
Rinehart and Winston, 1982.
[7] Seshu, Balabanian. Linear Network Analysis. John
Wiley, 1959.
[8] A. Chatterjee. Checksum-based Concurrent Error
Detection in Linear Analog Systems with second and
higherorders. Pmc IEEE VLSI Test Symp. pp. 286-
291, 1992.
[9] N. Balabanian, T.A. Bickart, and S. Seshu, Electrical
Network Theory, John Wiley & Sons, Inc.1969.
[10] The MathWorks Inc. MATLAB User’s Guide, 2012.
[11] B. Kaminska, K. Arabi, I. Bell, P. Goteti, J. L. Heurtas,
B.Kim,A.Rueda, and M.Soma"Analogand Mixed-Signal
Benchmark Circuits First Release", IEEE International
Test Conference, Washington DC, November 1997.
[12] A.MeixnerandW.Maly,“FaultModelingfortheTestingof
MixedIntegratedCircuits,”Proc.oftheIEEEInt’l.TestCo
nf.,Oct.1991,pp.564–572
BIOGRAPHIES:
Dr. Baldev Raj .He is currently working as
Associate Professor in the Department of
Electronics & Communication
Engineering, Government College of
Engineering & Technology Jammu, India.
He has completed his B.E. from
University of Jammu, M.Tech from IIT Roorkee, MBA
from IGNOU University, New Delhi and PhD from Ecole
Superieure Robert de Sorbon, France. He is having
fourteen years of teaching experience in the field of
Electronics & Communication and has eight publications
in reputed journals & conferences. He is reviewer of
some International Journals.
Dr. G. M. Bhat He is currently working
as Director in the Institute of
Engineering & Technology Safapora,
USIC, Kashmir University. He is having
good experience in teaching, research &
in administration and has more than
fifty publications in reputed journals & conferences.
Er.Sandeep Thakur, He is currently
working as Assistant Professor in the
department of electronics &
communication in Mahatma Gandhi
Mission’s College of Engineering &
Technology, Kamothe Maharashtra,
India. He did his B.E. from Himachal Pradesh University
Shimla and M.Tech from IIT Dhanbad. He is having two
years of teaching experience and has eleven publications
in SCOPUS journals & IEEE conferences.

Fault Modeling and Parametric Fault Detection in Analog VLSI Circuits using Discretization

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