Final paper0

Portable EEG Recording Using a
Lock-In Ampliﬁer
By
Braden Fong
Matthew Harvey
Kirill Lagoutchev
Final Report for ECE 445, Senior Design, Fall 2014
TA: Rishi Ratan
7 May 2014
Project No. 23

Abstract
The lock-in amplifier is an effective method for identifying steady-state visually evoked potentials (SSVEPs). Using
data read by electrodes for electroencephalography (EEG) recording, the signal is filtered and amplified in an analog
circuit. Given that raw EEG is noisy, the circuit removes common noise to provide a better signal-to-noise ratio
(SNR). The lock-in algorithm is implemented in LabVIEW for deployment on a myRIO. The myRIO converts the
analog data and, using two reference signals, determines if the desired frequency is present. Testing shows that
the system is able to extract the signal from a noisy environment within 0.75 Hz of its actual frequency. Further
calibration is required to more accurately detect the signal, but preliminary results are positive.
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Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Statement of Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Project Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.1 Protection Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.2 Instrumentation Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.3 Gain and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.4 Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 myRIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.1 Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.2 Input Analog Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.3 Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.4 Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Design Verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Analog Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.1 Protection Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.2 Instrumentation Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.3 Gain Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 myRIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.1 Reference Signal/Input Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.2 Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.3 Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 Cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2 Labor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 Marketability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 Ethical considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Appendix A Requirement and Veriﬁcation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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1 Introduction
1.1 Statement of Purpose
The majority of current electroencephalograph (EEG) technology is cumbersome and lacks the ability to be
transported easily. Experiments require the subject to remain in the laboratory, while wearing a cap that
is connected to a large amplifier, analog-to-digital converter (ADC), and desktop computer. One possible
application of EEG is towards brain-computer interfacing (BCI), where users control external interfaces with
brain activity. The actual implementation of these devices is currently limited by the technology. Through
the use of modern electronics EEG recording devices can be made smaller. A lock-in is one approach to the
detection of frequency entrained EEG. [1] [2]
1.2 Project Functions
Goals
• Amplify input signal from patient to readable voltage lever for myRIO
• Filter out the different forms of noise observed with EEG signals
• Implement Lock-In technique to find presence of set frequencies within the raw EEG Data
Functions
• Detect steady-state potentials from EEG
• Modulate the reference frequency within 1-45 Hz
Benefits
• Small size to be easier carried on patient
• Reduced cost from comparable EEG amplifiers
• Robust and portable EEG amplifier to allow for testing outside of a lab
• Scalable circuitry to allow custom number of EEG signal channels
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1.3 Block Diagrams
Figure 1: Analog Hardware Block Diagram
Figure 2: Lock-In Ampliﬁer Block Diagram
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2 Design
2.1 Analog
2.1.1 Protection Circuit
The first block in our design had to guarantee a level of electrical protection for the human subject from
discharge due to failing or misperforming components. The design chosen is a tested configuration found as
the input stage of an EEG amplifier detailed in the ModularEEG project[3] . It operates by using BJTs as
voltage limiting elements. Small voltages between a signal and the ground electrodes keep the BJTs off and
result in a very large impedance between the leads. Voltages of magnitude greater than VBEon of about 0.7
V cause the link to become very low impedance, allowing current flow. Often clamping diodes would be used
instead of BJTs for such a voltage limiting function but the allowed range of voltages of this circuit fit nicely
within our allowed range of inputs for the next block. A premade design was chosen because gambling with
subject safety wasn’t an option.
Figure 3: Protection Circuit Diagram
2.1.2 Instrumentation Amplifier
The following block in any biopotential amplifier is an instrumentation amplifier (IAmp). Such an amplifier
has a number of qualities that were essential to the functionality of our complete design. The source
impedance in EEG measurement is variable by person, electrode position and connection quality and is
relatively high in the range of thousands of kilo-ohms. The IAmp’s high input impedance ensures that
a maximal amount of the input voltage signal appears across it and minimizes the impact of unbalanced
impedances between the two signal electrode leads. The body acts as an antenna and receives noise from
surrounding electronic elements, most notably power line noise at 60 Hz. The extremely high common mode
rejection ratio (CMRR) of an IAmp greatly attenuates any signal that appears in equal amplitude and in
phase across both inputs, which is the case for the majority of such noise. An IAmp assembled from operating
amplifiers (opamps) and discrete components can’t provide a CMRR nearly as high as an integrated circuit
(IC) solution, so an off the shelf chip was chosen. In addition off the shelf solutions often offer much lower
noise levels and occupy less space, an important concern in our project. The reference voltage input used to
center the output to an arbitrary value allowed us to implement a single supply design. [4] [5] [6] [7]
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The AD621 IAmp IC was implemented in the project with a minimum of external components [8] . The signal
electrodes (via the Protection Circuit) were AC coupled to the inputs of the IAmp with 0.1µF monolithic
capacitors. This reduced the impact of time and individually varying DC and very low frequency electrode
half-cell potentials. With a gain of 10, output swing of 1.1 – 3.8 V for a 5 V supply and maximum EEG
differential input signal amplitude of 100µV , the output of the Iamp will not be clipped for DC differential
inputs with magnitudes up to (3.8 − 10(0.0001) − 2.5)/10 0.12. The typical half cell potential for the
AgCl electrodes used in testing is 0.22 V, but the variation with the specific electrodes and subjects used
was found to be so small at the inputs of the Iamp as to be undetectable using available instruments. [9]
CMRR = −20log10(
0.366
3.7(13300)
) = 102dB (1)
Figure 4: Instrumentation Amplifier Diagram
2.1.3 Gain and Filtering
EEG signals of interest appear as differential AC signals of amplitudes in the range of 10 − 100µV when
sensed by noninvasive electrodes at the surface of the scalp. Amplification is necessary to bring these signals
into a voltage range comparable to typical input ranges of an analog to digital converter (ADC) of about
1 – 4 V on a 5 V supply. High frequency elements above a typical EEG frequency range of interest of 10
– 50 Hz will cause aliasing in the ADC and must be filtered out. Electrodes used in EEG build up a DC
potential called the half-cell potential across them under normal operating conditions. This potential varies
by contact quality but stays relatively close to a typical level for a given electrode material. The difference
in DC potential between the two signal electrode appears as a DC differential signal at the inputs and is
thus amplified as much as the AC differential EEG signal of interest. Since this difference can be orders
of magnitude greater than the AC differential EEG signal of interest, it must be filtered out. The Gain
and Filtering block accomplishes these requirements through a cascade of four single order active filters,
alternating high and low pass. This arrangement was chosen because attempts at achieving all the required
gain with fewer cascaded elements resulted in input offset too great to allow the required output voltage
swing. Single order filters minimized the number of discrete elements keeping cost and use of printed circuit
board (PCB) space down. [10] [11] [12] [13]
The IAmp and the four high and low pass stages were directly coupled in the Gain and Filtering block.
4

Figure 5: Gain Stage Circuit Diagram
The first stage was a single order active inverting high pass filter with a gain of 2.35 and a cutoff frequency
of 1.16 Hz achieved with 99 and 235 kΩ resistors, a 1.38µF monolithic capacitor and one quarter of an
LM6144 opamp IC [14] . The component values needed to be minimized to reduce thermal noise contri-
bution at this early stage of amplification, but conversely the cutoff frequency needed to be kept low to
increase the frequency range of observable EEG signals and gain needed to be maximized to reduce thermal
noise contribution from circuit elements in following stages. 1.38µF was one of the largest non-polarized
capacitors available at a reasonable cost and dictated the value of one of the resistors. The other resistor
was experimentally chosen to create a balance between gain and average level shifting relative to Vref . [15]
[16]
G =
235k
99k
= 2.37 (2)
fc =
1
2π(99000)(1.38 ∗ 10−6) = 1.16Hz
(3)
Figure 6: High-Pass Filter Frequency Response
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The second stage was a single order active inverting low pass filter with a gain of 14 and a cutoff frequency
of 113.7 Hz achieved with 1 and 14 kΩ resistors, a 0.1µF monolithic capacitor and one quarter of an LM6144
opamp IC. The cutoff frequency was chosen so as to maintain maximally flat magnitude response in the
frequency range of interest up to 50 Hz. The first resistor was chosen to be 1kΩ based on a recommendation
to keep resistor values low, but at least 1kΩ [16]. The second resistor was chosen to create a balance between
gain and average level shifting relative to Vref . The compounded offset errors of the first high and low pass
filters was experimentally found to be 0.4 V. The conclusion was that at least two more stages would be
necessary to realize the goal of 1350 (a factor of 40 more) gain across the complete Gain and Filtering block
and a decision to not push the first high and low pass filters further was made. The resulting cutoff frequency
was deemed acceptable.
G =
13k
1k
= 14 (4)
fc =
1
2π(14000)(0.1 ∗ 10−6) = 113.7Hz
(5)
Figure 7: Low-Pass Filter Frequency Response
The third stage was identical to the first stage excepting the replacement of the 235kΩ resistor with a 180kΩ
one (gain of 1.8). Its purpose was to level shift the signal back down to Vref , provide some gain balanced
with the resulting average output level offset and have an identical cutoff frequency to the first stage. The
lower gain compared with the first high pass filter enabled finer offset control with available resistor values
in the final stage.
G =
180k
99k
= 1.82 (6)
6

fc =
1
2π(99000)(1.38 ∗ 10−6) = 1.16Hz
(7)
Figure 8: High-Pass Filter Frequency Response
The fourth and final stage was identical to the second stage excepting the replacement of the 14kΩ resistor
with at 22kΩ one (gain of 22). Its purpose was to provide the remainder of the needed gain without shifting
the average output level enough for the output to clip. Experimentally the average value with no input to
the whole block was found to be 2.9 V. With a maximum output value of 4.9 V that amounts to a 4 V
output swing which was found to be more than sufficient for a subject with a greater than average EEG
voltage amplitude. The resulting cutoff frequency of 72 Hz was deemed acceptable. The overall gain of the
Gain and Filtering block was calculated to be 1330 or 62.47 dB.
G =
22k
1k
= 22 (8)
fc =
1
2π(22000)(0.1 ∗ 10−6) = 76.3Hz
(9)
Gtot = 2.37 ∗ 14 ∗ 1.82 ∗ 22 = 1, 300 = 62.5dB (10)
2.1.4 Reference Voltage
To enable our circuit to run off a single power supply our design required a block to generate a DC voltage
reference value of half the supply voltage (Vref ). In order to minimize noise on this output which would
propagate through both the IAmp and the Gain and Filtering block a discrete solution was used in datasheet
7

Figure 9: Low-Pass Filter Frequency Response
recommended configuration. The Vref voltage level was buffered using a unity gain amplifier to prevent
current draw on the line from affecting its potential. Only one voltage reference block is needed for multiple
channels. A comparison between space and cost expenditure of the Vref implementation and an additional
power supply is dependent on the exact number of channels - for one channel having two batteries is more
efficient but since increasing channels requires larger batteries for the same period of operation, disposing of a
second power supply becomes ever more attractive. The Vref block was implemented with this consideration
in mind.
The LM4132 in the 2.5 V variety was used to generate a level of half the supply voltage [17] . In accordance
with its datasheet two capacitors were used to reduce noise at its output - a 10µF electrolytic capacitor
placed close to it in between the positive and negative power supply, and a 1.38µF monolithic capacitor
between 2.5 V and negative power supply.
2.2 myRIO
2.2.1 Reference
The reference signal module provides the means for identifying a specific frequency in the input signal.
Many lock-in amplifier designs use a single reference signal, which requires that the reference signal and
input signal be in phase. Since only the frequency of the signal is of interest when detecting SSVEPs, two
reference signals were used. Implementation of two reference signals with a 90 phase difference allows the
system to be phase independent. The first reference signal V1 is
V1 ∝ Vsigcos(φ) = X (11)
And the second reference signal V2 is
V2 ∝ Vsigsin(φ) = Y (12)
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where Vsig is the voltage of the input signal from EEG. The final operation determines the magnitude of
Vsig by using a trigonometric identity. This will eliminate the cosine and sine, and consequently any phase
difference. The magnitude of equations 11 and 12 is calculated as
Vsig = X2 + Y 2 (13)
Without the use of two reference signals with a 90 degree phase differernce, there would be a possibility
of destructively interfering with the input signal. If there is one reference signal that matches frequency
with the input signal and is 180 degrees out of phase, the lock-in amplifier will output a low voltage despite
matching frequencies. Vsig is the final output of the lock-in amplifier.
The reference signals were designed in LabVIEW for production in the myRIO. Since two reference signals
were being used, there were two separate instances of a sinusoid waveform generator in the circuit. One
generates sine wave and the other a cosine wave. Both signal generators are housed in the main while loop.
The loop iteration timing provided the basis for the sampling rate of the signals. The reference signals were
produced with a 250 Hz sampling rate, which is equivalent to the rate at which the analog input was being
read into the myRIO. The loop iteration timing is multiplied by 0.004 to properly match the 250 Hz sampling
rate. After multiplication of the input signal against the reference signals, equations 11 and 12 and filtering
of AC terms, the calculation shown in equation 13 is performed. The output is a voltage proportional to the
input signal magnitude, with no dependence on phase.
2.2.2 Input Analog Signal
The software in LabVIEW required the analog data provided by the circuit to be converted into digital data.
Complications with using an analog-to-digital converter were avoided by using the myRIO as a converter.
LabVIEW provides the capabilities to sample an analog input and feed the data into a data queue. This
data queue can then be used in another loop. To optimize speed, the conversion took place in a loop separate
from the main loop. This set up is called the producer/consumer architecture. The analog input served as
the producer and the main loop served as the consumer.
Analog-to-digital conversion is performed by the myRIO. The output of the hardware fed straight into an
MSP connector with analog-in port C on the myRIO. The positive terminal received the signal and the
negative terminal was connected to ground. In LabVIEW, sampling of the analog data took place in a while
loop outside of the main while loop. Separate loops were used to achieve higher sampling rates and to reduce
any computational delay in the main loop. The analog input loop was able to achieve speeds of about 1 kHz,
which was four times faster than the main loop iteration. Due to this timing difference, the analog input
loop was assigned a delay of 4 ms. The resulting sampling rate of the analog data was 250 Hz. The analog
input loop then feeds the sampled data into a data queue for the main loop to use.
2.2.3 Multiplication
[18] The multiplier receives signals from the input signal module and the reference signal module. In the
multiplier module, these signals are multiplied. Mathematically, the product of two sinusoidal signals contains
frequencies that are the sum and difference of the original signals. When the signals match, one of the terms
becomes constant and generates a DC offset. This multiplication is calculated once for each of the reference
signals. Both signal components, DC offset and sinusoid, are sent out of this module into the low-pass filter
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module.
[19] For example, if the input signal is represented as
V (t) = V0sin(ωt + φ) (14)
And one reference signal is
VR(t) = sin(Ωt) (15)
When the input signal Eqn. 14 and reference signal Eqn. 15 are multiplied
V (t)VR(t) =
V0
2
[cos[(ω − Ω)t + φ] − cos[(ω + Ω)t + φ]] (16)
And when the frequencies match, the first term in equation Eqn. 16 becomes DC, yielding
V (t)VR(t) =
V0
2
[cos(φ) − cos[2Ωt + φ) ω = Ω (17)
The multiplication was designed using a simple multiply function in LabVIEW. The multiply function receives
two inputs and multiplies them together. Since the design uses point-by-point sampling of the reference and
input signals, the multiply function is not require to perform an array or matrix multiplications.
2.2.4 Filtering
The low-pass filter in the lock-in amplifier requires an extremely low cutoff frequency to extract the DC term.
Since the filter was being generated digitally in LabVIEW on the myRIO, achieving a low cutoff frequency
was feasible. In this manner, most AC terms could be filtered out. The filtering stage takes place after the
multiplication. If the reference and input frequencies are not match, both terms will be filtered out. If the
frequencies are a match, only the high frequency will be removed. The DC term will be passed through to
the end of the circuit.
As with all the other components of the software, the filters were also a point-by-point operation. The filter
function collected 250 samples before applying the filter to match the 250 Hz sampling rate of the analog
input. We set the cutoff frequency to be around 1 Hz, which was the frequency difference that the lock-in
amplifier can detect between reference and input frequencies.
After the signal as passed through all the components of the lock-in amplifier, it is then compared to a
threshold value to determine if there is a DC term. If a DC term is present, which is indicative of matching
frequencies, the output voltage should rise above zero and trigger an LED. This value requires calibration to
the user, as the signal strength from user to user varies. For our testing we estimated a threshold of about
0.08 V, but further calibration is needed to receive accurate results.
10

3 Design Verification
3.1 Analog Hardware
3.1.1 Protection Circuit
To verify the protection circuit worked, a function generator was attached to the input of the circuit, while
an oscilloscope was measuring the input and output waveforms. The protection circuit should limit the
maximum voltage across the electrodes of the patient. Below are the results that confirm a successful
circuit. Fig. 10 show the input wave in green and the output waveform in yellow. It is clear the output
waveform clips the voltage off at 0.6 V even with an input voltage of 1.5V
Table 1: Add caption
Input Voltage Output Voltage
3V 1.2V
Figure 10: Protection Circuit Waveform
3.1.2 Instrumentation Amplifier
To test the instrumentation amplifier, a common signal from the function generator was input to both inputs
of the AD621. The amplitude of the signal that was fed to the IAmp was 3V pk − pk. Ideally, the entire
signal would be rejected by the amplifier. The output of the signal was passed through the amplification
stage so the output could be read on an oscilloscope and can be seen in Fig. 11. The output signal is in
green. The amplitude of the signal is 366mV after an amplification of 13,300. The measured CMRR was
102dB.
11

Table 2: Protection Circuit Test Data
Input Voltage Amplitude Expected Output Voltage
Amplitude
Actual Output Voltage
Amplitude
(after amplification)
3 V 0V 366 mV
Figure 11: IAmp Test Waveform
3.1.3 Gain Stage
The gain stage was tested by using a function generator to input a signal with amplitude of 2mV. The output
waveform was measured on the oscilloscope to confirm an amplification of 1,330 from the gain stage. As
seen in Tab. 3, the output amplitude is not quite as expected. This is a result of non-precision resistors used
within the gain stages.
Table 3: IAmp Test Data
Input Voltage Expected Output Voltage Actual Output Voltage
(without IAmp)
2mV 2.6V 2.27V
3.2 myRIO
3.2.1 Reference Signal/Input Signal
Both the reference signals and the input signal were verified using the same method. Each were probed with
a time domain graph and a frequency domain graph. Using a function generator to create an input signal,
the data read by the myRIO was displayed. Since the frequency and amplitude of the test input signal
were known, verification by the graphs was relatively simple. The reference signals were tested in a similar
manner. The only difference is that the reference signals are generated internally through LabVIEW.
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Figure 12: Gain Stage Test Waveform
3.2.2 Multiplication
In order to verify that the multiplication was functioning, we used the graphing capabilities found in Lab-
VIEW. We generated a test input signal using LabVIEW and multiplied it with the reference signals.
Frequencies of all the signals were known, and using simple arithmetic we expected certain frequencies to
appear after multiplication. The LabVIEW graph was viewing data from a spectral analysis function also
found in LabVIEW.
Fig. 15 and 18 display the spectral analysis of the multiplication output, clearly demonstrating the two
terms. Figure 13 illustrates when the frequencies match with a frequency of 6 Hz, resulting in a DC term.
Neither peak is at 0 Hz in figure 16 , which is caused by non-matching frequencies of 6 Hz and 10 Hz. These
results were expected and verified through comparison with a MATLAB simulation in Fig. 14 and 17.
Able to achieve cutoff frequency of about 0.75 Hz. Verified by generating an input signal and lowering the
frequency until the lock-in could not differentiate between the frequencies. Below a difference of about 0.75
Hz between the reference and input frequencies, the lock-in amplifier indicated a match. This problem can
be solved using a higher order filter, but at the expense of computational speed.
3.2.3 Filtering
Our design was able to achieve cutoff frequency of about 0.75 Hz. It was verified by generating an input signal
in LabVIEW and lowering the frequency until the lock-in could not differentiate between the frequencies.
Below a difference of about 0.75 Hz between the reference and input frequencies, the lock-in amplifier
indicated a match. This problem can be solved using a higher order filter, but at the expense of computational
speed. Filtering was also verified using the spectral analysis of the output waveform. With the frequency
difference above 0.75 Hz, the output of the filter displayed no frequency peaks and the voltage was essential
13

Figure 13: LabView Real-Time
Figure 14: Matlab Simulation
Figure 15: Matched Frequency Input Signal
Figure 16: LabView Real-Time
Figure 17: Matlab Simulation
Figure 18: Mismatched Frequency Input Signal
zero. For frequencies below 0.75 Hz, a low frequency peak was generated signifying a DC oﬀset. Fig. 19
shows the spectral analysis of matched signals at 6 Hz. Clearly there is a large peak around 0 Hz. This
corresponds to the output shown in Fig. 20. This cases veriﬁes the spectral analysis in the LabVIEW in
Fig. 22.
14

Figure 19: Matlab FFT Simulation Figure 20: Matlab Time Simulation
Figure 21: Matched Frequency Output Signal
Figure 22: LabView Real-Time Output
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4 Cost
4.1 Parts
Table 4: Parts Costs
Part Part Number Quantity Unit Cost ($) Cost ($)
Resistors - 15 0.10 1.50
Capacitors - 7 0.10 0.7
Transistors - 4 0.33 1.32
I-Amp INA155 1 3.24 3.24
Op Amp LM6144 1 6.85 6.85
myRIO NI myRIO - 1900 1 250.00 250.00
EEG Electrodes WBT-DSC 1- (10/pkg) 70.00 70.00
EEG equipment - - 100.00 100.00
Voltage Reference LM4132 1 2.87 2.87
PCB - 1 33.00 33.00
Total - - - 469.56
4.2 Labor
Table 5: Labor Costs
Name Hourly Rate Total Hours
Invested
Total ($)
Braden Fong $32.00 150 $12,000
Matthew Harvey $32.00 150 $12,000
Kirill Lagoutchev $32.00 150 $12,000
Total - - $ 36,000
16

5 Conclusion
5.1 Marketability
Currently, there is an emerging market for a portable EEG amplifier. The current technology on the market
has not has not quite met the demands of the research market. Emotiv is the biggest commercial device
currently, but researchers in the field are not satisfied with the performance of the device. That being said
we believe if our product was to be cleaned up and packaged correctly, it would be able to grasp part of the
market share.
The versatility of our product really makes it attractive to potential customers. The amplification circuit
can be sold separately from the lock-in amplifier for customers who have a specific software for their given
applications. In addition, the customer can design their order to whatever channel requirements they have.
The myRIO allows for us to sell a complete package lock-in amplifier to customers. It also has the ability
to be modified into a raw data recording devices as well as many other things with the power of LabView.
The product can even be modified to meet the requirements of almost any application a customer has. We
believe this type of versatility puts us ahead of the competition.
5.2 Ethical considerations
The biggest ethical consideration for this project was to have the safety of potential patients of this product
on the forefront of the design. After some careful research, the protection circuit was decided on to protect
patients from potential electrical shock. Also, research was done to ensure an original design to the analog
circuitry.
5.3 Future work
For this specific project, we will be completing a compact and optimized channel circuit design on a PCB
for our current customer. This will allow the customer to be able to use the product immediately. By the
time the product is ready to give to the customer, the myRIO will include a battery pack to enhance the
portability. Finally, a easy to read user manual will be included so the customer will not have to contact us
as much for technical support.
17

References
[1] “DIY EEG Circuit,” Online. [Online]. Available: http://www.instructables.com/id/
DIY-EEG-and-ECG-Circuit/?ALLSTEPS
[2] J. H. Nagel, The Biomedical Engineering Handbook, 2nd ed., Boca Raton: CRC Press LLC, 2000.
[3] “The ModularEEG,” Online. [Online]. Available: http://openeeg.sourceforge.net/doc/modeeg/modeeg.
html
[4] C. Kitchin, “Appling Instrumentation Amplifier Effectively – The Importance of an Input Ground
Return,” Datasheet, 2005.
[5] R. Mancini, “Op Amps for Everyone,” Texas Insturments, Tech. Rep., Aug 2002.
[6] C. Kitchin and L. Counts, “A Designers Guide to Instrumentation Amplifiers,” Analog Devices, Nor-
wood, MA, Tech. Rep., 2006.
[7] I. Hokajarvi, “Electrode Contact Impedance and Biopential Signal Quality,” Tampere University of
Technology, month = Dec, year = 2011,, Tech. Rep.
[8] “Low Drift, Low Power Instrumentation Amplifier: AD621,” Datasheet, 2001.
[9] M. Stitt, “AC Coupling Instrumentation and Difference Amplifiers,” Datasheet, Tucson, AZ.
[10] “Single-Supply Om Amp Design Techniques,” Datasheet, Mar 2001.
[11] C. Fonstad, “Lecture 19 - Differential Amplifier Stages,” Classnotes, Cambridge, MA: MIT OpenCourse-
Ware, Nov 2011.
[12] C. Wells, “Operational Amplifier Stability,” Feb 2012.
[13] J. Karki, “Active Low-Pass Filter Design,” Texas Instruments, Tech. Rep., Sep 2002.
[14] “LM6142/LM6144 17 MHz Rail-to-Rail Input-Output Operation Amplifiers,” Datasheet, Mar 2013.
[15] “Filters,” Online. [Online]. Available: http://www.electronics-tutorials.ws/category/filter
[16] “Filters Design and Analysis,” Online. [Online]. Available: http://sim.okawa-denshi.jp/en/Fkeisan.htm
[17] “LM4132 SOT-23 Precision Low Dropout Voltage Reference,” Datasheet, Apr 2013.
[18] “SR810 DSP Lock-In Amplifier,” Datasheet, Stanford Research Systems, 2014. [Online]. Available:
http://www.thinksrs.com/downloads/PDFs/Manuals/SR810m.pdf
[19] G. Armen, “Phase sensitive detection: the lock-in amplifier,” University of Tennessee, Knoxville, TN,
Tech. Rep.
18

Appendix A Requirement and Verification Table
Requirements Verifications Verified?
Protection Circuit
1. Limit of input and output voltage differ-
ence between signal electrode and reference
electrode is less than 1 V.
1. Supply with a current-limited power supply
and display voltage on an oscilloscope.
Y
Instrumentation Amplifier
1. Provide a voltage of 2.5 ± 0.1V 1. Display voltage on oscilloscope. Y
2. Maximum current draw of 2.1 mA from
unity gain buffer.
2. Configure power supply to provide 2.1 mA.
Connect supply to output of buffer. Verify on
oscilloscope that voltage remains at 2.5±0.1V .
Y
1. For common DC input voltage levels on
both inputs between 0-5 V relative to the neg-
ative supply, the output is within 1V of refer-
ence voltage.
1. Supply with a current-limited power supply
and display voltage on an oscilloscope.
Y
2. The magnitude of the output voltage re-
mains below 2.49 V relative to reference volt-
age value for a common mode DC input be-
tween 0.5-4.5 V relative to battery ground.
2. Use signal generator to create input signal
and verify voltage on oscilloscope.
Y
3. Output gain due to a AC differential input
with a bandwidth of 1 MHz is below 22 dB,
and with a bandwidth of 60 Hz is between 18-
22 dB.
3. Sweep frequency using signal generator and
monitor relative gain on oscilloscope.
Y
4. Output stays within 0.1 of reference voltage
level for common AC noise input.
4. Generate noise with a maximum magni-
tude of 2.5 V from reference voltage and view
output on oscilloscope.
Y
19

High-Pass Filters
1. The output voltage level due to a DC input
excitation up to 2.25 V relative to reference
voltage level is within 0.1 V of reference volt-
age after 2 second.
1. Use a signal generator to provide DC input.
Manually adjust voltage and observe settling
time on oscilloscope.
Y
2. For AC input signals between 5-50 Hz of
magnitude of 2.5 V relative to reference volt-
age, each individual output voltage is ampli-
fied with gain of 1.7 ± 0.1.
2. Use a signal generator to provide appropri-
ate input, verify that signal is being amplified.
Y
3. For signal frequencies above 50 Hz, gain
does not exceed 2.
3. Use a signal generator to provide appro-
priate input, verify that signal is not being
amplified by more than 2.
Y
Low-Pass Filters
1. The output voltage level due to a DC input
up to 0.1 V relative to reference voltage level
is within 1.1 V of reference voltage.
1. Use a signal generator to provide DC input.
Verify output voltage on oscilloscope.
Y
2. For AC input signals between 10-50 Hz of
maximum magnitude of 2.5 V relative to ref-
erence voltage, each individual output voltage
is amplified with gain of 10 ± 1.
ate input, verify that signal is being amplified.
Y
3. Falloff rate of output voltage relative to fre-
quency above 200 Hz is at least 15 dB/decade.
ate input, verify on oscilloscope that signal is
being attenuated above 200 Hz.
Y
4. For frequencies in the range of 50-200 Hz,
gain is no more than 11.
ate input, verify on oscilloscope that signal is
not being amplified by more than 11.
Y
Analog Signal Chain
1. In presence of common mode noise with a
maximum magnitude of 1 V and a differential
input signal with maximum magnitude higher
than 10 V, the total SNR is at most .
1. Generate a noisy signal using the myRIO.
Verify on an oscilloscope that the common
noise is being reduced and the signal is being
amplified.
Y
2. Output voltage amplitude lies in the range
of 0.05-4.5 V due to a AC input voltage be-
tween 10 − 200µV .
2. Use signal generator to provide AC input
and verify on oscilloscope that it is being am-
plified.
Y
3. With an input of zero relative to voltage
reference level, the output is within 0.1 V of
the reference.
3. With no input connected, verify on an os-
cilloscope that the output is near the reference
voltage.
Y
20

Reference Signal Module
1. Frequency of actual signal is within 0.1 Hz
of set frequency.
2. Frequency can be modulated in the
10-50 Hz range.
3. There should be two reference signals
with a phase difference of 90 degrees.
1. To ensure the internal signal generated by
the myRIO meets this requirement, the ref-
erence signals will be output though separate
channels and measured with an oscilloscope.
The following measurements will be done to
compare and verify the requirements. Fre-
quency measurements Frequecy reange Phase
angle difference
Y
4. Matching of frequencies should be phase
independent.
4. Create test input signal in LabVIEW with
control of phase. Vary phase and verify no
change in output.
Y
Multiplier Module
1. Produce two sinusoids with frequencies
equal to the sum and difference of the input
and reference signal ±0.5Hz.
1. Display the frequency response of the mul-
tiplier output on LabVIEW. Verify there are
two peaks with the appropriate frequency
Y
Digital Low-Pass Filter Module
1. Signals with frequencies above 0.75 Hz
should be output
2. Frequencies below 0.75 ± 0.05Hz are
passed through the filter.
1. Display frequency response on LabVIEW.
Verify that frequencies above 0.2 Hz are in the
stopband.
Y
21

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